Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T1 T4 T8 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T1 T4 T8 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T8
0	1	Covered	T1,T4,T8
1	0	Covered	T8,T22,T83

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57238313	9072	0	0
CascadeEffAonToRstPorAboveRise_A	57238313	9072	0	0
CascadeEffAonToRstPorIoAboveFall_A	54946574	9072	0	0
CascadeEffAonToRstPorIoAboveRise_A	54946574	9072	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27474693	9072	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27474693	9072	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13736990	9072	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13736990	9072	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27474271	9072	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27474271	9072	0	0
CascadeLcToLcAboveFall_A	57238313	22609	0	0
CascadeLcToLcAboveRise_A	57238313	22609	0	0
CascadeLcToLcAonAboveFall_A	1734894	22609	0	0
CascadeLcToLcAonAboveRise_A	1734894	22609	0	0
CascadeLcToLcShadowedAboveFall_A	57238313	22609	0	0
CascadeLcToLcShadowedAboveRise_A	57238313	22609	0	0
CascadePorToAonAboveFall_A	1734894	7194	0	0
CascadeSysToSysAboveFall_A	57238313	22609	0	0
CascadeSysToSysAboveRise_A	57238313	22609	0	0
ScanRstToAonRise_A	1734894	227	0	0
StablePorToAonRise_A	1734894	9072	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12238440	22609	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12238440	22609	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12238440	22609	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12238440	22609	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13736990	22609	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13736990	22609	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12238440	22609	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12238440	22609	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12238440	22609	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12238440	22609	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	9072	0	0
T1	22413	2	0	0
T2	21425	2	0	0
T3	26714	1	0	0
T4	14900	2	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	22	0	0
T9	18864	2	0	0
T10	8310	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	9072	0	0
T1	22413	2	0	0
T2	21425	2	0	0
T3	26714	1	0	0
T4	14900	2	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	22	0	0
T9	18864	2	0	0
T10	8310	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	9072	0	0
T1	21516	2	0	0
T2	20567	2	0	0
T3	25644	1	0	0
T4	14305	2	0	0
T5	26928	1	0	0
T6	23221	8	0	0
T7	6905	1	0	0
T8	140417	22	0	0
T9	18109	2	0	0
T10	7978	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	9072	0	0
T1	21516	2	0	0
T2	20567	2	0	0
T3	25644	1	0	0
T4	14305	2	0	0
T5	26928	1	0	0
T6	23221	8	0	0
T7	6905	1	0	0
T8	140417	22	0	0
T9	18109	2	0	0
T10	7978	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	9072	0	0
T1	10757	2	0	0
T2	10283	2	0	0
T3	12822	1	0	0
T4	7153	2	0	0
T5	13463	1	0	0
T6	11615	8	0	0
T7	3452	1	0	0
T8	70218	22	0	0
T9	9054	2	0	0
T10	3988	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	9072	0	0
T1	10757	2	0	0
T2	10283	2	0	0
T3	12822	1	0	0
T4	7153	2	0	0
T5	13463	1	0	0
T6	11615	8	0	0
T7	3452	1	0	0
T8	70218	22	0	0
T9	9054	2	0	0
T10	3988	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	9072	0	0
T1	5379	2	0	0
T2	5140	2	0	0
T3	6410	1	0	0
T4	3575	2	0	0
T5	6731	1	0	0
T6	5808	8	0	0
T7	1726	1	0	0
T8	35107	22	0	0
T9	4525	2	0	0
T10	1993	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	9072	0	0
T1	5379	2	0	0
T2	5140	2	0	0
T3	6410	1	0	0
T4	3575	2	0	0
T5	6731	1	0	0
T6	5808	8	0	0
T7	1726	1	0	0
T8	35107	22	0	0
T9	4525	2	0	0
T10	1993	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	9072	0	0
T1	10757	2	0	0
T2	10284	2	0	0
T3	12822	1	0	0
T4	7151	2	0	0
T5	13463	1	0	0
T6	11612	8	0	0
T7	3452	1	0	0
T8	70209	22	0	0
T9	9054	2	0	0
T10	3989	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	9072	0	0
T1	10757	2	0	0
T2	10284	2	0	0
T3	12822	1	0	0
T4	7151	2	0	0
T5	13463	1	0	0
T6	11612	8	0	0
T7	3452	1	0	0
T8	70209	22	0	0
T9	9054	2	0	0
T10	3989	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	22609	0	0
T1	672	6	0	0
T2	641	2	0	0
T3	801	21	0	0
T4	445	6	0	0
T5	841	1	0	0
T6	728	8	0	0
T7	215	1	0	0
T8	4434	51	0	0
T9	565	6	0	0
T10	249	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	22609	0	0
T1	672	6	0	0
T2	641	2	0	0
T3	801	21	0	0
T4	445	6	0	0
T5	841	1	0	0
T6	728	8	0	0
T7	215	1	0	0
T8	4434	51	0	0
T9	565	6	0	0
T10	249	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	7194	0	0
T1	672	1	0	0
T2	641	21	0	0
T3	801	1	0	0
T4	445	1	0	0
T5	841	1	0	0
T6	728	8	0	0
T7	215	1	0	0
T8	4434	8	0	0
T9	565	1	0	0
T10	249	3	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57238313	22609	0	0
T1	22413	6	0	0
T2	21425	2	0	0
T3	26714	21	0	0
T4	14900	6	0	0
T5	28050	1	0	0
T6	24186	8	0	0
T7	7193	1	0	0
T8	146266	51	0	0
T9	18864	6	0	0
T10	8310	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	227	0	0
T8	4434	1	0	0
T9	565	0	0	0
T10	249	0	0	0
T11	319	0	0	0
T12	432	0	0	0
T13	3680	0	0	0
T24	732	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T50	208	0	0	0
T56	329	0	0	0
T60	1183	0	0	0
T76	0	1	0	0
T83	0	1	0	0
T87	0	3	0	0
T88	0	7	0	0
T100	0	1	0	0
T101	0	2	0	0
T140	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	9072	0	0
T1	672	2	0	0
T2	641	2	0	0
T3	801	1	0	0
T4	445	2	0	0
T5	841	1	0	0
T6	728	8	0	0
T7	215	1	0	0
T8	4434	22	0	0
T9	565	2	0	0
T10	249	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	22609	0	0
T1	5379	6	0	0
T2	5140	2	0	0
T3	6410	21	0	0
T4	3575	6	0	0
T5	6731	1	0	0
T6	5808	8	0	0
T7	1726	1	0	0
T8	35107	51	0	0
T9	4525	6	0	0
T10	1993	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	22609	0	0
T1	5379	6	0	0
T2	5140	2	0	0
T3	6410	21	0	0
T4	3575	6	0	0
T5	6731	1	0	0
T6	5808	8	0	0
T7	1726	1	0	0
T8	35107	51	0	0
T9	4525	6	0	0
T10	1993	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12238440	22609	0	0
T1	5186	6	0	0
T2	5099	2	0	0
T3	5167	21	0	0
T4	3337	6	0	0
T5	6641	1	0	0
T6	5451	8	0	0
T7	1659	1	0	0
T8	29606	51	0	0
T9	4379	6	0	0
T10	1903	2	0	0