Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T1 T4 T5 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T1 T4 T5 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T4,T5,T10
1	0	Covered	T5,T41,T42

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51376637	8199	0	0
CascadeEffAonToRstPorAboveRise_A	51376637	8199	0	0
CascadeEffAonToRstPorIoAboveFall_A	49319998	8199	0	0
CascadeEffAonToRstPorIoAboveRise_A	49319998	8199	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24660639	8199	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24660639	8199	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12330029	8199	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12330029	8199	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24660621	8199	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24660621	8199	0	0
CascadeLcToLcAboveFall_A	51376637	20726	0	0
CascadeLcToLcAboveRise_A	51376637	20726	0	0
CascadeLcToLcAonAboveFall_A	1556845	20726	0	0
CascadeLcToLcAonAboveRise_A	1556845	20726	0	0
CascadeLcToLcShadowedAboveFall_A	51376637	20726	0	0
CascadeLcToLcShadowedAboveRise_A	51376637	20726	0	0
CascadePorToAonAboveFall_A	1556845	6555	0	0
CascadeSysToSysAboveFall_A	51376637	20726	0	0
CascadeSysToSysAboveRise_A	51376637	20726	0	0
ScanRstToAonRise_A	1556845	197	0	0
StablePorToAonRise_A	1556845	8199	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10985983	20726	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10985983	20726	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10985983	20726	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10985983	20726	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12330029	20726	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12330029	20726	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10985983	20726	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10985983	20726	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10985983	20726	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10985983	20726	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	8199	0	0
T1	26093	2	0	0
T2	15177	2	0	0
T3	20319	1	0	0
T4	18395	2	0	0
T5	89958	21	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	8199	0	0
T1	26093	2	0	0
T2	15177	2	0	0
T3	20319	1	0	0
T4	18395	2	0	0
T5	89958	21	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	8199	0	0
T1	25045	2	0	0
T2	14570	2	0	0
T3	19506	1	0	0
T4	17659	2	0	0
T5	86391	21	0	0
T6	28794	10	0	0
T7	32044	1	0	0
T8	35309	1	0	0
T9	19539	2	0	0
T10	12435	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	8199	0	0
T1	25045	2	0	0
T2	14570	2	0	0
T3	19506	1	0	0
T4	17659	2	0	0
T5	86391	21	0	0
T6	28794	10	0	0
T7	32044	1	0	0
T8	35309	1	0	0
T9	19539	2	0	0
T10	12435	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	8199	0	0
T1	12523	2	0	0
T2	7284	2	0	0
T3	9752	1	0	0
T4	8828	2	0	0
T5	43205	21	0	0
T6	14396	10	0	0
T7	16020	1	0	0
T8	17654	1	0	0
T9	9769	2	0	0
T10	6217	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	8199	0	0
T1	12523	2	0	0
T2	7284	2	0	0
T3	9752	1	0	0
T4	8828	2	0	0
T5	43205	21	0	0
T6	14396	10	0	0
T7	16020	1	0	0
T8	17654	1	0	0
T9	9769	2	0	0
T10	6217	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	8199	0	0
T1	6262	2	0	0
T2	3641	2	0	0
T3	4875	1	0	0
T4	4414	2	0	0
T5	21590	21	0	0
T6	7200	10	0	0
T7	8010	1	0	0
T8	8825	1	0	0
T9	4884	2	0	0
T10	3108	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	8199	0	0
T1	6262	2	0	0
T2	3641	2	0	0
T3	4875	1	0	0
T4	4414	2	0	0
T5	21590	21	0	0
T6	7200	10	0	0
T7	8010	1	0	0
T8	8825	1	0	0
T9	4884	2	0	0
T10	3108	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	8199	0	0
T1	12524	2	0	0
T2	7284	2	0	0
T3	9752	1	0	0
T4	8829	2	0	0
T5	43193	21	0	0
T6	14398	10	0	0
T7	16020	1	0	0
T8	17654	1	0	0
T9	9769	2	0	0
T10	6216	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	8199	0	0
T1	12524	2	0	0
T2	7284	2	0	0
T3	9752	1	0	0
T4	8829	2	0	0
T5	43193	21	0	0
T6	14398	10	0	0
T7	16020	1	0	0
T8	17654	1	0	0
T9	9769	2	0	0
T10	6216	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	20726	0	0
T1	782	6	0	0
T2	453	2	0	0
T3	608	17	0	0
T4	550	6	0	0
T5	2790	50	0	0
T6	903	10	0	0
T7	999	1	0	0
T8	1103	1	0	0
T9	610	2	0	0
T10	387	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	20726	0	0
T1	782	6	0	0
T2	453	2	0	0
T3	608	17	0	0
T4	550	6	0	0
T5	2790	50	0	0
T6	903	10	0	0
T7	999	1	0	0
T8	1103	1	0	0
T9	610	2	0	0
T10	387	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	6555	0	0
T1	782	1	0	0
T2	453	13	0	0
T3	608	1	0	0
T4	550	1	0	0
T5	2790	13	0	0
T6	903	10	0	0
T7	999	1	0	0
T8	1103	1	0	0
T9	610	20	0	0
T10	387	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51376637	20726	0	0
T1	26093	6	0	0
T2	15177	2	0	0
T3	20319	17	0	0
T4	18395	6	0	0
T5	89958	50	0	0
T6	30003	10	0	0
T7	33378	1	0	0
T8	36782	1	0	0
T9	20354	2	0	0
T10	12950	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	197	0	0
T5	2790	1	0	0
T6	903	0	0	0
T7	999	0	0	0
T8	1103	0	0	0
T9	610	0	0	0
T10	387	0	0	0
T11	287	1	0	0
T12	561	0	0	0
T15	907	0	0	0
T24	177	0	0	0
T42	0	2	0	0
T50	0	4	0	0
T61	0	4	0	0
T68	0	1	0	0
T86	0	1	0	0
T103	0	2	0	0
T112	0	2	0	0
T140	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	8199	0	0
T1	782	2	0	0
T2	453	2	0	0
T3	608	1	0	0
T4	550	2	0	0
T5	2790	21	0	0
T6	903	10	0	0
T7	999	1	0	0
T8	1103	1	0	0
T9	610	2	0	0
T10	387	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	20726	0	0
T1	6262	6	0	0
T2	3641	2	0	0
T3	4875	17	0	0
T4	4414	6	0	0
T5	21590	50	0	0
T6	7200	10	0	0
T7	8010	1	0	0
T8	8825	1	0	0
T9	4884	2	0	0
T10	3108	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	20726	0	0
T1	6262	6	0	0
T2	3641	2	0	0
T3	4875	17	0	0
T4	4414	6	0	0
T5	21590	50	0	0
T6	7200	10	0	0
T7	8010	1	0	0
T8	8825	1	0	0
T9	4884	2	0	0
T10	3108	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	20726	0	0
T1	5875	6	0	0
T2	3527	2	0	0
T3	3858	17	0	0
T4	4029	6	0	0
T5	16833	50	0	0
T6	6278	10	0	0
T7	7943	1	0	0
T8	8808	1	0	0
T9	4746	2	0	0
T10	2773	6	0	0