Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T67
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T67
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T67
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12330029	13382	0	0
gen_assertions[0].RstEnOn_A	12330029	1003	0	0
gen_assertions[0].RstNOff_A	12330029	13382	0	0
gen_assertions[0].RstNOn_A	12330029	1003	0	0
gen_assertions[1].RstEnOff_A	49319998	12185	0	0
gen_assertions[1].RstEnOn_A	49319998	941	0	0
gen_assertions[1].RstNOff_A	49319998	12185	0	0
gen_assertions[1].RstNOn_A	49319998	941	0	0
gen_assertions[2].RstEnOff_A	24660639	12265	0	0
gen_assertions[2].RstEnOn_A	24660639	981	0	0
gen_assertions[2].RstNOff_A	24660639	12265	0	0
gen_assertions[2].RstNOn_A	24660639	981	0	0
gen_assertions[3].RstEnOff_A	24660621	12300	0	0
gen_assertions[3].RstEnOn_A	24660621	1014	0	0
gen_assertions[3].RstNOff_A	24660621	12300	0	0
gen_assertions[3].RstNOn_A	24660621	1014	0	0
gen_assertions[4].RstEnOff_A	1556845	20283	0	0
gen_assertions[4].RstEnOn_A	1556845	1050	0	0
gen_assertions[4].RstNOff_A	1556845	20283	0	0
gen_assertions[4].RstNOn_A	1556845	1050	0	0
gen_assertions[5].RstEnOff_A	12330029	13617	0	0
gen_assertions[5].RstEnOn_A	12330029	1119	0	0
gen_assertions[5].RstNOff_A	12330029	13617	0	0
gen_assertions[5].RstNOn_A	12330029	1119	0	0
gen_assertions[6].RstEnOff_A	12330029	13668	0	0
gen_assertions[6].RstEnOn_A	12330029	1163	0	0
gen_assertions[6].RstNOff_A	12330029	13668	0	0
gen_assertions[6].RstNOn_A	12330029	1163	0	0
gen_assertions[7].RstEnOff_A	12330029	13717	0	0
gen_assertions[7].RstEnOn_A	12330029	1213	0	0
gen_assertions[7].RstNOff_A	12330029	13717	0	0
gen_assertions[7].RstNOn_A	12330029	1213	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13382	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	6	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	10	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1003	0	0
T3	4875	3	0	0
T4	4414	0	0	0
T5	21590	0	0	0
T6	7200	0	0	0
T7	8010	6	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T11	2296	0	0	0
T12	0	10	0	0
T24	1426	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T38	0	3	0	0
T42	0	6	0	0
T67	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13382	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	6	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	10	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1003	0	0
T3	4875	3	0	0
T4	4414	0	0	0
T5	21590	0	0	0
T6	7200	0	0	0
T7	8010	6	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T11	2296	0	0	0
T12	0	10	0	0
T24	1426	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T38	0	3	0	0
T42	0	6	0	0
T67	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	12185	0	0
T1	25045	4	0	0
T2	14570	0	0	0
T3	19506	15	0	0
T4	17659	4	0	0
T5	86391	28	0	0
T6	28794	0	0	0
T7	32044	5	0	0
T8	35309	0	0	0
T9	19539	0	0	0
T10	12435	4	0	0
T11	0	4	0	0
T12	0	10	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	941	0	0
T7	32044	5	0	0
T8	35309	0	0	0
T9	19539	0	0	0
T10	12435	1	0	0
T11	9191	0	0	0
T12	17970	10	0	0
T13	18974	0	0	0
T14	120704	0	0	0
T15	28942	0	0	0
T24	5708	0	0	0
T38	0	7	0	0
T42	0	5	0	0
T49	0	2	0	0
T67	0	3	0	0
T87	0	1	0	0
T90	0	17	0	0
T91	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	12185	0	0
T1	25045	4	0	0
T2	14570	0	0	0
T3	19506	15	0	0
T4	17659	4	0	0
T5	86391	28	0	0
T6	28794	0	0	0
T7	32044	5	0	0
T8	35309	0	0	0
T9	19539	0	0	0
T10	12435	4	0	0
T11	0	4	0	0
T12	0	10	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49319998	941	0	0
T7	32044	5	0	0
T8	35309	0	0	0
T9	19539	0	0	0
T10	12435	1	0	0
T11	9191	0	0	0
T12	17970	10	0	0
T13	18974	0	0	0
T14	120704	0	0	0
T15	28942	0	0	0
T24	5708	0	0	0
T38	0	7	0	0
T42	0	5	0	0
T49	0	2	0	0
T67	0	3	0	0
T87	0	1	0	0
T90	0	17	0	0
T91	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	12265	0	0
T1	12523	4	0	0
T2	7284	0	0	0
T3	9752	15	0	0
T4	8828	4	0	0
T5	43205	28	0	0
T6	14396	0	0	0
T7	16020	6	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6217	3	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	981	0	0
T7	16020	6	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6217	0	0	0
T11	4595	0	0	0
T12	8985	14	0	0
T13	9487	0	0	0
T14	60363	0	0	0
T15	14468	0	0	0
T24	2855	0	0	0
T38	0	5	0	0
T42	0	5	0	0
T49	0	3	0	0
T67	0	5	0	0
T87	0	2	0	0
T90	0	19	0	0
T92	0	1	0	0
T93	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	12265	0	0
T1	12523	4	0	0
T2	7284	0	0	0
T3	9752	15	0	0
T4	8828	4	0	0
T5	43205	28	0	0
T6	14396	0	0	0
T7	16020	6	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6217	3	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660639	981	0	0
T7	16020	6	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6217	0	0	0
T11	4595	0	0	0
T12	8985	14	0	0
T13	9487	0	0	0
T14	60363	0	0	0
T15	14468	0	0	0
T24	2855	0	0	0
T38	0	5	0	0
T42	0	5	0	0
T49	0	3	0	0
T67	0	5	0	0
T87	0	2	0	0
T90	0	19	0	0
T92	0	1	0	0
T93	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	12300	0	0
T1	12524	5	0	0
T2	7284	0	0	0
T3	9752	15	0	0
T4	8829	4	0	0
T5	43193	28	0	0
T6	14398	0	0	0
T7	16020	8	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6216	3	0	0
T11	0	4	0	0
T12	0	13	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	1014	0	0
T1	12524	1	0	0
T2	7284	0	0	0
T3	9752	0	0	0
T4	8829	0	0	0
T5	43193	0	0	0
T6	14398	0	0	0
T7	16020	8	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6216	0	0	0
T12	0	13	0	0
T38	0	9	0	0
T42	0	5	0	0
T49	0	3	0	0
T67	0	6	0	0
T87	0	4	0	0
T90	0	20	0	0
T93	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	12300	0	0
T1	12524	5	0	0
T2	7284	0	0	0
T3	9752	15	0	0
T4	8829	4	0	0
T5	43193	28	0	0
T6	14398	0	0	0
T7	16020	8	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6216	3	0	0
T11	0	4	0	0
T12	0	13	0	0
T13	0	11	0	0
T14	0	66	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24660621	1014	0	0
T1	12524	1	0	0
T2	7284	0	0	0
T3	9752	0	0	0
T4	8829	0	0	0
T5	43193	0	0	0
T6	14398	0	0	0
T7	16020	8	0	0
T8	17654	0	0	0
T9	9769	0	0	0
T10	6216	0	0	0
T12	0	13	0	0
T38	0	9	0	0
T42	0	5	0	0
T49	0	3	0	0
T67	0	6	0	0
T87	0	4	0	0
T90	0	20	0	0
T93	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	20283	0	0
T1	782	6	0	0
T2	453	2	0	0
T3	608	17	0	0
T4	550	6	0	0
T5	2790	50	0	0
T6	903	3	0	0
T7	999	8	0	0
T8	1103	1	0	0
T9	610	2	0	0
T10	387	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	1050	0	0
T7	999	7	0	0
T8	1103	0	0	0
T9	610	0	0	0
T10	387	0	0	0
T11	287	0	0	0
T12	561	11	0	0
T13	592	0	0	0
T14	3788	0	0	0
T15	907	0	0	0
T24	177	0	0	0
T25	0	1	0	0
T38	0	7	0	0
T42	0	8	0	0
T49	0	5	0	0
T67	0	6	0	0
T87	0	5	0	0
T90	0	17	0	0
T91	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	20283	0	0
T1	782	6	0	0
T2	453	2	0	0
T3	608	17	0	0
T4	550	6	0	0
T5	2790	50	0	0
T6	903	3	0	0
T7	999	8	0	0
T8	1103	1	0	0
T9	610	2	0	0
T10	387	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556845	1050	0	0
T7	999	7	0	0
T8	1103	0	0	0
T9	610	0	0	0
T10	387	0	0	0
T11	287	0	0	0
T12	561	11	0	0
T13	592	0	0	0
T14	3788	0	0	0
T15	907	0	0	0
T24	177	0	0	0
T25	0	1	0	0
T38	0	7	0	0
T42	0	8	0	0
T49	0	5	0	0
T67	0	6	0	0
T87	0	5	0	0
T90	0	17	0	0
T91	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13617	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	10	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	5	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1119	0	0
T7	8010	10	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	1	0	0
T11	2296	0	0	0
T12	4489	7	0	0
T13	4742	0	0	0
T14	30187	0	0	0
T15	7229	0	0	0
T24	1426	0	0	0
T38	0	8	0	0
T42	0	6	0	0
T49	0	6	0	0
T67	0	6	0	0
T87	0	6	0	0
T90	0	16	0	0
T93	0	12	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13617	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	10	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	5	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1119	0	0
T7	8010	10	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	1	0	0
T11	2296	0	0	0
T12	4489	7	0	0
T13	4742	0	0	0
T14	30187	0	0	0
T15	7229	0	0	0
T24	1426	0	0	0
T38	0	8	0	0
T42	0	6	0	0
T49	0	6	0	0
T67	0	6	0	0
T87	0	6	0	0
T90	0	16	0	0
T93	0	12	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13668	0	0
T1	6262	5	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	11	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1163	0	0
T1	6262	1	0	0
T2	3641	0	0	0
T3	4875	0	0	0
T4	4414	0	0	0
T5	21590	0	0	0
T6	7200	0	0	0
T7	8010	11	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T12	0	12	0	0
T25	0	1	0	0
T38	0	11	0	0
T42	0	5	0	0
T49	0	7	0	0
T67	0	7	0	0
T71	0	1	0	0
T87	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13668	0	0
T1	6262	5	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	11	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	12	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1163	0	0
T1	6262	1	0	0
T2	3641	0	0	0
T3	4875	0	0	0
T4	4414	0	0	0
T5	21590	0	0	0
T6	7200	0	0	0
T7	8010	11	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T12	0	12	0	0
T25	0	1	0	0
T38	0	11	0	0
T42	0	5	0	0
T49	0	7	0	0
T67	0	7	0	0
T71	0	1	0	0
T87	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13717	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	12	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1213	0	0
T7	8010	12	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T11	2296	0	0	0
T12	4489	14	0	0
T13	4742	0	0	0
T14	30187	0	0	0
T15	7229	0	0	0
T24	1426	0	0	0
T38	0	10	0	0
T42	0	2	0	0
T49	0	7	0	0
T67	0	9	0	0
T71	0	1	0	0
T87	0	7	0	0
T90	0	16	0	0
T93	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	13717	0	0
T1	6262	4	0	0
T2	3641	0	0	0
T3	4875	16	0	0
T4	4414	4	0	0
T5	21590	29	0	0
T6	7200	0	0	0
T7	8010	12	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	4	0	0
T11	0	4	0	0
T12	0	14	0	0
T13	0	12	0	0
T14	0	78	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12330029	1213	0	0
T7	8010	12	0	0
T8	8825	0	0	0
T9	4884	0	0	0
T10	3108	0	0	0
T11	2296	0	0	0
T12	4489	14	0	0
T13	4742	0	0	0
T14	30187	0	0	0
T15	7229	0	0	0
T24	1426	0	0	0
T38	0	10	0	0
T42	0	2	0	0
T49	0	7	0	0
T67	0	9	0	0
T71	0	1	0	0
T87	0	7	0	0
T90	0	16	0	0
T93	0	15	0	0