Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T60,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T60,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T60,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T60,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13736990	14396	0	0
gen_assertions[0].RstEnOn_A	13736990	1071	0	0
gen_assertions[0].RstNOff_A	13736990	14396	0	0
gen_assertions[0].RstNOn_A	13736990	1071	0	0
gen_assertions[1].RstEnOff_A	54946574	13085	0	0
gen_assertions[1].RstEnOn_A	54946574	982	0	0
gen_assertions[1].RstNOff_A	54946574	13085	0	0
gen_assertions[1].RstNOn_A	54946574	982	0	0
gen_assertions[2].RstEnOff_A	27474693	13135	0	0
gen_assertions[2].RstEnOn_A	27474693	980	0	0
gen_assertions[2].RstNOff_A	27474693	13135	0	0
gen_assertions[2].RstNOn_A	27474693	980	0	0
gen_assertions[3].RstEnOff_A	27474271	13186	0	0
gen_assertions[3].RstEnOn_A	27474271	1019	0	0
gen_assertions[3].RstNOff_A	27474271	13186	0	0
gen_assertions[3].RstNOn_A	27474271	1019	0	0
gen_assertions[4].RstEnOff_A	1734894	22313	0	0
gen_assertions[4].RstEnOn_A	1734894	1068	0	0
gen_assertions[4].RstNOff_A	1734894	22313	0	0
gen_assertions[4].RstNOn_A	1734894	1068	0	0
gen_assertions[5].RstEnOff_A	13736990	14627	0	0
gen_assertions[5].RstEnOn_A	13736990	1124	0	0
gen_assertions[5].RstNOff_A	13736990	14627	0	0
gen_assertions[5].RstNOn_A	13736990	1124	0	0
gen_assertions[6].RstEnOff_A	13736990	14670	0	0
gen_assertions[6].RstEnOn_A	13736990	1165	0	0
gen_assertions[6].RstNOff_A	13736990	14670	0	0
gen_assertions[6].RstNOn_A	13736990	1165	0	0
gen_assertions[7].RstEnOff_A	13736990	14681	0	0
gen_assertions[7].RstEnOn_A	13736990	1179	0	0
gen_assertions[7].RstNOff_A	13736990	14681	0	0
gen_assertions[7].RstNOn_A	13736990	1179	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14396	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	2	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1071	0	0
T3	6410	5	0	0
T4	3575	0	0	0
T5	6731	2	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	1	0	0
T12	3459	0	0	0
T23	0	1	0	0
T35	0	2	0	0
T39	0	1	0	0
T52	0	5	0	0
T53	0	9	0	0
T56	0	1	0	0
T60	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14396	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	2	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1071	0	0
T3	6410	5	0	0
T4	3575	0	0	0
T5	6731	2	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	1	0	0
T12	3459	0	0	0
T23	0	1	0	0
T35	0	2	0	0
T39	0	1	0	0
T52	0	5	0	0
T53	0	9	0	0
T56	0	1	0	0
T60	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	13085	0	0
T1	21516	4	0	0
T2	20567	0	0	0
T3	25644	19	0	0
T4	14305	3	0	0
T5	26928	2	0	0
T6	23221	0	0	0
T7	6905	0	0	0
T8	140417	29	0	0
T9	18109	4	0	0
T10	7978	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	11	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	982	0	0
T5	26928	2	0	0
T6	23221	0	0	0
T7	6905	0	0	0
T8	140417	0	0	0
T9	18109	0	0	0
T10	7978	0	0	0
T11	10258	0	0	0
T12	13839	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T53	0	9	0	0
T56	10546	1	0	0
T60	37913	11	0	0
T84	0	1	0	0
T85	0	9	0	0
T86	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	13085	0	0
T1	21516	4	0	0
T2	20567	0	0	0
T3	25644	19	0	0
T4	14305	3	0	0
T5	26928	2	0	0
T6	23221	0	0	0
T7	6905	0	0	0
T8	140417	29	0	0
T9	18109	4	0	0
T10	7978	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	11	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54946574	982	0	0
T5	26928	2	0	0
T6	23221	0	0	0
T7	6905	0	0	0
T8	140417	0	0	0
T9	18109	0	0	0
T10	7978	0	0	0
T11	10258	0	0	0
T12	13839	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T53	0	9	0	0
T56	10546	1	0	0
T60	37913	11	0	0
T84	0	1	0	0
T85	0	9	0	0
T86	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	13135	0	0
T1	10757	4	0	0
T2	10283	0	0	0
T3	12822	19	0	0
T4	7153	3	0	0
T5	13463	3	0	0
T6	11615	0	0	0
T7	3452	0	0	0
T8	70218	29	0	0
T9	9054	4	0	0
T10	3988	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	10	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	980	0	0
T5	13463	3	0	0
T6	11615	0	0	0
T7	3452	0	0	0
T8	70218	0	0	0
T9	9054	0	0	0
T10	3988	0	0	0
T11	5129	0	0	0
T12	6921	0	0	0
T39	0	3	0	0
T53	0	7	0	0
T56	5272	1	0	0
T60	18956	10	0	0
T79	0	4	0	0
T85	0	9	0	0
T87	0	30	0	0
T88	0	21	0	0
T89	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	13135	0	0
T1	10757	4	0	0
T2	10283	0	0	0
T3	12822	19	0	0
T4	7153	3	0	0
T5	13463	3	0	0
T6	11615	0	0	0
T7	3452	0	0	0
T8	70218	29	0	0
T9	9054	4	0	0
T10	3988	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	10	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474693	980	0	0
T5	13463	3	0	0
T6	11615	0	0	0
T7	3452	0	0	0
T8	70218	0	0	0
T9	9054	0	0	0
T10	3988	0	0	0
T11	5129	0	0	0
T12	6921	0	0	0
T39	0	3	0	0
T53	0	7	0	0
T56	5272	1	0	0
T60	18956	10	0	0
T79	0	4	0	0
T85	0	9	0	0
T87	0	30	0	0
T88	0	21	0	0
T89	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	13186	0	0
T1	10757	5	0	0
T2	10284	0	0	0
T3	12822	19	0	0
T4	7151	3	0	0
T5	13463	5	0	0
T6	11612	0	0	0
T7	3452	0	0	0
T8	70209	29	0	0
T9	9054	5	0	0
T10	3989	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	9	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	1019	0	0
T1	10757	1	0	0
T2	10284	0	0	0
T3	12822	0	0	0
T4	7151	0	0	0
T5	13463	5	0	0
T6	11612	0	0	0
T7	3452	0	0	0
T8	70209	0	0	0
T9	9054	1	0	0
T10	3989	0	0	0
T39	0	5	0	0
T53	0	10	0	0
T56	0	1	0	0
T60	0	9	0	0
T79	0	6	0	0
T85	0	8	0	0
T87	0	22	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	13186	0	0
T1	10757	5	0	0
T2	10284	0	0	0
T3	12822	19	0	0
T4	7151	3	0	0
T5	13463	5	0	0
T6	11612	0	0	0
T7	3452	0	0	0
T8	70209	29	0	0
T9	9054	5	0	0
T10	3989	0	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	67	0	0
T60	0	9	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27474271	1019	0	0
T1	10757	1	0	0
T2	10284	0	0	0
T3	12822	0	0	0
T4	7151	0	0	0
T5	13463	5	0	0
T6	11612	0	0	0
T7	3452	0	0	0
T8	70209	0	0	0
T9	9054	1	0	0
T10	3989	0	0	0
T39	0	5	0	0
T53	0	10	0	0
T56	0	1	0	0
T60	0	9	0	0
T79	0	6	0	0
T85	0	8	0	0
T87	0	22	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	22313	0	0
T1	672	7	0	0
T2	641	2	0	0
T3	801	21	0	0
T4	445	5	0	0
T5	841	6	0	0
T6	728	3	0	0
T7	215	1	0	0
T8	4434	51	0	0
T9	565	7	0	0
T10	249	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	1068	0	0
T1	672	1	0	0
T2	641	0	0	0
T3	801	0	0	0
T4	445	0	0	0
T5	841	5	0	0
T6	728	0	0	0
T7	215	0	0	0
T8	4434	0	0	0
T9	565	1	0	0
T10	249	0	0	0
T39	0	5	0	0
T53	0	12	0	0
T60	0	10	0	0
T79	0	6	0	0
T82	0	1	0	0
T85	0	10	0	0
T86	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	22313	0	0
T1	672	7	0	0
T2	641	2	0	0
T3	801	21	0	0
T4	445	5	0	0
T5	841	6	0	0
T6	728	3	0	0
T7	215	1	0	0
T8	4434	51	0	0
T9	565	7	0	0
T10	249	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1734894	1068	0	0
T1	672	1	0	0
T2	641	0	0	0
T3	801	0	0	0
T4	445	0	0	0
T5	841	5	0	0
T6	728	0	0	0
T7	215	0	0	0
T8	4434	0	0	0
T9	565	1	0	0
T10	249	0	0	0
T39	0	5	0	0
T53	0	12	0	0
T60	0	10	0	0
T79	0	6	0	0
T82	0	1	0	0
T85	0	10	0	0
T86	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14627	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	6	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	12	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1124	0	0
T5	6731	6	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	0	0	0
T12	3459	0	0	0
T39	0	6	0	0
T53	0	14	0	0
T56	2635	1	0	0
T60	9478	12	0	0
T79	0	8	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	14	0	0
T87	0	25	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14627	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	6	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	12	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1124	0	0
T5	6731	6	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	0	0	0
T12	3459	0	0	0
T39	0	6	0	0
T53	0	14	0	0
T56	2635	1	0	0
T60	9478	12	0	0
T79	0	8	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	14	0	0
T87	0	25	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14670	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	7	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1165	0	0
T5	6731	7	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	0	0	0
T12	3459	0	0	0
T39	0	8	0	0
T53	0	11	0	0
T56	2635	1	0	0
T60	9478	12	0	0
T79	0	8	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	12	0	0
T87	0	27	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14670	0	0
T1	5379	4	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	7	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	4	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1165	0	0
T5	6731	7	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	0	0	0
T10	1993	0	0	0
T11	2564	0	0	0
T12	3459	0	0	0
T39	0	8	0	0
T53	0	11	0	0
T56	2635	1	0	0
T60	9478	12	0	0
T79	0	8	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	12	0	0
T87	0	27	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14681	0	0
T1	5379	5	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	9	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	5	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	13	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1179	0	0
T1	5379	1	0	0
T2	5140	0	0	0
T3	6410	0	0	0
T4	3575	0	0	0
T5	6731	9	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	1	0	0
T10	1993	0	0	0
T36	0	1	0	0
T39	0	8	0	0
T53	0	15	0	0
T60	0	13	0	0
T79	0	9	0	0
T85	0	14	0	0
T87	0	25	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	14681	0	0
T1	5379	5	0	0
T2	5140	0	0	0
T3	6410	20	0	0
T4	3575	4	0	0
T5	6731	9	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	29	0	0
T9	4525	5	0	0
T10	1993	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	75	0	0
T60	0	13	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13736990	1179	0	0
T1	5379	1	0	0
T2	5140	0	0	0
T3	6410	0	0	0
T4	3575	0	0	0
T5	6731	9	0	0
T6	5808	0	0	0
T7	1726	0	0	0
T8	35107	0	0	0
T9	4525	1	0	0
T10	1993	0	0	0
T36	0	1	0	0
T39	0	8	0	0
T53	0	15	0	0
T60	0	13	0	0
T79	0	9	0	0
T85	0	14	0	0
T87	0	25	0	0