Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 87.50 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00


87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T1 T3 T4 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00


112                       end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113        1/1              assign wr_en   = we | de;
           Tests:       T1 T7 T10 
114                         if (Mubi) begin : gen_mubi
115                           if (DW == 4) begin : gen_mubi4
116                             assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117                                                                          (we ? prim_mubi_pkg::mubi4_t'(wd) :
118                                                                                prim_mubi_pkg::MuBi4True));
119                           end else if (DW == 8) begin : gen_mubi8
120                             assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121                                                                          (we ? prim_mubi_pkg::mubi8_t'(wd) :
122                                                                                prim_mubi_pkg::MuBi8True));
123                           end else if (DW == 12) begin : gen_mubi12
124                             assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125                                                                           (we ? prim_mubi_pkg::mubi12_t'(wd) :
126                                                                                 prim_mubi_pkg::MuBi12True));
127                           end else if (DW == 16) begin : gen_mubi16
128                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129                                                                           (we ? prim_mubi_pkg::mubi16_t'(wd) :
130                                                                                 prim_mubi_pkg::MuBi16True));
131                           end else begin : gen_invalid_mubi
132                             $error("%m: Invalid width for MuBi");
133                           end
134                         end else begin : gen_non_mubi
135        1/1                assign wr_data = (de ? d : q) & (we ? wd : '1);
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300


42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T3 T4 
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=5,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb

TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T7,T10 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT7,T67,T49
10CoveredT7,T67,T49
11CoveredT1,T2,T3 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T7,T10
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

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