Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13012010	8023	0	0
alert_regwen_rd_A	13012010	4905	0	0
cpu_regwen_rd_A	13012010	5056	0	0
sw_rst_ctrl_n_0_rd_A	13012010	10008	0	0
sw_rst_ctrl_n_1_rd_A	13012010	9681	0	0
sw_rst_ctrl_n_2_rd_A	13012010	9699	0	0
sw_rst_ctrl_n_3_rd_A	13012010	9816	0	0
sw_rst_ctrl_n_4_rd_A	13012010	9860	0	0
sw_rst_ctrl_n_5_rd_A	13012010	10017	0	0
sw_rst_ctrl_n_6_rd_A	13012010	9971	0	0
sw_rst_ctrl_n_7_rd_A	13012010	9952	0	0
sw_rst_regwen_0_rd_A	13012010	5521	0	0
sw_rst_regwen_1_rd_A	13012010	5640	0	0
sw_rst_regwen_2_rd_A	13012010	5619	0	0
sw_rst_regwen_3_rd_A	13012010	5662	0	0
sw_rst_regwen_4_rd_A	13012010	5661	0	0
sw_rst_regwen_5_rd_A	13012010	5738	0	0
sw_rst_regwen_6_rd_A	13012010	5588	0	0
sw_rst_regwen_7_rd_A	13012010	5450	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	8023	0	0
T64	4603	22	0	0
T70	10754	2	0	0
T71	4178	392	0	0
T72	4320	361	0	0
T73	5147	22	0	0
T91	20380	4	0	0
T92	6429	188	0	0
T93	2825	6	0	0
T94	2434	181	0	0
T95	17303	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	4905	0	0
T15	2165	0	0	0
T25	42012	0	0	0
T35	4389	0	0	0
T36	5611	0	0	0
T37	29303	41	0	0
T38	2515	0	0	0
T39	2664	0	0	0
T40	16239	0	0	0
T41	5257	0	0	0
T83	35080	36	0	0
T99	0	46	0	0
T104	0	39	0	0
T107	0	63	0	0
T108	0	271	0	0
T132	0	49	0	0
T133	0	83	0	0
T134	0	46	0	0
T135	0	57	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5056	0	0
T15	2165	0	0	0
T25	42012	0	0	0
T35	4389	0	0	0
T36	5611	0	0	0
T37	29303	28	0	0
T38	2515	0	0	0
T39	2664	0	0	0
T40	16239	0	0	0
T41	5257	0	0	0
T83	35080	20	0	0
T99	0	38	0	0
T104	0	51	0	0
T107	0	56	0	0
T108	0	313	0	0
T132	0	75	0	0
T133	0	57	0	0
T134	0	60	0	0
T135	0	43	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	10008	0	0
T1	5186	8	0	0
T2	5099	0	0	0
T3	5167	79	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	16	0	0
T37	0	42	0	0
T52	0	55	0	0
T77	0	43	0	0
T83	0	31	0	0
T85	0	119	0	0
T86	0	11	0	0
T136	0	66	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9681	0	0
T1	5186	7	0	0
T2	5099	0	0	0
T3	5167	41	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	23	0	0
T37	0	44	0	0
T52	0	58	0	0
T77	0	41	0	0
T83	0	50	0	0
T85	0	95	0	0
T86	0	13	0	0
T136	0	54	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9699	0	0
T1	5186	2	0	0
T2	5099	0	0	0
T3	5167	62	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	21	0	0
T37	0	42	0	0
T52	0	55	0	0
T77	0	52	0	0
T83	0	40	0	0
T85	0	160	0	0
T86	0	12	0	0
T136	0	61	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9816	0	0
T1	5186	1	0	0
T2	5099	0	0	0
T3	5167	31	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	10	0	0
T37	0	42	0	0
T52	0	63	0	0
T77	0	61	0	0
T83	0	55	0	0
T85	0	142	0	0
T86	0	4	0	0
T136	0	58	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9860	0	0
T1	5186	2	0	0
T2	5099	0	0	0
T3	5167	39	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	18	0	0
T37	0	59	0	0
T52	0	49	0	0
T77	0	25	0	0
T83	0	35	0	0
T85	0	145	0	0
T86	0	14	0	0
T136	0	71	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	10017	0	0
T1	5186	4	0	0
T2	5099	0	0	0
T3	5167	49	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	3	0	0
T37	0	31	0	0
T52	0	69	0	0
T77	0	51	0	0
T83	0	38	0	0
T85	0	115	0	0
T86	0	12	0	0
T136	0	80	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9971	0	0
T1	5186	1	0	0
T2	5099	0	0	0
T3	5167	35	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	7	0	0
T37	0	41	0	0
T52	0	65	0	0
T77	0	49	0	0
T83	0	14	0	0
T85	0	114	0	0
T86	0	20	0	0
T136	0	82	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	9952	0	0
T1	5186	12	0	0
T2	5099	0	0	0
T3	5167	24	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	17	0	0
T37	0	42	0	0
T52	0	76	0	0
T77	0	80	0	0
T83	0	31	0	0
T85	0	122	0	0
T86	0	6	0	0
T136	0	78	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5521	0	0
T1	5186	7	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	9	0	0
T37	0	54	0	0
T83	0	24	0	0
T85	0	37	0	0
T86	0	4	0	0
T99	0	34	0	0
T137	0	24	0	0
T138	0	22	0	0
T139	0	11	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5640	0	0
T15	2165	0	0	0
T25	42012	0	0	0
T35	4389	0	0	0
T36	5611	10	0	0
T37	29303	45	0	0
T38	2515	0	0	0
T39	2664	0	0	0
T40	16239	0	0	0
T41	5257	0	0	0
T83	35080	22	0	0
T85	0	17	0	0
T86	0	8	0	0
T99	0	17	0	0
T104	0	36	0	0
T137	0	34	0	0
T138	0	35	0	0
T139	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5619	0	0
T15	2165	0	0	0
T25	42012	0	0	0
T35	4389	0	0	0
T36	5611	8	0	0
T37	29303	51	0	0
T38	2515	0	0	0
T39	2664	0	0	0
T40	16239	0	0	0
T41	5257	0	0	0
T83	35080	40	0	0
T85	0	12	0	0
T86	0	5	0	0
T99	0	44	0	0
T104	0	40	0	0
T137	0	42	0	0
T138	0	29	0	0
T139	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5662	0	0
T1	5186	3	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	3	0	0
T37	0	49	0	0
T83	0	17	0	0
T85	0	25	0	0
T86	0	12	0	0
T99	0	41	0	0
T137	0	24	0	0
T138	0	38	0	0
T139	0	6	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5661	0	0
T1	5186	6	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	5	0	0
T37	0	64	0	0
T83	0	27	0	0
T85	0	16	0	0
T86	0	7	0	0
T99	0	33	0	0
T137	0	27	0	0
T138	0	43	0	0
T139	0	14	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5738	0	0
T1	5186	10	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	2	0	0
T37	0	41	0	0
T83	0	27	0	0
T85	0	15	0	0
T86	0	10	0	0
T99	0	35	0	0
T137	0	34	0	0
T138	0	21	0	0
T139	0	14	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5588	0	0
T1	5186	6	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	3	0	0
T37	0	43	0	0
T83	0	26	0	0
T85	0	10	0	0
T86	0	8	0	0
T99	0	41	0	0
T137	0	21	0	0
T138	0	27	0	0
T139	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012010	5450	0	0
T1	5186	6	0	0
T2	5099	0	0	0
T3	5167	0	0	0
T4	3337	0	0	0
T5	6641	0	0	0
T6	5451	0	0	0
T7	1659	0	0	0
T8	29606	0	0	0
T9	4379	0	0	0
T10	1903	0	0	0
T36	0	13	0	0
T37	0	45	0	0
T83	0	34	0	0
T85	0	14	0	0
T86	0	7	0	0
T99	0	43	0	0
T137	0	32	0	0
T138	0	34	0	0
T139	0	1	0	0