Module Definition
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Module : prim_rst_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync 100.00 100.00



Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 100.00 100.00 100.00 100.00
u_sync 100.00 100.00 100.00

Line Coverage for Module : prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5 
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00

34 end else begin : g_rst_direct 35 1/1 assign async_rst_n = d_i; Tests: T1 T2 T3  36 1/1 assign scan_rst = scan_rst_ni; Tests: T1 T4 T5