Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
81.82	81.82	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	81.82	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.82	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	6	15	71.43

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	6	15	71.43	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	60	1			T17	1		T18	1		T64	1
auto_req_mode	69	1			T8	1		T9	1		T31	1
sw_mode	2922	1			T20	48		T52	1		T36	13

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

104

1

T17

1

T18

1

T8

1

single

42

1

T62

1

T31

1

T122

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1956	1			T17	1		T18	1		T20	48
auto[2]	43	1			T37	1		T41	1		T270	9
auto[3]	89	1			T78	1		T271	42		T79	1
auto[4]	24	1			T173	7		T272	11		T273	5
auto[5]	134	1			T63	3		T126	1		T274	2
auto[6]	131	1			T124	5		T89	2		T32	1
auto[7]	674	1			T24	21		T65	10		T142	10

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	6	15	71.43	6

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[auto_req_mode]	0	1	1
[auto[4] - auto[5]]	[boot_req_mode , auto_req_mode]	--	--	4
[auto[6]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	53	1			T17	1		T18	1		T64	1
auto[1]	auto_req_mode	61	1			T8	1		T9	1		T31	1
auto[1]	sw_mode	1842	1			T20	48		T52	1		T36	13
auto[2]	boot_req_mode	1	1			T275	1		-	-		-	-
auto[2]	sw_mode	42	1			T37	1		T41	1		T270	9
auto[3]	boot_req_mode	1	1			T79	1		-	-		-	-
auto[3]	auto_req_mode	1	1			T78	1		-	-		-	-
auto[3]	sw_mode	87	1			T271	42		T276	6		T277	39
auto[4]	sw_mode	24	1			T173	7		T272	11		T273	5
auto[5]	sw_mode	134	1			T63	3		T126	1		T274	2
auto[6]	auto_req_mode	1	1			T32	1		-	-		-	-
auto[6]	sw_mode	130	1			T124	5		T89	2		T156	21
auto[7]	boot_req_mode	5	1			T38	1		T39	1		T47	1
auto[7]	auto_req_mode	6	1			T99	1		T116	1		T12	1
auto[7]	sw_mode	663	1			T24	21		T65	10		T142	10