Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	591109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5489402

1

T1

8

T2

9

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1561122	1			T1	46		T2	19		T3	4
values[0x0]	2097636	1			T1	6		T2	8		T3	9
values[0x1]	2421753	1			T1	6		T2	2		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	280947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5799564

1

T1

28

T2

16

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25423	1			T14	1		T20	118		T8	4
valid_sources[0x01]	23645	1			T20	133		T36	3		T62	1
valid_sources[0x02]	22709	1			T20	137		T36	10		T13	1
valid_sources[0x03]	26283	1			T20	105		T36	3		T24	778
valid_sources[0x04]	23464	1			T20	163		T36	7		T24	192
valid_sources[0x05]	25687	1			T2	1		T20	100		T36	2
valid_sources[0x06]	23099	1			T20	112		T36	4		T24	273
valid_sources[0x07]	23579	1			T20	144		T36	6		T24	90
valid_sources[0x08]	24285	1			T2	1		T20	102		T24	83
valid_sources[0x09]	22895	1			T2	2		T20	160		T36	3
valid_sources[0x0a]	24531	1			T20	110		T36	3		T24	427
valid_sources[0x0b]	23551	1			T20	131		T24	115		T26	2
valid_sources[0x0c]	24177	1			T20	121		T36	4		T24	409
valid_sources[0x0d]	25803	1			T20	100		T8	2		T36	2
valid_sources[0x0e]	24778	1			T20	102		T36	10		T67	1
valid_sources[0x0f]	22940	1			T20	136		T36	7		T24	94
valid_sources[0x10]	23680	1			T2	1		T14	2		T20	130
valid_sources[0x11]	23445	1			T20	155		T36	1		T24	414
valid_sources[0x12]	23506	1			T2	1		T20	129		T36	6
valid_sources[0x13]	24171	1			T20	138		T36	1		T24	110
valid_sources[0x14]	23711	1			T20	110		T36	3		T62	1
valid_sources[0x15]	22652	1			T2	1		T4	1		T20	131
valid_sources[0x16]	22390	1			T20	147		T36	2		T24	234
valid_sources[0x17]	21892	1			T20	140		T36	3		T67	1
valid_sources[0x18]	24589	1			T20	150		T36	5		T24	314
valid_sources[0x19]	22722	1			T20	155		T36	2		T24	17
valid_sources[0x1a]	23180	1			T20	149		T36	8		T24	205
valid_sources[0x1b]	23520	1			T20	112		T36	1		T24	164
valid_sources[0x1c]	23694	1			T20	123		T36	4		T9	1
valid_sources[0x1d]	23829	1			T20	172		T8	1		T36	7
valid_sources[0x1e]	23469	1			T20	115		T36	1		T24	30
valid_sources[0x1f]	22052	1			T20	102		T36	2		T24	178
valid_sources[0x20]	23239	1			T20	122		T36	3		T150	1
valid_sources[0x21]	23873	1			T20	143		T62	1		T24	113
valid_sources[0x22]	25061	1			T20	139		T36	3		T24	157
valid_sources[0x23]	22944	1			T20	152		T36	8		T24	253
valid_sources[0x24]	23088	1			T20	135		T36	2		T67	1
valid_sources[0x25]	22902	1			T3	2		T14	1		T20	154
valid_sources[0x26]	25568	1			T20	125		T36	5		T24	246
valid_sources[0x27]	24271	1			T20	145		T36	4		T65	3
valid_sources[0x28]	23859	1			T20	104		T8	1		T36	5
valid_sources[0x29]	24882	1			T20	145		T36	3		T13	1
valid_sources[0x2a]	23552	1			T20	87		T36	2		T62	3
valid_sources[0x2b]	22608	1			T14	1		T20	115		T24	129
valid_sources[0x2c]	22366	1			T14	2		T20	74		T36	2
valid_sources[0x2d]	23034	1			T20	155		T36	3		T67	2
valid_sources[0x2e]	26156	1			T14	1		T20	93		T36	9
valid_sources[0x2f]	24795	1			T20	143		T36	1		T62	2
valid_sources[0x30]	23147	1			T20	161		T36	10		T24	804
valid_sources[0x31]	23831	1			T14	1		T20	147		T36	8
valid_sources[0x32]	24537	1			T20	126		T36	2		T24	266
valid_sources[0x33]	23749	1			T20	90		T36	2		T24	283
valid_sources[0x34]	25475	1			T18	1		T20	96		T36	5
valid_sources[0x35]	22089	1			T2	1		T20	98		T8	3
valid_sources[0x36]	23442	1			T14	1		T20	115		T36	2
valid_sources[0x37]	23959	1			T20	131		T36	3		T24	1
valid_sources[0x38]	23640	1			T4	1		T20	132		T8	1
valid_sources[0x39]	24603	1			T20	106		T36	3		T24	230
valid_sources[0x3a]	24627	1			T20	129		T9	3		T24	31
valid_sources[0x3b]	25403	1			T3	1		T20	134		T36	6
valid_sources[0x3c]	22776	1			T20	129		T8	1		T36	3
valid_sources[0x3d]	25764	1			T2	1		T14	3		T20	110
valid_sources[0x3e]	23579	1			T14	1		T4	1		T20	135
valid_sources[0x3f]	23035	1			T20	151		T36	9		T24	373
valid_sources[0x40]	24358	1			T20	139		T36	8		T24	80
valid_sources[0x41]	24449	1			T2	1		T20	115		T36	3
valid_sources[0x42]	22517	1			T20	143		T36	3		T67	2
valid_sources[0x43]	22373	1			T20	108		T36	5		T13	1
valid_sources[0x44]	22317	1			T20	124		T36	2		T24	3
valid_sources[0x45]	26714	1			T20	134		T36	1		T24	75
valid_sources[0x46]	23690	1			T14	1		T20	127		T8	1
valid_sources[0x47]	23519	1			T3	2		T20	158		T36	2
valid_sources[0x48]	21540	1			T3	1		T20	131		T36	19
valid_sources[0x49]	24582	1			T20	129		T36	7		T24	235
valid_sources[0x4a]	26183	1			T4	1		T20	179		T36	12
valid_sources[0x4b]	23699	1			T20	116		T36	4		T13	1
valid_sources[0x4c]	24436	1			T20	163		T24	155		T65	2
valid_sources[0x4d]	23430	1			T20	155		T36	7		T65	1
valid_sources[0x4e]	22400	1			T3	1		T20	139		T36	7
valid_sources[0x4f]	23117	1			T20	101		T24	80		T69	1
valid_sources[0x50]	23513	1			T20	142		T8	2		T36	2
valid_sources[0x51]	26057	1			T3	1		T14	1		T20	147
valid_sources[0x52]	24974	1			T20	143		T8	1		T36	2
valid_sources[0x53]	22881	1			T2	1		T20	112		T36	5
valid_sources[0x54]	22380	1			T20	164		T24	1		T76	1
valid_sources[0x55]	27005	1			T20	153		T36	8		T24	176
valid_sources[0x56]	24818	1			T20	169		T36	1		T24	211
valid_sources[0x57]	24029	1			T2	1		T14	1		T20	153
valid_sources[0x58]	25233	1			T20	133		T36	1		T24	214
valid_sources[0x59]	24123	1			T20	106		T36	2		T24	170
valid_sources[0x5a]	23060	1			T20	135		T24	414		T65	4
valid_sources[0x5b]	24559	1			T20	77		T36	2		T24	123
valid_sources[0x5c]	22662	1			T20	121		T36	7		T24	365
valid_sources[0x5d]	22766	1			T16	4		T20	141		T36	3
valid_sources[0x5e]	23408	1			T20	155		T36	3		T62	2
valid_sources[0x5f]	24194	1			T20	130		T24	594		T68	1
valid_sources[0x60]	23681	1			T20	130		T24	545		T65	1
valid_sources[0x61]	24529	1			T20	171		T24	205		T65	2
valid_sources[0x62]	23232	1			T2	1		T20	87		T36	4
valid_sources[0x63]	26171	1			T20	148		T8	4		T36	4
valid_sources[0x64]	25015	1			T20	113		T36	1		T24	226
valid_sources[0x65]	27391	1			T20	178		T36	4		T67	1
valid_sources[0x66]	22821	1			T2	1		T20	164		T36	1
valid_sources[0x67]	24885	1			T20	79		T24	368		T74	1
valid_sources[0x68]	22844	1			T3	1		T20	107		T36	2
valid_sources[0x69]	24745	1			T4	1		T20	112		T8	1
valid_sources[0x6a]	23565	1			T17	6		T20	135		T24	164
valid_sources[0x6b]	24186	1			T20	112		T36	2		T24	383
valid_sources[0x6c]	23174	1			T2	1		T14	1		T20	125
valid_sources[0x6d]	23987	1			T20	100		T36	5		T24	165
valid_sources[0x6e]	22194	1			T1	58		T4	1		T20	128
valid_sources[0x6f]	24861	1			T20	149		T52	1		T36	4
valid_sources[0x70]	23585	1			T20	141		T36	9		T26	4
valid_sources[0x71]	25969	1			T2	1		T4	1		T20	134
valid_sources[0x72]	23225	1			T20	136		T36	6		T13	2
valid_sources[0x73]	24705	1			T20	129		T36	3		T24	89
valid_sources[0x74]	23920	1			T14	1		T20	128		T36	4
valid_sources[0x75]	23407	1			T14	1		T20	154		T24	176
valid_sources[0x76]	23335	1			T4	2		T20	125		T36	5
valid_sources[0x77]	22490	1			T20	184		T36	3		T24	392
valid_sources[0x78]	25550	1			T2	1		T20	104		T36	4
valid_sources[0x79]	23655	1			T20	105		T36	2		T24	73
valid_sources[0x7a]	23593	1			T20	141		T36	1		T24	46
valid_sources[0x7b]	24982	1			T20	117		T36	6		T9	3
valid_sources[0x7c]	22776	1			T20	125		T36	1		T24	283
valid_sources[0x7d]	23823	1			T3	1		T20	120		T36	1
valid_sources[0x7e]	23377	1			T20	117		T36	5		T67	1
valid_sources[0x7f]	24232	1			T20	162		T36	12		T24	48
valid_sources[0x80]	22633	1			T20	122		T36	2		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1380997

1

T1

3

T2

1

T3

2

values[0x0]

all_enables

biggest_size

2056581

1

T1

3

T2

7

T3

5

values[0x1]

all_enables

biggest_size

2051824

1

T1

2

T2

1

T3

2