Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1719	1			T20	30		T8	5		T36	4
non_zero_bins[1]	1159	1			T20	21		T8	2		T36	7
zero	5595	1			T1	3		T2	2		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	1426	1			T20	16		T52	1		T36	6
gen	3601	1			T1	2		T2	1		T3	2
res	126	1			T8	4		T9	2		T31	4
ins	3320	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5635

1

T2

2

T3

3

T17

2

mubi_true

2838

1

T1

3

T3

1

T14

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4234

1

T1

2

T2

1

T3

2

pass

4239

1

T1

1

T2

1

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	363	1			T20	3		T36	3		T24	2
uni	zero	fail	mubi_true	344	1			T20	9		T52	1		T63	1
uni	zero	pass	mubi_false	366	1			T20	1		T36	1		T24	4
uni	zero	pass	mubi_true	353	1			T20	3		T36	2		T24	3
gen	non_zero_bins[0]	fail	mubi_false	204	1			T20	2		T36	1		T24	1
gen	non_zero_bins[0]	fail	mubi_true	232	1			T20	8		T24	2		T65	1
gen	non_zero_bins[0]	pass	mubi_false	198	1			T20	1		T24	2		T5	1
gen	non_zero_bins[0]	pass	mubi_true	255	1			T20	3		T36	1		T24	1
gen	non_zero_bins[1]	fail	mubi_false	131	1			T20	3		T77	1		T6	1
gen	non_zero_bins[1]	fail	mubi_true	164	1			T20	1		T9	9		T62	1
gen	non_zero_bins[1]	pass	mubi_false	154	1			T20	2		T36	1		T24	1
gen	non_zero_bins[1]	pass	mubi_true	159	1			T20	2		T8	1		T36	1
gen	zero	fail	mubi_false	895	1			T4	1		T20	10		T52	1
gen	zero	fail	mubi_true	177	1			T1	1		T14	2		T20	2
gen	zero	pass	mubi_false	862	1			T2	1		T3	2		T17	2
gen	zero	pass	mubi_true	170	1			T1	1		T20	2		T8	1
res	non_zero_bins[0]	fail	mubi_false	11	1			T110	1		T10	2		T99	1
res	non_zero_bins[0]	fail	mubi_true	20	1			T8	4		T31	1		T34	1
res	non_zero_bins[0]	pass	mubi_false	10	1			T32	2		T57	1		T99	1
res	non_zero_bins[0]	pass	mubi_true	21	1			T31	3		T34	1		T70	1
res	non_zero_bins[1]	fail	mubi_false	9	1			T29	2		T85	2		T181	3
res	non_zero_bins[1]	fail	mubi_true	6	1			T122	1		T81	1		T282	1
res	non_zero_bins[1]	pass	mubi_false	8	1			T29	1		T117	1		T283	1
res	non_zero_bins[1]	pass	mubi_true	12	1			T122	1		T81	1		T112	1
res	zero	fail	mubi_false	5	1			T180	1		T175	1		T284	1
res	zero	fail	mubi_true	11	1			T9	2		T191	1		T118	1
res	zero	pass	mubi_false	8	1			T180	1		T285	1		T286	1
res	zero	pass	mubi_true	5	1			T118	1		T287	1		T286	1
ins	non_zero_bins[0]	fail	mubi_false	197	1			T20	4		T8	1		T36	1
ins	non_zero_bins[0]	fail	mubi_true	196	1			T20	5		T62	1		T63	1
ins	non_zero_bins[0]	pass	mubi_false	192	1			T20	5		T24	1		T25	1
ins	non_zero_bins[0]	pass	mubi_true	183	1			T20	2		T36	1		T24	3
ins	non_zero_bins[1]	fail	mubi_false	128	1			T20	3		T8	1		T36	2
ins	non_zero_bins[1]	fail	mubi_true	120	1			T20	1		T36	1		T24	1
ins	non_zero_bins[1]	pass	mubi_false	151	1			T20	5		T36	2		T9	1
ins	non_zero_bins[1]	pass	mubi_true	117	1			T20	4		T24	1		T142	2
ins	zero	fail	mubi_false	865	1			T2	1		T3	1		T18	2
ins	zero	fail	mubi_true	156	1			T1	1		T3	1		T14	1
ins	zero	pass	mubi_false	878	1			T4	1		T20	7		T36	3
ins	zero	pass	mubi_true	137	1			T24	1		T66	1		T75	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded