Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	73	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	3	3
67	1	1
69	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
			MISSING_ELSE
100	1	1
101	1	1
104	1	1
105	1	1
108	1	1
109	1	1
			MISSING_ELSE
113	1	1
114	1	1
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
			MISSING_ELSE
128	1	1
129	1	1
135	1	1
136	1	1
137	1	1
138	1	1
			MISSING_ELSE
142	1	1
143	1	1
144	1	1
145	1	1
			MISSING_ELSE
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
162	1	1
163	1	1
165	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
			MISSING_ELSE
184	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
200	1	1
208	1	1
209	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
232	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       69
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T17,T18
1	1	0	1	Covered	T3,T17,T18
1	1	1	0	Covered	T1,T2,T14
1	1	1	1	Covered	T2,T3,T17

 LINE       69
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       69
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       69
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       69
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T17,T18,T64
1	1	Covered	T3,T17,T18

 LINE       92
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T8,T31,T34
1	1	Covered	T8,T9,T5

 LINE       223
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	54	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	180	Covered	T8,T9,T5
AutoCaptGenCnt	165	Covered	T8,T9,T5
AutoCaptReseedCnt	163	Covered	T8,T9,T31
AutoDispatch	145	Covered	T8,T9,T5
AutoFirstAckWait	138	Covered	T8,T9,T5
AutoLoadIns	93	Covered	T8,T9,T5
AutoSendGenCmd	173	Covered	T8,T9,T5
AutoSendReseedCmd	187	Covered	T8,T9,T31
BootCaptGenCnt	109	Covered	T3,T17,T18
BootDone	129	Covered	T3,T17,T18
BootGenAckWait	119	Covered	T3,T17,T18
BootInsAckWait	105	Covered	T3,T17,T18
BootLoadGen	101	Covered	T3,T17,T18
BootLoadIns	91	Covered	T3,T17,T18
BootPulse	124	Covered	T3,T17,T18
BootSendGenCmd	114	Covered	T3,T17,T18
Error	209	Covered	T2,T3,T4
Idle	160	Covered	T1,T2,T3
SWPortMode	96	Covered	T1,T2,T14

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	152	Covered	T8,T9,T31
AutoAckWait->Error	209	Covered	T175,T176,T177
AutoAckWait->Idle	232	Covered	T8,T31,T34
AutoCaptGenCnt->AutoSendGenCmd	173	Covered	T8,T9,T5
AutoCaptGenCnt->Error	209	Covered	T178,T179
AutoCaptGenCnt->Idle	232	Covered	T81,T72,T180
AutoCaptReseedCnt->AutoSendReseedCmd	187	Covered	T8,T9,T31
AutoCaptReseedCnt->Error	209	Covered	T134,T49
AutoCaptReseedCnt->Idle	232	Covered	T29,T95,T181
AutoDispatch->AutoCaptGenCnt	165	Covered	T8,T9,T5
AutoDispatch->AutoCaptReseedCnt	163	Covered	T8,T9,T31
AutoDispatch->Error	209	Covered	T182,T183
AutoDispatch->Idle	160	Covered	T9,T122,T32
AutoFirstAckWait->AutoDispatch	145	Covered	T8,T9,T5
AutoFirstAckWait->Error	209	Covered	T184,T185
AutoFirstAckWait->Idle	232	Covered	T34,T186,T113
AutoLoadIns->AutoFirstAckWait	138	Covered	T8,T9,T5
AutoLoadIns->Error	209	Covered	T187,T188,T189
AutoLoadIns->Idle	232	Covered	T57,T110,T85
AutoSendGenCmd->AutoAckWait	180	Covered	T8,T9,T5
AutoSendGenCmd->Error	209	Covered	T26,T48,T190
AutoSendGenCmd->Idle	232	Covered	T191,T70,T118
AutoSendReseedCmd->AutoAckWait	194	Covered	T8,T9,T31
AutoSendReseedCmd->Error	209	Covered	T6,T7,T192
AutoSendReseedCmd->Idle	232	Covered	T8,T193,T194
BootCaptGenCnt->BootSendGenCmd	114	Covered	T3,T17,T18
BootCaptGenCnt->Error	209	Covered	T195,T196
BootCaptGenCnt->Idle	232	Covered	T96,T120,T197
BootDone->Error	209	Covered	T4,T50,T198
BootDone->Idle	232	Covered	T17,T46,T45
BootGenAckWait->BootPulse	124	Covered	T3,T17,T18
BootGenAckWait->Error	209	Covered	T199,T60,T200
BootGenAckWait->Idle	232	Covered	T18,T123,T40
BootInsAckWait->BootCaptGenCnt	109	Covered	T3,T17,T18
BootInsAckWait->Error	209	Covered	T201,T202,T203
BootInsAckWait->Idle	232	Covered	T102,T146,T91
BootLoadGen->BootInsAckWait	105	Covered	T3,T17,T18
BootLoadGen->Error	209	Covered	T204
BootLoadGen->Idle	232	Covered	T30,T87,T205
BootLoadIns->BootLoadGen	101	Covered	T3,T17,T18
BootLoadIns->Error	209	Covered	T206
BootLoadIns->Idle	232	Covered	T64,T42,T111
BootPulse->BootDone	129	Covered	T3,T17,T18
BootPulse->Error	209	Covered	T59,T207,T208
BootPulse->Idle	232	Covered	T153,T92,T131
BootSendGenCmd->BootGenAckWait	119	Covered	T3,T17,T18
BootSendGenCmd->Error	209	Covered	T209
BootSendGenCmd->Idle	232	Covered	T103,T115,T104
Idle->AutoLoadIns	93	Covered	T8,T9,T5
Idle->BootLoadIns	91	Covered	T3,T17,T18
Idle->Error	209	Covered	T21,T22,T23
Idle->SWPortMode	96	Covered	T1,T2,T14
SWPortMode->Error	209	Covered	T2,T13,T68
SWPortMode->Idle	232	Covered	T20,T36,T67

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	65	2	2	100.00
CASE	88	33	33	100.00
IF	208	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	65	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	case (state_q)
-2-:	90	if ((boot_req_mode_i && edn_enable_i))
-3-:	92	if ((auto_req_mode_i && edn_enable_i))
-4-:	94	if (edn_enable_i)
-5-:	108	if (csrng_cmd_ack_i)
-6-:	118	if (cmd_sent_i)
-7-:	123	if (csrng_cmd_ack_i)
-8-:	137	if (sw_cmd_req_load_i)
-9-:	143	if (csrng_cmd_ack_i)
-10-:	151	if (csrng_cmd_ack_i)
-11-:	158	if ((!auto_req_mode_i))
-12-:	162	if (max_reqs_cnt_zero_i)
-13-:	179	if (cmd_sent_i)
-14-:	193	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T5
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T96,T102,T146
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T18
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T5
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T9,T5
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T5
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T5
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T31
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T5
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T122,T32
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T31
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T5
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T5
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T5
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T5
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T31
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T31
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T31,T6
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T69

	LineNo.	Expression
-1-:	208	if (local_escalate_i)
-2-:	223	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	217892640	130696	0	0
FpvSecCmErrorStEscalate_A	217892640	131636	0	0
u_state_regs_A	217850171	217703529	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	130696	0	0
T2	1213	613	0	0
T3	2068	550	0	0
T4	2899	1139	0	0
T5	0	233	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	832	0	0
T150	0	370	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	131636	0	0
T2	1213	614	0	0
T3	2068	551	0	0
T4	2899	1140	0	0
T5	0	234	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	833	0	0
T150	0	371	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217850171	217703529	0	0
T1	1555	1500	0	0
T2	1074	940	0	0
T3	957	773	0	0
T4	1739	1599	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0