Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.25	100.00	85.74			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T1,T2,T18
DataWait	78	Covered	T1,T2,T18
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Covered	T92,T131,T244
AckPls->Error	102	Covered	T5,T150,T176
AckPls->Idle	88	Covered	T1,T2,T18
DataWait->AckPls	83	Covered	T1,T2,T18
DataWait->Disabled	110	Covered	T18,T8,T31
DataWait->Error	102	Covered	T4,T26,T48
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T1,T2,T18
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T18
Idle	-	1	0	-	Covered	T1,T2,T18
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T18
DataWait	-	-	-	0	Covered	T1,T18,T4
AckPls	-	-	-	-	Covered	T1,T2,T18
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T68,T6,T26

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1525248480	929022	0	0
FpvSecCmErrorStEscalate_A	1525248480	935602	0	0
u_state_regs_A	1525206011	1524179517	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1525248480	929022	0	0
T2	8491	4291	0	0
T3	14476	4200	0	0
T4	20293	7973	0	0
T5	0	1981	0	0
T6	0	4444	0	0
T7	0	4214	0	0
T13	0	2016	0	0
T14	11277	0	0	0
T16	8708	0	0	0
T17	7273	0	0	0
T18	9940	0	0	0
T19	9184	0	0	0
T20	996968	0	0	0
T52	9954	0	0	0
T68	0	3023	0	0
T69	0	6174	0	0
T150	0	2940	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1525248480	935602	0	0
T2	8491	4298	0	0
T3	14476	4207	0	0
T4	20293	7980	0	0
T5	0	1988	0	0
T6	0	4451	0	0
T7	0	4221	0	0
T13	0	2023	0	0
T14	11277	0	0	0
T16	8708	0	0	0
T17	7273	0	0	0
T18	9940	0	0	0
T19	9184	0	0	0
T20	996968	0	0	0
T52	9954	0	0	0
T68	0	3030	0	0
T69	0	6181	0	0
T150	0	2947	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1525206011	1524179517	0	0
T1	10885	10500	0	0
T2	8352	7414	0	0
T3	13365	12077	0	0
T4	19133	18153	0	0
T14	11277	10773	0	0
T16	8708	8008	0	0
T17	7273	6643	0	0
T18	9940	9282	0	0
T19	9184	8659	0	0
T20	996968	996884	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T14,T17,T30
DataWait	78	Covered	T14,T17,T30
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Not Covered
AckPls->Error	102	Not Covered
AckPls->Idle	88	Covered	T14,T17,T30
DataWait->AckPls	83	Covered	T14,T17,T30
DataWait->Disabled	110	Covered	T96
DataWait->Error	102	Covered	T50,T198,T246
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T14,T17,T30
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T14,T17,T30
Idle	-	1	0	-	Covered	T14,T17,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T14,T17,T30
DataWait	-	-	-	0	Covered	T14,T17,T30
AckPls	-	-	-	-	Covered	T14,T17,T30
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T31,T32,T38
DataWait	78	Covered	T3,T31,T32
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Not Covered
AckPls->Error	102	Not Covered
AckPls->Idle	88	Covered	T31,T32,T38
DataWait->AckPls	83	Covered	T31,T32,T38
DataWait->Disabled	110	Covered	T103,T104,T247
DataWait->Error	102	Covered	T3,T248,T249
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T3,T31,T32
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T4,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T31,T32,T38
Idle	-	1	0	-	Covered	T3,T31,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T31,T32,T38
DataWait	-	-	-	0	Covered	T3,T31,T32
AckPls	-	-	-	-	Covered	T31,T32,T38
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T15,T27,T37
DataWait	78	Covered	T15,T26,T27
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Not Covered
AckPls->Error	102	Covered	T176
AckPls->Idle	88	Covered	T15,T27,T37
DataWait->AckPls	83	Covered	T15,T27,T37
DataWait->Disabled	110	Covered	T40,T197,T250
DataWait->Error	102	Covered	T26,T195,T209
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T15,T26,T27
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T15,T27,T37
Idle	-	1	0	-	Covered	T15,T26,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T15,T27,T37
DataWait	-	-	-	0	Covered	T15,T26,T37
AckPls	-	-	-	-	Covered	T15,T27,T37
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T2,T29,T43
DataWait	78	Covered	T2,T29,T43
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Covered	T92
AckPls->Error	102	Not Covered
AckPls->Idle	88	Covered	T2,T29,T43
DataWait->AckPls	83	Covered	T2,T29,T43
DataWait->Disabled	110	Covered	T251,T252
DataWait->Error	102	Covered	T253,T254,T255
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T2,T29,T43
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T29,T43
Idle	-	1	0	-	Covered	T2,T29,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T29,T43
DataWait	-	-	-	0	Covered	T32,T42,T253
AckPls	-	-	-	-	Covered	T2,T29,T43
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T8,T5,T33
DataWait	78	Covered	T8,T5,T33
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Not Covered
AckPls->Error	102	Covered	T5
AckPls->Idle	88	Covered	T8,T33,T87
DataWait->AckPls	83	Covered	T8,T5,T33
DataWait->Disabled	110	Covered	T115
DataWait->Error	102	Covered	T199,T256,T257
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T8,T5,T33
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T33,T87
Idle	-	1	0	-	Covered	T8,T5,T33
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T5,T33
DataWait	-	-	-	0	Covered	T8,T5,T87
AckPls	-	-	-	-	Covered	T8,T5,T33
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T31,T34,T35
DataWait	78	Covered	T31,T34,T35
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Covered	T131
AckPls->Error	102	Not Covered
AckPls->Idle	88	Covered	T31,T34,T35
DataWait->AckPls	83	Covered	T31,T34,T35
DataWait->Disabled	110	Covered	T31,T120,T258
DataWait->Error	102	Covered	T259,T260,T261
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T31,T34,T35
Idle->Disabled	110	Covered	T17,T18,T20
Idle->Error	102	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T31,T34,T35
Idle	-	1	0	-	Covered	T31,T34,T35
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T31,T34,T35
DataWait	-	-	-	0	Covered	T31,T34,T29
AckPls	-	-	-	-	Covered	T31,T34,T35
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	132996	0	0
FpvSecCmErrorStEscalate_A	217892640	133936	0	0
u_state_regs_A	217892640	217745998	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	132996	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	642	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	439	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	133936	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	643	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	440	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	217745998	0	0
T1	1555	1500	0	0
T2	1213	1079	0	0
T3	2068	1884	0	0
T4	2899	2759	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	55	3	3	100.00
ALWAYS	58	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	3	3
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
65	1	1
66	1	1
67	1	1
			MISSING_ELSE
71	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
78	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
87	1	1
88	1	1
91	1	1
101	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
110	1	1
112	1	1
113	1	1
114	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	83	Covered	T1,T18,T20
DataWait	78	Covered	T1,T18,T4
Disabled	110	Covered	T1,T2,T3
EndPointClear	66	Covered	T1,T2,T3
Error	102	Covered	T2,T3,T4
Idle	71	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	110	Covered	T244
AckPls->Error	102	Covered	T150,T262
AckPls->Idle	88	Covered	T1,T18,T20
DataWait->AckPls	83	Covered	T1,T18,T20
DataWait->Disabled	110	Covered	T18,T8,T123
DataWait->Error	102	Covered	T4,T48,T263
Disabled->EndPointClear	66	Covered	T1,T2,T3
Disabled->Error	102	Covered	T21,T22,T23
EndPointClear->Disabled	110	Covered	T64,T142,T42
EndPointClear->Error	102	Covered	T28,T21,T245
EndPointClear->Idle	71	Covered	T1,T2,T3
Idle->DataWait	78	Covered	T1,T18,T4
Idle->Disabled	110	Covered	T17,T20,T8
Idle->Error	102	Covered	T2,T3,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	55	2	2	100.00
CASE	63	11	11	100.00
IF	101	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	63	case (state_q)
-2-:	65	if (enable_i)
-3-:	74	if (req_i)
-4-:	75	if (fifo_not_empty_i)
-5-:	82	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T18,T20
Idle	-	1	0	-	Covered	T1,T18,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T18,T20
DataWait	-	-	-	0	Covered	T1,T18,T4
AckPls	-	-	-	-	Covered	T1,T18,T20
Error	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Covered	T68,T6,T26

	LineNo.	Expression
-1-:	101	if (local_escalate_i)
-2-:	107	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T17,T18,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	217892640	131046	0	0
FpvSecCmErrorStEscalate_A	217892640	131986	0	0
u_state_regs_A	217850171	217703529	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	131046	0	0
T2	1213	613	0	0
T3	2068	600	0	0
T4	2899	1139	0	0
T5	0	283	0	0
T6	0	592	0	0
T7	0	602	0	0
T13	0	288	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	389	0	0
T69	0	882	0	0
T150	0	420	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217892640	131986	0	0
T2	1213	614	0	0
T3	2068	601	0	0
T4	2899	1140	0	0
T5	0	284	0	0
T6	0	593	0	0
T7	0	603	0	0
T13	0	289	0	0
T14	1611	0	0	0
T16	1244	0	0	0
T17	1039	0	0	0
T18	1420	0	0	0
T19	1312	0	0	0
T20	142424	0	0	0
T52	1422	0	0	0
T68	0	390	0	0
T69	0	883	0	0
T150	0	421	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217850171	217703529	0	0
T1	1555	1500	0	0
T2	1074	940	0	0
T3	957	773	0	0
T4	1739	1599	0	0
T14	1611	1539	0	0
T16	1244	1144	0	0
T17	1039	949	0	0
T18	1420	1326	0	0
T19	1312	1237	0	0
T20	142424	142412	0	0