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Module Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_ins_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_gen_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_rdy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sw_cmd_sts_cmd_sts


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_max_num_reqs_between_reseeds


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_edn_enable_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_boot_req_mode_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_auto_req_mode_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_cmd_fifo_rst_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_edn_bus_cmp_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_sfifo_rescmd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_sfifo_gencmd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_sfifo_output_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_err_code_sfifo_output_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_edn_ack_sm_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_regwen.wr_en_data_arb
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_sfifo_output_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T14
10CoveredT1,T2,T3 

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T14
11CoveredT1,T2,T14 

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T14 

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
80 1 1
102 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       80
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T14 

 LINE       102
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4 

 LINE       102
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4 

 LINE       102
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT76,T148,T149 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT76,T148,T149
10CoveredT76,T148,T149
11CoveredT1,T2,T3 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT76,T148,T149
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T17,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T17,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T17,T18
Branch Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T3,T17,T18
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T17,T18 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T17,T18 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T17,T18
Branch Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T3,T17,T18
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN39100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 0 1
40 1 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 1 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
37 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT8,T9,T5 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T5 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T5
Branch Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T5
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T66,T264
10CoveredT1,T14,T15 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T66,T264
11CoveredT1,T66,T264 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T66,T264 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT75,T94,T265
10CoveredT1,T14,T15 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT75,T94,T265
11CoveredT75,T94,T265 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT75,T94,T265 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT144,T266,T109
10CoveredT1,T14,T15 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT144,T266,T109
11CoveredT144,T266,T109 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT144,T266,T109 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T267
10CoveredT1,T14,T15 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T267
11CoveredT14,T15,T267 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T15,T267 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
127 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       105
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T14,T15
10CoveredT1,T14,T15 

 LINE       127
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T14,T15
11CoveredT1,T14,T15 

 LINE       127
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15 

 LINE       127
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T14,T15
Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_output_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3911100.00
CONT_ASSIGN40100.00
CONT_ASSIGN4500
CONT_ASSIGN4600
CONT_ASSIGN4711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 1 1
40 0 1
45 unreachable
46 unreachable
47 1 1

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