Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4558263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

581271

1

T1

127

T2

222

T3

367

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4750180	1			T1	1472		T2	5725		T3	679
values[0x0]	192263	1			T1	70		T2	67		T3	130
values[0x1]	197091	1			T1	66		T2	57		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3094483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2045051

1

T1

627

T2

2079

T3

537

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27143	1			T1	5		T2	4		T4	19
valid_sources[0x01]	19525	1			T1	1		T2	12		T4	13
valid_sources[0x02]	16566	1			T1	7		T2	7		T4	11
valid_sources[0x03]	18065	1			T1	9		T4	9		T17	8
valid_sources[0x04]	50908	1			T1	8		T2	23		T4	5
valid_sources[0x05]	15485	1			T1	6		T2	32		T4	8
valid_sources[0x06]	16613	1			T1	5		T2	21		T4	15
valid_sources[0x07]	16191	1			T1	7		T2	5		T4	14
valid_sources[0x08]	16102	1			T1	1		T2	39		T4	9
valid_sources[0x09]	16932	1			T1	11		T2	21		T4	12
valid_sources[0x0a]	22489	1			T1	3		T2	12		T4	18
valid_sources[0x0b]	18861	1			T1	15		T2	38		T4	9
valid_sources[0x0c]	16391	1			T1	9		T2	2		T4	9
valid_sources[0x0d]	27324	1			T1	5		T4	15		T5	4
valid_sources[0x0e]	25455	1			T1	12		T2	17		T4	12
valid_sources[0x0f]	18291	1			T1	4		T2	52		T4	12
valid_sources[0x10]	34517	1			T1	9		T2	23		T4	9
valid_sources[0x11]	20785	1			T1	5		T2	26		T4	9
valid_sources[0x12]	15669	1			T1	2		T2	9		T4	11
valid_sources[0x13]	16548	1			T1	10		T2	15		T4	12
valid_sources[0x14]	16284	1			T1	9		T2	9		T4	7
valid_sources[0x15]	17010	1			T1	4		T4	13		T5	5
valid_sources[0x16]	22125	1			T1	14		T4	10		T5	1
valid_sources[0x17]	26717	1			T1	14		T2	4		T4	21
valid_sources[0x18]	16480	1			T1	5		T2	26		T4	16
valid_sources[0x19]	16644	1			T1	8		T2	31		T4	21
valid_sources[0x1a]	19944	1			T1	4		T2	13		T4	16
valid_sources[0x1b]	16482	1			T1	1		T2	17		T4	8
valid_sources[0x1c]	16204	1			T1	9		T2	3		T4	13
valid_sources[0x1d]	18504	1			T1	3		T2	10		T4	14
valid_sources[0x1e]	16238	1			T1	3		T2	6		T4	23
valid_sources[0x1f]	16495	1			T1	10		T2	10		T4	7
valid_sources[0x20]	20767	1			T1	4		T2	13		T4	8
valid_sources[0x21]	25097	1			T1	6		T2	38		T4	20
valid_sources[0x22]	17019	1			T1	7		T2	18		T4	18
valid_sources[0x23]	38469	1			T1	3		T2	5		T4	9
valid_sources[0x24]	16865	1			T1	8		T2	16		T4	3
valid_sources[0x25]	21184	1			T1	7		T2	22		T4	14
valid_sources[0x26]	17180	1			T1	9		T2	17		T4	9
valid_sources[0x27]	17253	1			T1	2		T2	41		T4	18
valid_sources[0x28]	16467	1			T1	11		T4	9		T5	3
valid_sources[0x29]	16155	1			T1	7		T2	11		T4	11
valid_sources[0x2a]	165278	1			T1	5		T2	40		T4	10
valid_sources[0x2b]	20417	1			T1	3		T2	41		T4	13
valid_sources[0x2c]	16250	1			T1	8		T2	18		T4	16
valid_sources[0x2d]	15672	1			T1	5		T2	34		T4	13
valid_sources[0x2e]	16412	1			T1	7		T2	40		T4	10
valid_sources[0x2f]	15954	1			T1	8		T2	22		T4	12
valid_sources[0x30]	32972	1			T1	2		T2	2		T4	12
valid_sources[0x31]	16873	1			T1	6		T2	41		T4	7
valid_sources[0x32]	48007	1			T1	8		T2	42		T4	16
valid_sources[0x33]	17370	1			T1	5		T2	18		T4	14
valid_sources[0x34]	21922	1			T1	8		T2	38		T4	19
valid_sources[0x35]	15660	1			T1	8		T2	52		T4	12
valid_sources[0x36]	17322	1			T1	1		T2	9		T4	9
valid_sources[0x37]	16893	1			T1	1		T2	20		T4	12
valid_sources[0x38]	22181	1			T1	9		T2	21		T4	14
valid_sources[0x39]	18944	1			T1	5		T2	20		T4	19
valid_sources[0x3a]	22033	1			T1	2		T4	17		T5	1
valid_sources[0x3b]	16191	1			T1	2		T2	23		T4	11
valid_sources[0x3c]	16606	1			T1	5		T2	10		T4	5
valid_sources[0x3d]	19768	1			T1	3		T2	24		T4	19
valid_sources[0x3e]	17293	1			T1	4		T2	18		T4	15
valid_sources[0x3f]	16646	1			T1	16		T2	51		T4	2
valid_sources[0x40]	17159	1			T1	6		T2	25		T4	18
valid_sources[0x41]	16241	1			T1	6		T2	31		T4	12
valid_sources[0x42]	34094	1			T1	8		T2	37		T4	9
valid_sources[0x43]	19068	1			T1	7		T2	18		T4	13
valid_sources[0x44]	27916	1			T1	16		T2	25		T4	10
valid_sources[0x45]	23436	1			T1	4		T2	32		T4	25
valid_sources[0x46]	17859	1			T1	4		T2	6		T4	18
valid_sources[0x47]	16592	1			T1	4		T2	5		T4	11
valid_sources[0x48]	16283	1			T1	10		T2	43		T4	20
valid_sources[0x49]	18280	1			T1	5		T2	54		T4	15
valid_sources[0x4a]	17789	1			T1	7		T2	28		T4	9
valid_sources[0x4b]	17226	1			T1	3		T4	10		T5	14
valid_sources[0x4c]	17481	1			T1	9		T2	7		T4	6
valid_sources[0x4d]	19739	1			T1	6		T2	16		T4	15
valid_sources[0x4e]	25597	1			T1	7		T4	14		T13	8
valid_sources[0x4f]	15751	1			T1	3		T2	12		T4	12
valid_sources[0x50]	31501	1			T1	8		T2	91		T4	14
valid_sources[0x51]	16239	1			T1	9		T2	20		T4	12
valid_sources[0x52]	16524	1			T1	2		T2	55		T4	9
valid_sources[0x53]	15351	1			T1	3		T2	3		T4	9
valid_sources[0x54]	15884	1			T1	5		T2	29		T4	8
valid_sources[0x55]	20558	1			T1	5		T2	42		T4	19
valid_sources[0x56]	16771	1			T1	9		T2	9		T4	23
valid_sources[0x57]	15936	1			T1	11		T2	34		T4	19
valid_sources[0x58]	28539	1			T1	6		T2	28		T4	30
valid_sources[0x59]	15853	1			T1	9		T2	8		T4	5
valid_sources[0x5a]	18875	1			T1	5		T2	34		T4	12
valid_sources[0x5b]	16668	1			T1	2		T2	5		T4	21
valid_sources[0x5c]	16514	1			T1	2		T2	9		T4	15
valid_sources[0x5d]	16850	1			T1	9		T2	68		T4	11
valid_sources[0x5e]	17452	1			T1	9		T2	31		T4	19
valid_sources[0x5f]	16714	1			T1	6		T2	2		T4	13
valid_sources[0x60]	31304	1			T1	3		T2	81		T4	13
valid_sources[0x61]	19902	1			T1	6		T2	2		T4	16
valid_sources[0x62]	16790	1			T1	7		T2	41		T4	9
valid_sources[0x63]	17056	1			T1	7		T2	64		T4	18
valid_sources[0x64]	17144	1			T1	8		T2	19		T4	11
valid_sources[0x65]	16428	1			T1	10		T2	43		T4	12
valid_sources[0x66]	16134	1			T1	10		T2	13		T4	17
valid_sources[0x67]	15840	1			T1	4		T2	30		T4	16
valid_sources[0x68]	21130	1			T1	5		T2	9		T4	15
valid_sources[0x69]	16371	1			T1	5		T2	26		T4	12
valid_sources[0x6a]	52179	1			T1	3		T2	44		T4	14
valid_sources[0x6b]	16757	1			T1	3		T2	33		T4	11
valid_sources[0x6c]	19304	1			T1	6		T2	3		T4	12
valid_sources[0x6d]	20737	1			T1	14		T2	25		T4	17
valid_sources[0x6e]	16649	1			T1	8		T2	34		T4	16
valid_sources[0x6f]	29838	1			T1	1		T2	81		T4	9
valid_sources[0x70]	16198	1			T1	20		T2	15		T4	17
valid_sources[0x71]	15986	1			T1	2		T2	24		T4	6
valid_sources[0x72]	18481	1			T1	10		T2	62		T3	961
valid_sources[0x73]	18806	1			T1	3		T2	30		T4	13
valid_sources[0x74]	17198	1			T1	3		T2	22		T4	12
valid_sources[0x75]	15645	1			T1	10		T2	56		T4	13
valid_sources[0x76]	24843	1			T1	5		T2	17		T4	7
valid_sources[0x77]	17753	1			T4	10		T5	7		T17	2
valid_sources[0x78]	16552	1			T1	6		T2	81		T4	7
valid_sources[0x79]	17004	1			T1	5		T2	6		T4	15
valid_sources[0x7a]	18714	1			T1	6		T2	19		T4	14
valid_sources[0x7b]	19978	1			T1	6		T2	80		T4	14
valid_sources[0x7c]	27053	1			T1	7		T2	5		T4	18
valid_sources[0x7d]	16893	1			T2	19		T4	12		T5	8
valid_sources[0x7e]	19435	1			T1	13		T2	4		T4	16
valid_sources[0x7f]	17021	1			T1	6		T2	42		T4	19
valid_sources[0x80]	18707	1			T1	5		T2	5		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

315805

1

T1

18

T2

177

T3

163

values[0x0]

all_enables

biggest_size

139124

1

T1

56

T2

27

T3

99

values[0x1]

all_enables

biggest_size

126342

1

T1

53

T2

18

T3

105