Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	31866308	19570	0	0
attest_sw_binding_0_rd_A	31866308	606	0	0
attest_sw_binding_1_rd_A	31866308	707	0	0
attest_sw_binding_2_rd_A	31866308	688	0	0
attest_sw_binding_3_rd_A	31866308	704	0	0
attest_sw_binding_4_rd_A	31866308	683	0	0
attest_sw_binding_5_rd_A	31866308	763	0	0
attest_sw_binding_6_rd_A	31866308	669	0	0
attest_sw_binding_7_rd_A	31866308	646	0	0
intr_enable_rd_A	31866308	1226	0	0
key_version_rd_A	31866308	638	0	0
max_creator_key_ver_regwen_rd_A	31866308	746	0	0
max_owner_int_key_ver_regwen_rd_A	31866308	749	0	0
max_owner_key_ver_regwen_rd_A	31866308	720	0	0
reseed_interval_regwen_rd_A	31866308	788	0	0
salt_0_rd_A	31866308	759	0	0
salt_1_rd_A	31866308	729	0	0
salt_2_rd_A	31866308	706	0	0
salt_3_rd_A	31866308	713	0	0
salt_4_rd_A	31866308	712	0	0
salt_5_rd_A	31866308	712	0	0
salt_6_rd_A	31866308	720	0	0
salt_7_rd_A	31866308	592	0	0
sealing_sw_binding_0_rd_A	31866308	712	0	0
sealing_sw_binding_1_rd_A	31866308	663	0	0
sealing_sw_binding_2_rd_A	31866308	709	0	0
sealing_sw_binding_3_rd_A	31866308	769	0	0
sealing_sw_binding_4_rd_A	31866308	735	0	0
sealing_sw_binding_5_rd_A	31866308	701	0	0
sealing_sw_binding_6_rd_A	31866308	731	0	0
sealing_sw_binding_7_rd_A	31866308	696	0	0
sideload_clear_rd_A	31866308	680	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	19570	0	0
T16	4124	1	0	0
T17	18299	0	0	0
T26	156598	0	0	0
T30	8389	0	0	0
T31	3170	0	0	0
T35	26428	0	0	0
T49	0	525	0	0
T51	2288	0	0	0
T70	119537	0	0	0
T74	38346	0	0	0
T75	10697	0	0	0
T101	0	738	0	0
T111	0	131	0	0
T112	0	538	0	0
T113	0	410	0	0
T114	0	156	0	0
T115	0	288	0	0
T116	0	74	0	0
T130	0	2	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	606	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	23	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	6	0	0
T166	1390	9	0	0
T167	0	2	0	0
T168	0	13	0	0
T169	0	10	0	0
T170	0	16	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	8	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	707	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	23	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	7	0	0
T166	1390	4	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	17	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	7	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	688	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	24	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	1	0	0
T166	1390	4	0	0
T167	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	23	0	0
T171	0	9	0	0
T172	0	13	0	0
T173	0	3	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	704	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	25	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	8	0	0
T167	0	8	0	0
T168	0	16	0	0
T170	0	6	0	0
T171	0	6	0	0
T172	0	18	0	0
T173	0	5	0	0
T174	0	4	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	683	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	32	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	6	0	0
T166	1390	3	0	0
T168	0	6	0	0
T169	0	2	0	0
T170	0	9	0	0
T171	0	5	0	0
T172	0	12	0	0
T175	0	10	0	0
T176	0	7	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	763	0	0
T87	7683	0	0	0
T110	20567	0	0	0
T114	20382	37	0	0
T165	1353	1	0	0
T167	2021	1	0	0
T168	5994	5	0	0
T169	0	6	0	0
T170	0	20	0	0
T171	0	1	0	0
T175	0	2	0	0
T176	0	4	0	0
T177	0	27	0	0
T178	1159	0	0	0
T179	25270	0	0	0
T180	1465	0	0	0
T181	1692	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	669	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	6	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	9	0	0
T166	1390	2	0	0
T167	0	3	0	0
T170	0	6	0	0
T171	0	3	0	0
T172	0	7	0	0
T173	0	6	0	0
T175	0	6	0	0
T177	0	21	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	646	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	16	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	4	0	0
T166	1390	2	0	0
T167	0	6	0	0
T168	0	8	0	0
T169	0	2	0	0
T170	0	11	0	0
T172	0	2	0	0
T173	0	1	0	0
T175	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	1226	0	0
T36	11268	0	0	0
T44	513888	10	0	0
T49	12708	0	0	0
T57	21557	0	0	0
T73	109705	0	0	0
T114	0	16	0	0
T119	77948	0	0	0
T120	243312	0	0	0
T121	87797	0	0	0
T122	6824	0	0	0
T132	0	11	0	0
T133	0	16	0	0
T165	0	8	0	0
T166	0	1	0	0
T167	0	2	0	0
T182	0	26	0	0
T183	0	7	0	0
T184	0	19	0	0
T185	5270	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	638	0	0
T87	7683	0	0	0
T110	20567	0	0	0
T114	20382	15	0	0
T135	2717	0	0	0
T165	1353	7	0	0
T168	5994	4	0	0
T169	0	12	0	0
T170	0	28	0	0
T171	0	6	0	0
T172	0	8	0	0
T173	0	7	0	0
T175	0	3	0	0
T176	0	7	0	0
T179	25270	0	0	0
T180	1465	0	0	0
T181	1692	0	0	0
T186	919	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	746	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	19	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	6	0	0
T166	1390	1	0	0
T167	0	3	0	0
T168	0	30	0	0
T169	0	1	0	0
T170	0	16	0	0
T171	0	1	0	0
T172	0	11	0	0
T173	0	2	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	749	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	32	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	5	0	0
T168	0	4	0	0
T169	0	6	0	0
T170	0	16	0	0
T171	0	5	0	0
T172	0	4	0	0
T173	0	4	0	0
T175	0	16	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	720	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	2	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	6	0	0
T166	1390	5	0	0
T167	0	3	0	0
T169	0	4	0	0
T170	0	34	0	0
T171	0	5	0	0
T172	0	3	0	0
T174	0	4	0	0
T175	0	33	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	788	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	32	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	8	0	0
T166	1390	3	0	0
T167	0	6	0	0
T168	0	4	0	0
T169	0	2	0	0
T170	0	24	0	0
T171	0	6	0	0
T172	0	7	0	0
T174	0	2	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	759	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	36	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	5	0	0
T166	1390	6	0	0
T167	0	9	0	0
T168	0	8	0	0
T169	0	9	0	0
T170	0	26	0	0
T171	0	6	0	0
T172	0	10	0	0
T173	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	729	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	33	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	6	0	0
T166	1390	6	0	0
T167	0	4	0	0
T168	0	19	0	0
T169	0	4	0	0
T170	0	33	0	0
T171	0	4	0	0
T172	0	10	0	0
T173	0	2	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	706	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	5	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	2	0	0
T168	0	23	0	0
T170	0	21	0	0
T171	0	2	0	0
T172	0	6	0	0
T173	0	7	0	0
T174	0	3	0	0
T175	0	6	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	713	0	0
T87	7683	0	0	0
T110	20567	0	0	0
T114	20382	7	0	0
T165	1353	5	0	0
T167	2021	2	0	0
T168	5994	4	0	0
T170	0	28	0	0
T171	0	7	0	0
T172	0	12	0	0
T173	0	6	0	0
T175	0	14	0	0
T177	0	25	0	0
T178	1159	0	0	0
T179	25270	0	0	0
T180	1465	0	0	0
T181	1692	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	712	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	35	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	4	0	0
T166	1390	5	0	0
T167	0	2	0	0
T168	0	7	0	0
T169	0	6	0	0
T170	0	13	0	0
T171	0	10	0	0
T172	0	14	0	0
T173	0	9	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	712	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	18	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	4	0	0
T167	0	9	0	0
T168	0	17	0	0
T169	0	2	0	0
T170	0	34	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	5	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	720	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	9	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	7	0	0
T166	1390	5	0	0
T167	0	7	0	0
T169	0	3	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	5	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	592	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	31	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	1	0	0
T168	0	9	0	0
T170	0	16	0	0
T171	0	8	0	0
T172	0	5	0	0
T177	0	21	0	0
T187	0	26	0	0
T188	0	100	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	712	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	23	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	1	0	0
T166	1390	8	0	0
T167	0	10	0	0
T168	0	2	0	0
T169	0	6	0	0
T170	0	37	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	5	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	663	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	19	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	3	0	0
T167	0	9	0	0
T168	0	8	0	0
T169	0	8	0	0
T170	0	5	0	0
T171	0	6	0	0
T172	0	6	0	0
T173	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	709	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	28	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	1	0	0
T166	1390	5	0	0
T167	0	4	0	0
T168	0	5	0	0
T169	0	4	0	0
T170	0	19	0	0
T171	0	3	0	0
T172	0	11	0	0
T173	0	3	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	769	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	32	0	0
T117	2829	0	0	0
T118	11112	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T166	1390	4	0	0
T167	0	6	0	0
T168	0	16	0	0
T169	0	1	0	0
T170	0	17	0	0
T171	0	8	0	0
T173	0	7	0	0
T174	0	1	0	0
T176	0	7	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	735	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	8	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	5	0	0
T166	1390	5	0	0
T167	0	2	0	0
T169	0	1	0	0
T170	0	29	0	0
T172	0	10	0	0
T173	0	5	0	0
T174	0	1	0	0
T175	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	701	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	21	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	4	0	0
T166	1390	5	0	0
T167	0	8	0	0
T168	0	1	0	0
T169	0	4	0	0
T170	0	12	0	0
T171	0	5	0	0
T172	0	8	0	0
T173	0	5	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	731	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	22	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	2	0	0
T166	1390	3	0	0
T168	0	5	0	0
T169	0	1	0	0
T170	0	12	0	0
T171	0	6	0	0
T172	0	5	0	0
T176	0	8	0	0
T177	0	32	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	696	0	0
T87	7683	0	0	0
T102	9938	0	0	0
T107	8589	0	0	0
T114	20382	30	0	0
T117	2829	0	0	0
T130	2791	0	0	0
T131	765	0	0	0
T132	1204	0	0	0
T165	1353	1	0	0
T166	1390	2	0	0
T167	0	8	0	0
T168	0	6	0	0
T169	0	2	0	0
T170	0	25	0	0
T171	0	6	0	0
T172	0	4	0	0
T173	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31866308	680	0	0
T87	7683	0	0	0
T110	20567	0	0	0
T114	20382	26	0	0
T135	2717	0	0	0
T167	2021	3	0	0
T168	5994	8	0	0
T170	0	21	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	5	0	0
T175	0	4	0	0
T176	0	6	0	0
T178	1159	0	0	0
T179	25270	0	0	0
T180	1465	0	0	0
T181	1692	0	0	0