KEYMGR Simulation Results

Monday January 22 2024 20:02:58 UTC

GitHub Revision: 509f2f46b9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3521792850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 43.620s 4.458ms 50 50 100.00
V1 random keymgr_random 1.227m 10.410ms 48 50 96.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.470s 60.936us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.550s 25.277us 16 20 80.00
V1 csr_bit_bash keymgr_csr_bit_bash 12.830s 268.488us 3 5 60.00
V1 csr_aliasing keymgr_csr_aliasing 13.650s 767.979us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.740s 40.628us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.550s 25.277us 16 20 80.00
keymgr_csr_aliasing 13.650s 767.979us 5 5 100.00
V1 TOTAL 146 155 94.19
V2 cfgen_during_op keymgr_cfg_regwen 2.305m 40.552ms 49 50 98.00
V2 sideload keymgr_sideload 56.640s 4.058ms 48 50 96.00
keymgr_sideload_kmac 1.340m 7.815ms 47 50 94.00
keymgr_sideload_aes 1.151m 4.510ms 50 50 100.00
keymgr_sideload_otbn 1.282m 2.289ms 47 50 94.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.076m 11.680ms 47 50 94.00
V2 lc_disable keymgr_lc_disable 20.780s 689.782us 48 50 96.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.151m 3.143ms 44 50 88.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.578m 4.979ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 55.600s 6.701ms 49 50 98.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 18.350s 11.260ms 48 50 96.00
V2 stress_all keymgr_stress_all 9.589m 35.526ms 48 50 96.00
V2 intr_test keymgr_intr_test 1.160s 30.280us 50 50 100.00
V2 alert_test keymgr_alert_test 1.130s 308.246us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.960s 173.963us 19 20 95.00
V2 tl_d_illegal_access keymgr_tl_errors 4.960s 173.963us 19 20 95.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.470s 60.936us 5 5 100.00
keymgr_csr_rw 1.550s 25.277us 16 20 80.00
keymgr_csr_aliasing 13.650s 767.979us 5 5 100.00
keymgr_same_csr_outstanding 2.680s 112.553us 13 20 65.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.470s 60.936us 5 5 100.00
keymgr_csr_rw 1.550s 25.277us 16 20 80.00
keymgr_csr_aliasing 13.650s 767.979us 5 5 100.00
keymgr_same_csr_outstanding 2.680s 112.553us 13 20 65.00
V2 TOTAL 707 740 95.54
V2S sec_cm_additional_check keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
keymgr_tl_intg_err 18.000s 1.820ms 15 20 75.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 29.560s 1.729ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 29.560s 1.729ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 29.560s 1.729ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 29.560s 1.729ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 21.210s 724.795us 16 20 80.00
V2S prim_count_check keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 18.000s 1.820ms 15 20 75.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 29.560s 1.729ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.305m 40.552ms 49 50 98.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.227m 10.410ms 48 50 96.00
keymgr_csr_rw 1.550s 25.277us 16 20 80.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.227m 10.410ms 48 50 96.00
keymgr_csr_rw 1.550s 25.277us 16 20 80.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.227m 10.410ms 48 50 96.00
keymgr_csr_rw 1.550s 25.277us 16 20 80.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 20.780s 689.782us 48 50 96.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 55.600s 6.701ms 49 50 98.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 55.600s 6.701ms 49 50 98.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.227m 10.410ms 48 50 96.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 30.960s 1.591ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 38.680s 1.544ms 49 50 98.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 20.780s 689.782us 48 50 96.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 38.680s 1.544ms 49 50 98.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 38.680s 1.544ms 49 50 98.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 38.680s 1.544ms 49 50 98.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 2.014m 5.576ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 38.680s 1.544ms 49 50 98.00
V2S TOTAL 155 165 93.94
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 17.740s 1.725ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1056 1110 95.14

Testplan Progress

Items Total Written Passing Progress
V1 7 7 3 42.86
V2 16 16 4 25.00
V2S 6 6 3 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.83 99.10 98.07 98.58 100.00 99.11 98.41 91.58

Failure Buckets

Past Results