KEYMGR Simulation Results

Saturday June 08 2024 19:02:20 UTC

GitHub Revision: 8dab2b7626

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4247883128

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 40.530s 3.779ms 50 50 100.00
V1 random keymgr_random 1.950m 49.641ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.580s 450.366us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.700s 333.275us 16 20 80.00
V1 csr_bit_bash keymgr_csr_bit_bash 17.700s 868.771us 4 5 80.00
V1 csr_aliasing keymgr_csr_aliasing 9.000s 684.978us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.200s 509.050us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.700s 333.275us 16 20 80.00
keymgr_csr_aliasing 9.000s 684.978us 5 5 100.00
V1 TOTAL 150 155 96.77
V2 cfgen_during_op keymgr_cfg_regwen 2.179m 7.527ms 50 50 100.00
V2 sideload keymgr_sideload 1.535m 8.513ms 50 50 100.00
keymgr_sideload_kmac 1.320m 7.638ms 50 50 100.00
keymgr_sideload_aes 1.080m 3.425ms 50 50 100.00
keymgr_sideload_otbn 1.106m 3.850ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 38.740s 11.531ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 20.220s 448.329us 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.970m 25.915ms 43 50 86.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.158m 3.890ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.140m 2.788ms 49 50 98.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 16.690s 621.714us 49 50 98.00
V2 stress_all keymgr_stress_all 5.981m 62.798ms 47 50 94.00
V2 intr_test keymgr_intr_test 1.030s 16.126us 50 50 100.00
V2 alert_test keymgr_alert_test 1.180s 126.553us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.990s 142.430us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.990s 142.430us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.580s 450.366us 5 5 100.00
keymgr_csr_rw 1.700s 333.275us 16 20 80.00
keymgr_csr_aliasing 9.000s 684.978us 5 5 100.00
keymgr_same_csr_outstanding 3.910s 595.781us 17 20 85.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.580s 450.366us 5 5 100.00
keymgr_csr_rw 1.700s 333.275us 16 20 80.00
keymgr_csr_aliasing 9.000s 684.978us 5 5 100.00
keymgr_same_csr_outstanding 3.910s 595.781us 17 20 85.00
V2 TOTAL 724 740 97.84
V2S sec_cm_additional_check keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
keymgr_tl_intg_err 24.720s 3.433ms 14 20 70.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 14.010s 766.895us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 14.010s 766.895us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 14.010s 766.895us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 14.010s 766.895us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 16.040s 2.145ms 11 20 55.00
V2S prim_count_check keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 24.720s 3.433ms 14 20 70.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 14.010s 766.895us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.179m 7.527ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.950m 49.641ms 50 50 100.00
keymgr_csr_rw 1.700s 333.275us 16 20 80.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.950m 49.641ms 50 50 100.00
keymgr_csr_rw 1.700s 333.275us 16 20 80.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.950m 49.641ms 50 50 100.00
keymgr_csr_rw 1.700s 333.275us 16 20 80.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 20.220s 448.329us 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.140m 2.788ms 49 50 98.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.140m 2.788ms 49 50 98.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.950m 49.641ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 41.010s 4.784ms 49 50 98.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 54.020s 5.784ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 20.220s 448.329us 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 54.020s 5.784ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 54.020s 5.784ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 54.020s 5.784ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 47.280s 1.543ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 54.020s 5.784ms 50 50 100.00
V2S TOTAL 149 165 90.30
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 18.790s 1.097ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1063 1110 95.77

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 16 16 10 62.50
V2S 6 6 3 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.80 99.10 98.03 98.25 100.00 99.12 98.41 91.71

Failure Buckets

Past Results