Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3949079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

583214

1

T1

139

T2

1496

T3

215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4131842	1			T1	1777		T2	1036		T3	1158
values[0x0]	198636	1			T1	37		T2	499		T3	50
values[0x1]	201815	1			T1	43		T2	500		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2685279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1847014

1

T1

675

T2

1605

T3

538

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13131	1			T1	42		T2	11		T5	28
valid_sources[0x01]	18133	1			T2	6		T5	22		T79	3
valid_sources[0x02]	23022	1			T1	3		T2	11		T5	29
valid_sources[0x03]	13756	1			T1	4		T2	7		T5	18
valid_sources[0x04]	33611	1			T2	7		T5	29		T18	1
valid_sources[0x05]	13267	1			T1	5		T2	7		T5	30
valid_sources[0x06]	13126	1			T1	12		T2	9		T5	30
valid_sources[0x07]	15628	1			T2	12		T5	37		T18	2
valid_sources[0x08]	13295	1			T1	1		T2	14		T5	22
valid_sources[0x09]	13045	1			T1	6		T2	4		T5	27
valid_sources[0x0a]	13580	1			T1	12		T2	9		T5	22
valid_sources[0x0b]	15127	1			T2	11		T5	26		T79	1
valid_sources[0x0c]	14661	1			T2	5		T5	23		T79	4
valid_sources[0x0d]	13394	1			T1	20		T2	5		T5	21
valid_sources[0x0e]	13559	1			T1	5		T2	11		T5	28
valid_sources[0x0f]	22432	1			T1	9		T2	7		T5	26
valid_sources[0x10]	13106	1			T2	10		T5	31		T79	1
valid_sources[0x11]	23127	1			T1	1		T2	9		T5	30
valid_sources[0x12]	13529	1			T2	5		T5	20		T18	3
valid_sources[0x13]	36549	1			T1	6		T2	9		T5	34
valid_sources[0x14]	12843	1			T1	19		T2	11		T5	30
valid_sources[0x15]	15671	1			T1	38		T2	7		T5	25
valid_sources[0x16]	13190	1			T2	4		T5	27		T16	1
valid_sources[0x17]	16498	1			T2	6		T5	36		T79	5
valid_sources[0x18]	14458	1			T1	13		T2	10		T5	27
valid_sources[0x19]	12865	1			T2	5		T5	27		T79	3
valid_sources[0x1a]	14236	1			T2	11		T5	29		T16	4
valid_sources[0x1b]	19368	1			T1	3		T2	6		T5	21
valid_sources[0x1c]	14395	1			T1	20		T2	5		T5	34
valid_sources[0x1d]	14164	1			T1	1		T2	12		T5	28
valid_sources[0x1e]	19271	1			T1	10		T2	5		T5	25
valid_sources[0x1f]	25766	1			T2	12		T5	27		T18	1
valid_sources[0x20]	14314	1			T2	6		T5	23		T79	5
valid_sources[0x21]	14334	1			T1	2		T2	4		T5	23
valid_sources[0x22]	30764	1			T1	13		T2	6		T5	33
valid_sources[0x23]	38842	1			T1	12		T2	7		T5	29
valid_sources[0x24]	12421	1			T1	2		T2	3		T5	32
valid_sources[0x25]	13721	1			T1	1		T2	7		T5	32
valid_sources[0x26]	19811	1			T1	40		T2	7		T5	21
valid_sources[0x27]	14665	1			T2	8		T5	27		T79	3
valid_sources[0x28]	12913	1			T1	11		T2	13		T5	28
valid_sources[0x29]	14842	1			T1	2		T2	6		T5	35
valid_sources[0x2a]	21715	1			T1	16		T2	4		T5	29
valid_sources[0x2b]	24829	1			T2	4		T5	22		T79	5
valid_sources[0x2c]	13506	1			T2	8		T5	36		T16	9
valid_sources[0x2d]	101118	1			T1	11		T2	7		T15	61479
valid_sources[0x2e]	25147	1			T2	8		T5	26		T79	1
valid_sources[0x2f]	15430	1			T1	1		T2	10		T5	16
valid_sources[0x30]	22994	1			T1	8		T2	7		T5	25
valid_sources[0x31]	14265	1			T1	1		T2	10		T5	28
valid_sources[0x32]	13206	1			T1	15		T2	3		T5	35
valid_sources[0x33]	14150	1			T2	9		T5	24		T79	1
valid_sources[0x34]	13205	1			T1	1		T2	5		T5	15
valid_sources[0x35]	15993	1			T2	7		T5	44		T79	2
valid_sources[0x36]	12961	1			T1	8		T2	8		T5	28
valid_sources[0x37]	13083	1			T1	3		T2	13		T5	30
valid_sources[0x38]	14467	1			T1	8		T2	12		T5	32
valid_sources[0x39]	16012	1			T1	1		T2	5		T5	28
valid_sources[0x3a]	13014	1			T1	6		T2	4		T5	30
valid_sources[0x3b]	13944	1			T2	8		T5	26		T16	6
valid_sources[0x3c]	16640	1			T1	7		T2	6		T5	31
valid_sources[0x3d]	12798	1			T1	6		T2	9		T5	30
valid_sources[0x3e]	20198	1			T1	26		T2	12		T5	31
valid_sources[0x3f]	14216	1			T1	1		T2	10		T5	24
valid_sources[0x40]	15457	1			T1	11		T2	5		T5	18
valid_sources[0x41]	13020	1			T1	15		T2	6		T5	31
valid_sources[0x42]	15127	1			T1	35		T2	9		T5	30
valid_sources[0x43]	13786	1			T1	83		T2	11		T5	36
valid_sources[0x44]	21628	1			T2	6		T5	33		T79	4
valid_sources[0x45]	14352	1			T1	4		T2	7		T5	37
valid_sources[0x46]	21564	1			T1	4		T2	11		T5	25
valid_sources[0x47]	13766	1			T2	7		T5	26		T79	4
valid_sources[0x48]	12882	1			T2	10		T5	24		T18	10
valid_sources[0x49]	14557	1			T1	13		T2	10		T5	47
valid_sources[0x4a]	15471	1			T1	12		T2	6		T5	28
valid_sources[0x4b]	44896	1			T1	39		T2	8		T5	29
valid_sources[0x4c]	16066	1			T1	2		T2	4		T5	29
valid_sources[0x4d]	13791	1			T2	8		T5	25		T79	3
valid_sources[0x4e]	14220	1			T1	20		T2	5		T5	37
valid_sources[0x4f]	12842	1			T1	11		T2	7		T5	21
valid_sources[0x50]	12885	1			T2	12		T5	29		T18	9
valid_sources[0x51]	12241	1			T1	9		T2	7		T5	34
valid_sources[0x52]	30670	1			T1	9		T2	8		T5	26
valid_sources[0x53]	14315	1			T2	10		T5	33		T18	1
valid_sources[0x54]	37233	1			T1	25		T2	7		T5	21
valid_sources[0x55]	13063	1			T1	2		T2	6		T5	27
valid_sources[0x56]	33190	1			T2	6		T5	27		T79	5
valid_sources[0x57]	12789	1			T1	11		T2	2		T5	27
valid_sources[0x58]	13266	1			T1	1		T2	10		T5	28
valid_sources[0x59]	16328	1			T2	5		T5	33		T79	3
valid_sources[0x5a]	15863	1			T2	12		T5	31		T79	4
valid_sources[0x5b]	28739	1			T1	2		T2	12		T5	28
valid_sources[0x5c]	13937	1			T1	8		T2	6		T5	23
valid_sources[0x5d]	157201	1			T2	7		T5	34		T17	2927
valid_sources[0x5e]	13326	1			T2	15		T5	25		T79	2
valid_sources[0x5f]	33946	1			T1	12		T2	9		T5	40
valid_sources[0x60]	16806	1			T1	4		T2	4		T5	22
valid_sources[0x61]	13122	1			T2	8		T5	28		T79	3
valid_sources[0x62]	15500	1			T2	11		T5	35		T16	6
valid_sources[0x63]	18467	1			T2	7		T5	30		T18	10
valid_sources[0x64]	13844	1			T1	3		T2	1		T5	36
valid_sources[0x65]	13570	1			T1	2		T2	7		T5	26
valid_sources[0x66]	30586	1			T1	4		T2	3		T5	28
valid_sources[0x67]	13254	1			T1	3		T2	6		T5	23
valid_sources[0x68]	16387	1			T2	3		T5	27		T79	2
valid_sources[0x69]	14849	1			T2	5		T5	32		T18	4
valid_sources[0x6a]	13759	1			T1	4		T2	9		T5	16
valid_sources[0x6b]	14475	1			T2	8		T5	16		T79	1
valid_sources[0x6c]	15064	1			T1	8		T2	10		T5	21
valid_sources[0x6d]	17609	1			T1	15		T2	10		T5	30
valid_sources[0x6e]	12437	1			T1	3		T2	7		T5	21
valid_sources[0x6f]	42041	1			T1	15		T2	12		T5	33
valid_sources[0x70]	13764	1			T2	6		T5	22		T16	15
valid_sources[0x71]	13449	1			T1	18		T2	12		T5	30
valid_sources[0x72]	14201	1			T2	6		T5	27		T79	3
valid_sources[0x73]	23237	1			T1	11		T2	6		T5	28
valid_sources[0x74]	13065	1			T1	1		T2	11		T5	21
valid_sources[0x75]	13583	1			T1	2		T2	4		T5	49
valid_sources[0x76]	13215	1			T1	8		T2	7		T5	32
valid_sources[0x77]	13952	1			T1	6		T5	25		T79	4
valid_sources[0x78]	13290	1			T1	7		T2	9		T5	30
valid_sources[0x79]	14316	1			T2	9		T5	30		T16	9
valid_sources[0x7a]	12796	1			T1	1		T2	13		T5	36
valid_sources[0x7b]	20045	1			T2	5		T5	26		T18	5
valid_sources[0x7c]	13830	1			T2	7		T5	30		T16	2
valid_sources[0x7d]	14771	1			T2	6		T5	26		T79	1
valid_sources[0x7e]	14759	1			T2	9		T5	26		T79	1
valid_sources[0x7f]	16275	1			T2	7		T5	32		T18	5
valid_sources[0x80]	16742	1			T2	6		T5	20		T18	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308198

1

T1

117

T2

593

T3

179

values[0x0]

all_enables

biggest_size

144545

1

T1

15

T2

454

T3

18

values[0x1]

all_enables

biggest_size

130471

1

T1

7

T2

449

T3

18