Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26319940	20830	0	0
attest_sw_binding_0_rd_A	26319940	1105	0	0
attest_sw_binding_1_rd_A	26319940	1151	0	0
attest_sw_binding_2_rd_A	26319940	1104	0	0
attest_sw_binding_3_rd_A	26319940	1011	0	0
attest_sw_binding_4_rd_A	26319940	957	0	0
attest_sw_binding_5_rd_A	26319940	1119	0	0
attest_sw_binding_6_rd_A	26319940	1196	0	0
attest_sw_binding_7_rd_A	26319940	1024	0	0
intr_enable_rd_A	26319940	1566	0	0
key_version_rd_A	26319940	1069	0	0
max_creator_key_ver_regwen_rd_A	26319940	988	0	0
max_owner_int_key_ver_regwen_rd_A	26319940	964	0	0
max_owner_key_ver_regwen_rd_A	26319940	1028	0	0
reseed_interval_regwen_rd_A	26319940	1083	0	0
salt_0_rd_A	26319940	1052	0	0
salt_1_rd_A	26319940	1117	0	0
salt_2_rd_A	26319940	1035	0	0
salt_3_rd_A	26319940	967	0	0
salt_4_rd_A	26319940	1022	0	0
salt_5_rd_A	26319940	1065	0	0
salt_6_rd_A	26319940	963	0	0
salt_7_rd_A	26319940	1041	0	0
sealing_sw_binding_0_rd_A	26319940	1019	0	0
sealing_sw_binding_1_rd_A	26319940	1069	0	0
sealing_sw_binding_2_rd_A	26319940	1116	0	0
sealing_sw_binding_3_rd_A	26319940	1107	0	0
sealing_sw_binding_4_rd_A	26319940	1078	0	0
sealing_sw_binding_5_rd_A	26319940	1103	0	0
sealing_sw_binding_6_rd_A	26319940	1054	0	0
sealing_sw_binding_7_rd_A	26319940	1051	0	0
sideload_clear_rd_A	26319940	1062	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	20830	0	0
T2	17911	66	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	33	0	0
T58	0	610	0	0
T79	8911	0	0	0
T94	0	17	0	0
T96	0	461	0	0
T113	0	653	0	0
T114	0	453	0	0
T115	0	111	0	0
T116	0	281	0	0
T139	0	19	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1105	0	0
T2	17911	33	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	28	0	0
T79	8911	0	0	0
T94	0	14	0	0
T108	0	78	0	0
T109	0	79	0	0
T127	0	7	0	0
T129	0	18	0	0
T139	0	38	0	0
T147	0	3	0	0
T148	0	7	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1151	0	0
T2	17911	55	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	34	0	0
T79	8911	0	0	0
T94	0	3	0	0
T109	0	77	0	0
T118	0	8	0	0
T127	0	14	0	0
T129	0	7	0	0
T139	0	29	0	0
T147	0	4	0	0
T148	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1104	0	0
T2	17911	56	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	32	0	0
T79	8911	0	0	0
T94	0	14	0	0
T109	0	56	0	0
T125	0	1	0	0
T127	0	10	0	0
T129	0	19	0	0
T139	0	37	0	0
T147	0	4	0	0
T148	0	10	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1011	0	0
T2	17911	48	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	22	0	0
T79	8911	0	0	0
T94	0	13	0	0
T109	0	63	0	0
T125	0	3	0	0
T127	0	2	0	0
T129	0	22	0	0
T139	0	22	0	0
T147	0	4	0	0
T148	0	11	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	957	0	0
T2	17911	36	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	15	0	0
T79	8911	0	0	0
T94	0	6	0	0
T108	0	58	0	0
T109	0	46	0	0
T111	0	32	0	0
T127	0	8	0	0
T129	0	2	0	0
T139	0	23	0	0
T148	0	10	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1119	0	0
T2	17911	30	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	28	0	0
T79	8911	0	0	0
T94	0	6	0	0
T108	0	59	0	0
T109	0	70	0	0
T127	0	5	0	0
T129	0	12	0	0
T139	0	21	0	0
T147	0	1	0	0
T148	0	4	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1196	0	0
T2	17911	56	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	26	0	0
T79	8911	0	0	0
T94	0	13	0	0
T108	0	51	0	0
T109	0	72	0	0
T127	0	10	0	0
T129	0	27	0	0
T139	0	47	0	0
T147	0	2	0	0
T148	0	6	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1024	0	0
T2	17911	54	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	33	0	0
T79	8911	0	0	0
T94	0	8	0	0
T108	0	33	0	0
T109	0	66	0	0
T125	0	6	0	0
T127	0	21	0	0
T129	0	26	0	0
T139	0	39	0	0
T148	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1566	0	0
T2	17911	79	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T8	0	10	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	34	0	0
T46	0	12	0	0
T79	8911	0	0	0
T94	0	5	0	0
T109	0	76	0	0
T139	0	37	0	0
T147	0	4	0	0
T148	0	5	0	0
T168	0	25	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1069	0	0
T2	17911	83	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	24	0	0
T79	8911	0	0	0
T94	0	22	0	0
T108	0	70	0	0
T109	0	56	0	0
T127	0	21	0	0
T129	0	12	0	0
T139	0	19	0	0
T147	0	2	0	0
T148	0	9	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	988	0	0
T2	17911	56	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	13	0	0
T79	8911	0	0	0
T94	0	9	0	0
T108	0	48	0	0
T109	0	78	0	0
T127	0	1	0	0
T129	0	12	0	0
T139	0	26	0	0
T147	0	8	0	0
T148	0	8	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	964	0	0
T2	17911	56	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	41	0	0
T79	8911	0	0	0
T94	0	16	0	0
T108	0	54	0	0
T109	0	54	0	0
T125	0	5	0	0
T127	0	12	0	0
T129	0	16	0	0
T139	0	10	0	0
T148	0	5	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1028	0	0
T2	17911	51	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	23	0	0
T79	8911	0	0	0
T94	0	5	0	0
T109	0	50	0	0
T125	0	4	0	0
T127	0	7	0	0
T129	0	7	0	0
T139	0	30	0	0
T147	0	10	0	0
T148	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1083	0	0
T2	17911	67	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	39	0	0
T79	8911	0	0	0
T94	0	11	0	0
T108	0	53	0	0
T109	0	67	0	0
T125	0	2	0	0
T127	0	10	0	0
T129	0	8	0	0
T139	0	23	0	0
T148	0	11	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1052	0	0
T2	17911	49	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	11	0	0
T79	8911	0	0	0
T108	0	61	0	0
T109	0	71	0	0
T111	0	30	0	0
T127	0	13	0	0
T129	0	19	0	0
T139	0	49	0	0
T148	0	4	0	0
T169	0	13	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1117	0	0
T2	17911	58	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	26	0	0
T79	8911	0	0	0
T94	0	7	0	0
T108	0	48	0	0
T109	0	60	0	0
T125	0	2	0	0
T127	0	17	0	0
T129	0	10	0	0
T139	0	28	0	0
T148	0	6	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1035	0	0
T2	17911	27	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	34	0	0
T79	8911	0	0	0
T108	0	52	0	0
T109	0	75	0	0
T125	0	4	0	0
T127	0	4	0	0
T129	0	4	0	0
T139	0	39	0	0
T147	0	2	0	0
T148	0	10	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	967	0	0
T2	17911	47	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	41	0	0
T79	8911	0	0	0
T94	0	10	0	0
T108	0	49	0	0
T109	0	65	0	0
T127	0	16	0	0
T129	0	5	0	0
T139	0	28	0	0
T147	0	2	0	0
T148	0	13	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1022	0	0
T2	17911	45	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	16	0	0
T79	8911	0	0	0
T94	0	7	0	0
T109	0	71	0	0
T125	0	5	0	0
T127	0	3	0	0
T129	0	8	0	0
T139	0	32	0	0
T147	0	3	0	0
T148	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1065	0	0
T2	17911	70	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	42	0	0
T79	8911	0	0	0
T94	0	8	0	0
T108	0	55	0	0
T109	0	60	0	0
T127	0	9	0	0
T129	0	11	0	0
T139	0	36	0	0
T147	0	6	0	0
T148	0	7	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	963	0	0
T2	17911	39	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	22	0	0
T79	8911	0	0	0
T94	0	11	0	0
T108	0	41	0	0
T109	0	61	0	0
T111	0	21	0	0
T125	0	3	0	0
T127	0	13	0	0
T139	0	30	0	0
T148	0	8	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1041	0	0
T2	17911	36	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	26	0	0
T79	8911	0	0	0
T94	0	16	0	0
T109	0	55	0	0
T118	0	1	0	0
T125	0	4	0	0
T127	0	13	0	0
T139	0	35	0	0
T147	0	1	0	0
T148	0	2	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1019	0	0
T2	17911	69	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	35	0	0
T79	8911	0	0	0
T94	0	20	0	0
T108	0	55	0	0
T109	0	47	0	0
T127	0	22	0	0
T129	0	3	0	0
T139	0	23	0	0
T147	0	1	0	0
T148	0	4	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1069	0	0
T2	17911	64	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	19	0	0
T79	8911	0	0	0
T94	0	8	0	0
T109	0	74	0	0
T125	0	7	0	0
T127	0	24	0	0
T129	0	9	0	0
T139	0	31	0	0
T147	0	13	0	0
T148	0	2	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1116	0	0
T2	17911	42	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	25	0	0
T79	8911	0	0	0
T94	0	32	0	0
T108	0	64	0	0
T109	0	59	0	0
T127	0	22	0	0
T129	0	20	0	0
T139	0	36	0	0
T147	0	9	0	0
T148	0	11	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1107	0	0
T2	17911	70	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	34	0	0
T79	8911	0	0	0
T94	0	6	0	0
T108	0	62	0	0
T109	0	63	0	0
T125	0	3	0	0
T127	0	24	0	0
T129	0	3	0	0
T139	0	38	0	0
T148	0	9	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1078	0	0
T2	17911	33	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	17	0	0
T79	8911	0	0	0
T94	0	25	0	0
T108	0	52	0	0
T109	0	50	0	0
T127	0	10	0	0
T129	0	10	0	0
T139	0	49	0	0
T147	0	3	0	0
T148	0	8	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1103	0	0
T2	17911	63	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	20	0	0
T79	8911	0	0	0
T94	0	3	0	0
T108	0	51	0	0
T109	0	55	0	0
T127	0	34	0	0
T129	0	8	0	0
T139	0	29	0	0
T147	0	10	0	0
T148	0	2	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1054	0	0
T2	17911	47	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	39	0	0
T79	8911	0	0	0
T94	0	7	0	0
T109	0	50	0	0
T118	0	4	0	0
T125	0	1	0	0
T127	0	12	0	0
T139	0	39	0	0
T147	0	2	0	0
T148	0	10	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1051	0	0
T2	17911	63	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	24	0	0
T79	8911	0	0	0
T94	0	7	0	0
T108	0	41	0	0
T109	0	56	0	0
T125	0	1	0	0
T127	0	12	0	0
T129	0	13	0	0
T139	0	36	0	0
T148	0	4	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26319940	1062	0	0
T2	17911	43	0	0
T3	7357	0	0	0
T4	18572	0	0	0
T5	99189	0	0	0
T15	193627	0	0	0
T16	5846	0	0	0
T17	12521	0	0	0
T18	2047	0	0	0
T19	11667	0	0	0
T44	0	23	0	0
T79	8911	0	0	0
T94	0	30	0	0
T109	0	71	0	0
T125	0	2	0	0
T127	0	2	0	0
T129	0	8	0	0
T139	0	16	0	0
T147	0	10	0	0
T148	0	5	0	0