Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4281828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

581101

1

T1

2128

T2

671

T3

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4469129	1			T1	3380		T2	5438		T3	914
values[0x0]	195224	1			T1	787		T2	229		T3	67
values[0x1]	198576	1			T1	755		T2	216		T3	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2909017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1953912

1

T1

2746

T2

2354

T3

475

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16554	1			T2	7		T3	2		T4	56
valid_sources[0x01]	18557	1			T2	30		T3	7		T4	66
valid_sources[0x02]	16284	1			T3	1		T4	37		T13	11
valid_sources[0x03]	18786	1			T2	133		T3	9		T4	40
valid_sources[0x04]	17120	1			T2	25		T3	6		T4	48
valid_sources[0x05]	15686	1			T2	77		T3	8		T4	46
valid_sources[0x06]	19656	1			T2	43		T3	4		T4	39
valid_sources[0x07]	16356	1			T2	4		T3	3		T4	34
valid_sources[0x08]	19603	1			T2	27		T3	10		T4	47
valid_sources[0x09]	31455	1			T2	32		T3	1		T4	60
valid_sources[0x0a]	18268	1			T2	27		T3	6		T4	49
valid_sources[0x0b]	16019	1			T2	83		T3	6		T4	40
valid_sources[0x0c]	16632	1			T2	4		T3	4		T4	50
valid_sources[0x0d]	36957	1			T2	6		T3	4		T4	52
valid_sources[0x0e]	24034	1			T2	25		T3	1		T4	40
valid_sources[0x0f]	16951	1			T2	15		T3	3		T4	37
valid_sources[0x10]	21644	1			T2	60		T3	3		T4	53
valid_sources[0x11]	52501	1			T2	1		T4	55		T14	7
valid_sources[0x12]	17053	1			T2	3		T3	5		T4	52
valid_sources[0x13]	16651	1			T2	71		T3	7		T4	36
valid_sources[0x14]	16561	1			T2	18		T3	7		T4	56
valid_sources[0x15]	17348	1			T2	10		T3	9		T4	27
valid_sources[0x16]	15668	1			T2	5		T3	5		T4	50
valid_sources[0x17]	15884	1			T2	1		T3	3		T4	43
valid_sources[0x18]	16799	1			T2	51		T3	11		T4	49
valid_sources[0x19]	17133	1			T2	40		T3	8		T4	52
valid_sources[0x1a]	19172	1			T2	30		T3	9		T4	34
valid_sources[0x1b]	18399	1			T3	1		T4	49		T13	3
valid_sources[0x1c]	21187	1			T2	5		T3	4		T4	49
valid_sources[0x1d]	23233	1			T2	19		T3	1		T4	41
valid_sources[0x1e]	15692	1			T2	5		T4	40		T13	6
valid_sources[0x1f]	17692	1			T2	9		T3	3		T4	40
valid_sources[0x20]	16150	1			T2	21		T3	6		T4	41
valid_sources[0x21]	15978	1			T2	73		T3	4		T4	49
valid_sources[0x22]	16385	1			T2	17		T3	8		T4	43
valid_sources[0x23]	16389	1			T2	9		T3	3		T4	42
valid_sources[0x24]	18956	1			T2	14		T3	8		T4	34
valid_sources[0x25]	17015	1			T2	14		T3	2		T4	55
valid_sources[0x26]	17560	1			T2	5		T3	4		T4	47
valid_sources[0x27]	16671	1			T2	12		T4	52		T14	1
valid_sources[0x28]	17916	1			T2	4		T3	3		T4	49
valid_sources[0x29]	16595	1			T2	1		T3	3		T4	74
valid_sources[0x2a]	16736	1			T2	36		T3	9		T4	43
valid_sources[0x2b]	41045	1			T2	5		T3	5		T4	46
valid_sources[0x2c]	17045	1			T2	50		T4	44		T13	8
valid_sources[0x2d]	16582	1			T2	5		T3	6		T4	44
valid_sources[0x2e]	44491	1			T2	3		T3	9		T4	50
valid_sources[0x2f]	36358	1			T2	14		T3	4		T4	44
valid_sources[0x30]	19082	1			T1	1		T2	9		T3	4
valid_sources[0x31]	16516	1			T2	45		T3	5		T4	49
valid_sources[0x32]	19053	1			T2	14		T3	2		T4	43
valid_sources[0x33]	16911	1			T2	16		T3	6		T4	53
valid_sources[0x34]	19548	1			T2	49		T3	9		T4	52
valid_sources[0x35]	16383	1			T4	46		T13	6		T14	5
valid_sources[0x36]	16236	1			T2	5		T3	5		T4	56
valid_sources[0x37]	16427	1			T2	13		T3	5		T4	36
valid_sources[0x38]	16993	1			T2	51		T3	4		T4	48
valid_sources[0x39]	18051	1			T2	12		T3	2		T4	59
valid_sources[0x3a]	16469	1			T2	9		T3	7		T4	57
valid_sources[0x3b]	16228	1			T2	37		T3	6		T4	50
valid_sources[0x3c]	16158	1			T2	76		T3	4		T4	62
valid_sources[0x3d]	16070	1			T2	10		T3	4		T4	57
valid_sources[0x3e]	16687	1			T2	8		T3	2		T4	51
valid_sources[0x3f]	20235	1			T2	37		T3	6		T4	44
valid_sources[0x40]	17999	1			T2	23		T3	3		T4	43
valid_sources[0x41]	48287	1			T2	17		T3	6		T4	40
valid_sources[0x42]	24970	1			T2	10		T3	6		T4	58
valid_sources[0x43]	23067	1			T2	19		T3	1		T4	44
valid_sources[0x44]	18719	1			T2	1		T3	1		T4	53
valid_sources[0x45]	17124	1			T1	1		T2	5		T3	5
valid_sources[0x46]	19077	1			T1	1		T2	3		T3	4
valid_sources[0x47]	17014	1			T2	36		T3	6		T4	38
valid_sources[0x48]	16937	1			T2	41		T3	5		T4	49
valid_sources[0x49]	17933	1			T2	13		T3	3		T4	27
valid_sources[0x4a]	16294	1			T2	24		T3	4		T4	44
valid_sources[0x4b]	18354	1			T2	7		T3	2		T4	51
valid_sources[0x4c]	17863	1			T2	75		T3	1		T4	43
valid_sources[0x4d]	18068	1			T2	40		T4	42		T14	6
valid_sources[0x4e]	21464	1			T2	10		T3	4		T4	48
valid_sources[0x4f]	15584	1			T2	60		T3	5		T4	37
valid_sources[0x50]	18418	1			T2	28		T3	2		T4	61
valid_sources[0x51]	17566	1			T2	3		T3	12		T4	52
valid_sources[0x52]	16026	1			T2	29		T3	2		T4	58
valid_sources[0x53]	21752	1			T2	18		T3	5		T4	62
valid_sources[0x54]	16326	1			T2	17		T3	3		T4	48
valid_sources[0x55]	16330	1			T2	68		T3	5		T4	41
valid_sources[0x56]	19175	1			T2	23		T4	52		T13	6
valid_sources[0x57]	16440	1			T2	4		T3	6		T4	42
valid_sources[0x58]	15920	1			T2	12		T3	2		T4	49
valid_sources[0x59]	16046	1			T2	16		T3	5		T4	52
valid_sources[0x5a]	19904	1			T2	34		T3	5		T4	47
valid_sources[0x5b]	17607	1			T2	6		T3	6		T4	65
valid_sources[0x5c]	15900	1			T2	2		T3	3		T4	45
valid_sources[0x5d]	21345	1			T2	33		T4	48		T13	3
valid_sources[0x5e]	17938	1			T2	67		T3	8		T4	47
valid_sources[0x5f]	23993	1			T2	2		T3	3		T4	41
valid_sources[0x60]	15745	1			T2	7		T3	3		T4	36
valid_sources[0x61]	45055	1			T2	29		T3	2		T4	40
valid_sources[0x62]	17618	1			T2	4		T3	5		T4	36
valid_sources[0x63]	19075	1			T2	1		T3	4		T4	46
valid_sources[0x64]	20643	1			T2	34		T3	1		T4	45
valid_sources[0x65]	18200	1			T2	22		T3	9		T4	52
valid_sources[0x66]	16159	1			T2	18		T3	7		T4	52
valid_sources[0x67]	19472	1			T2	58		T3	1		T4	48
valid_sources[0x68]	16366	1			T2	2		T3	4		T4	57
valid_sources[0x69]	18426	1			T2	3		T3	2		T4	48
valid_sources[0x6a]	17827	1			T1	1		T2	49		T3	6
valid_sources[0x6b]	16877	1			T2	2		T3	1		T4	43
valid_sources[0x6c]	16758	1			T2	12		T3	4		T4	38
valid_sources[0x6d]	19174	1			T2	74		T3	2		T4	47
valid_sources[0x6e]	16897	1			T2	3		T3	6		T4	35
valid_sources[0x6f]	16438	1			T2	19		T4	45		T13	1
valid_sources[0x70]	16524	1			T3	6		T4	47		T13	9
valid_sources[0x71]	16565	1			T2	23		T3	3		T4	48
valid_sources[0x72]	16522	1			T2	18		T3	4		T4	48
valid_sources[0x73]	16661	1			T2	45		T3	2		T4	66
valid_sources[0x74]	18425	1			T2	29		T3	3		T4	54
valid_sources[0x75]	16952	1			T2	38		T3	7		T4	51
valid_sources[0x76]	16563	1			T3	3		T4	51		T13	4
valid_sources[0x77]	16239	1			T2	21		T3	9		T4	51
valid_sources[0x78]	17156	1			T3	1		T4	42		T13	12
valid_sources[0x79]	29914	1			T2	27		T3	5		T4	53
valid_sources[0x7a]	17808	1			T2	2		T3	1		T4	47
valid_sources[0x7b]	18494	1			T2	38		T3	2		T4	37
valid_sources[0x7c]	17693	1			T2	14		T3	2		T4	58
valid_sources[0x7d]	25274	1			T2	9		T3	7		T4	45
valid_sources[0x7e]	16283	1			T2	14		T3	3		T4	45
valid_sources[0x7f]	15466	1			T2	16		T3	8		T4	59
valid_sources[0x80]	36243	1			T2	5		T3	14		T4	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

311465

1

T1

1330

T2

355

T3

204

values[0x0]

all_enables

biggest_size

141562

1

T1

476

T2

169

T3

30

values[0x1]

all_enables

biggest_size

128074

1

T1

322

T2

147

T3

18