Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32783348	16808	0	0
attest_sw_binding_0_rd_A	32783348	946	0	0
attest_sw_binding_1_rd_A	32783348	950	0	0
attest_sw_binding_2_rd_A	32783348	1066	0	0
attest_sw_binding_3_rd_A	32783348	1084	0	0
attest_sw_binding_4_rd_A	32783348	962	0	0
attest_sw_binding_5_rd_A	32783348	968	0	0
attest_sw_binding_6_rd_A	32783348	923	0	0
attest_sw_binding_7_rd_A	32783348	926	0	0
intr_enable_rd_A	32783348	1688	0	0
key_version_rd_A	32783348	1060	0	0
max_creator_key_ver_regwen_rd_A	32783348	917	0	0
max_owner_int_key_ver_regwen_rd_A	32783348	1010	0	0
max_owner_key_ver_regwen_rd_A	32783348	1032	0	0
reseed_interval_regwen_rd_A	32783348	953	0	0
salt_0_rd_A	32783348	961	0	0
salt_1_rd_A	32783348	995	0	0
salt_2_rd_A	32783348	1034	0	0
salt_3_rd_A	32783348	963	0	0
salt_4_rd_A	32783348	925	0	0
salt_5_rd_A	32783348	978	0	0
salt_6_rd_A	32783348	1099	0	0
salt_7_rd_A	32783348	988	0	0
sealing_sw_binding_0_rd_A	32783348	1055	0	0
sealing_sw_binding_1_rd_A	32783348	851	0	0
sealing_sw_binding_2_rd_A	32783348	892	0	0
sealing_sw_binding_3_rd_A	32783348	995	0	0
sealing_sw_binding_4_rd_A	32783348	992	0	0
sealing_sw_binding_5_rd_A	32783348	994	0	0
sealing_sw_binding_6_rd_A	32783348	930	0	0
sealing_sw_binding_7_rd_A	32783348	976	0	0
sideload_clear_rd_A	32783348	983	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	16808	0	0
T14	9604	17	0	0
T15	13347	0	0	0
T16	4894	0	0	0
T17	2774	0	0	0
T40	21630	0	0	0
T45	4518	0	0	0
T78	8874	0	0	0
T79	4705	0	0	0
T93	1259	0	0	0
T94	0	4	0	0
T105	0	138	0	0
T106	0	31	0	0
T107	0	1	0	0
T112	0	30	0	0
T113	0	525	0	0
T121	0	436	0	0
T122	0	8	0	0
T123	2162	0	0	0
T168	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	946	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	26	0	0
T112	15357	22	0	0
T117	0	48	0	0
T122	2339	1	0	0
T125	0	4	0	0
T133	1094	0	0	0
T165	0	17	0	0
T169	0	5	0	0
T170	0	8	0	0
T171	0	81	0	0
T172	0	13	0	0
T173	22492	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	950	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	4	0	0
T112	15357	30	0	0
T117	20074	41	0	0
T125	0	22	0	0
T165	0	10	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	88	0	0
T172	0	4	0	0
T173	22492	0	0	0
T174	0	57	0	0
T175	35002	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1066	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	9	0	0
T112	15357	52	0	0
T117	0	37	0	0
T122	2339	5	0	0
T125	0	2	0	0
T133	1094	0	0	0
T149	0	7	0	0
T165	0	16	0	0
T169	0	3	0	0
T170	0	3	0	0
T171	0	74	0	0
T173	22492	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1084	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	32	0	0
T112	15357	32	0	0
T117	0	12	0	0
T122	2339	10	0	0
T125	0	8	0	0
T133	1094	0	0	0
T149	0	18	0	0
T165	0	16	0	0
T169	0	8	0	0
T170	0	4	0	0
T171	0	109	0	0
T173	22492	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	962	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	25	0	0
T112	15357	36	0	0
T117	0	31	0	0
T122	2339	7	0	0
T133	1094	0	0	0
T165	0	23	0	0
T169	0	2	0	0
T170	0	11	0	0
T171	0	84	0	0
T172	0	4	0	0
T173	22492	0	0	0
T174	0	69	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	968	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	9	0	0
T112	15357	46	0	0
T117	0	22	0	0
T122	2339	4	0	0
T133	1094	0	0	0
T149	0	2	0	0
T165	0	12	0	0
T169	0	7	0	0
T170	0	3	0	0
T171	0	60	0	0
T172	0	12	0	0
T173	22492	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	923	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	30	0	0
T112	15357	39	0	0
T117	20074	20	0	0
T165	0	20	0	0
T169	0	6	0	0
T170	0	2	0	0
T171	0	76	0	0
T172	0	9	0	0
T173	22492	0	0	0
T174	0	53	0	0
T175	35002	0	0	0
T176	0	6	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	926	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T112	15357	39	0	0
T117	0	22	0	0
T122	2339	3	0	0
T125	0	4	0	0
T133	1094	0	0	0
T134	2290	0	0	0
T149	0	3	0	0
T165	0	15	0	0
T169	0	5	0	0
T170	0	3	0	0
T171	0	57	0	0
T172	0	5	0	0
T173	22492	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1688	0	0
T4	146660	20	0	0
T12	24651	0	0	0
T13	7442	0	0	0
T14	9604	0	0	0
T15	13347	0	0	0
T16	4894	0	0	0
T17	2774	0	0	0
T78	8874	0	0	0
T79	4705	0	0	0
T93	1259	0	0	0
T105	0	40	0	0
T112	0	30	0	0
T117	0	21	0	0
T122	0	4	0	0
T133	0	24	0	0
T177	0	28	0	0
T178	0	34	0	0
T179	0	17	0	0
T180	0	16	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1060	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	23	0	0
T112	15357	21	0	0
T117	0	39	0	0
T122	2339	3	0	0
T125	0	5	0	0
T133	1094	0	0	0
T149	0	6	0	0
T165	0	14	0	0
T169	0	2	0	0
T170	0	13	0	0
T171	0	82	0	0
T173	22492	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	917	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	11	0	0
T112	15357	31	0	0
T117	0	16	0	0
T122	2339	6	0	0
T133	1094	0	0	0
T165	0	23	0	0
T169	0	4	0	0
T170	0	3	0	0
T171	0	71	0	0
T173	22492	0	0	0
T174	0	72	0	0
T176	0	2	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1010	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	15	0	0
T112	15357	36	0	0
T117	20074	19	0	0
T125	0	6	0	0
T149	0	9	0	0
T165	0	31	0	0
T169	0	5	0	0
T170	0	8	0	0
T171	0	84	0	0
T172	0	11	0	0
T173	22492	0	0	0
T175	35002	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1032	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	33	0	0
T112	15357	24	0	0
T117	0	41	0	0
T122	2339	4	0	0
T133	1094	0	0	0
T165	0	29	0	0
T169	0	5	0	0
T170	0	18	0	0
T171	0	89	0	0
T172	0	9	0	0
T173	22492	0	0	0
T174	0	60	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	953	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	22	0	0
T112	15357	30	0	0
T117	0	19	0	0
T122	2339	7	0	0
T133	1094	0	0	0
T165	0	10	0	0
T169	0	2	0	0
T170	0	12	0	0
T171	0	70	0	0
T173	22492	0	0	0
T174	0	67	0	0
T176	0	6	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	961	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	20	0	0
T112	15357	36	0	0
T117	0	25	0	0
T122	2339	7	0	0
T125	0	5	0	0
T133	1094	0	0	0
T165	0	17	0	0
T169	0	7	0	0
T170	0	3	0	0
T171	0	65	0	0
T172	0	3	0	0
T173	22492	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	995	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	16	0	0
T112	15357	28	0	0
T117	0	33	0	0
T122	2339	1	0	0
T125	0	9	0	0
T133	1094	0	0	0
T165	0	25	0	0
T169	0	1	0	0
T170	0	13	0	0
T171	0	62	0	0
T173	22492	0	0	0
T174	0	70	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1034	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	23	0	0
T112	15357	31	0	0
T117	0	26	0	0
T122	2339	3	0	0
T125	0	4	0	0
T133	1094	0	0	0
T165	0	23	0	0
T170	0	10	0	0
T171	0	74	0	0
T172	0	6	0	0
T173	22492	0	0	0
T174	0	88	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	963	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	25	0	0
T112	15357	33	0	0
T117	0	23	0	0
T122	2339	3	0	0
T133	1094	0	0	0
T149	0	3	0	0
T165	0	25	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	72	0	0
T172	0	7	0	0
T173	22492	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	925	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	24	0	0
T112	15357	11	0	0
T117	0	24	0	0
T122	2339	1	0	0
T125	0	3	0	0
T133	1094	0	0	0
T165	0	22	0	0
T170	0	17	0	0
T171	0	70	0	0
T172	0	4	0	0
T173	22492	0	0	0
T174	0	64	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	978	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	20	0	0
T112	15357	39	0	0
T117	20074	33	0	0
T165	0	27	0	0
T170	0	10	0	0
T171	0	79	0	0
T173	22492	0	0	0
T174	0	50	0	0
T175	35002	0	0	0
T176	0	6	0	0
T181	0	1	0	0
T182	0	4	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1099	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	2	0	0
T112	15357	43	0	0
T117	0	50	0	0
T122	2339	7	0	0
T125	0	3	0	0
T133	1094	0	0	0
T149	0	8	0	0
T165	0	22	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	61	0	0
T173	22492	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	988	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	20	0	0
T112	15357	23	0	0
T117	20074	26	0	0
T125	0	6	0	0
T165	0	25	0	0
T170	0	13	0	0
T171	0	69	0	0
T172	0	4	0	0
T173	22492	0	0	0
T174	0	74	0	0
T175	35002	0	0	0
T176	0	3	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	1055	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	16	0	0
T112	15357	18	0	0
T117	20074	43	0	0
T125	0	4	0	0
T149	0	9	0	0
T165	0	37	0	0
T169	0	3	0	0
T170	0	18	0	0
T171	0	74	0	0
T173	22492	0	0	0
T174	0	67	0	0
T175	35002	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	851	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	5	0	0
T112	15357	15	0	0
T117	20074	20	0	0
T165	0	13	0	0
T169	0	3	0	0
T170	0	5	0	0
T171	0	65	0	0
T172	0	3	0	0
T173	22492	0	0	0
T174	0	60	0	0
T175	35002	0	0	0
T176	0	6	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	892	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	21	0	0
T112	15357	28	0	0
T117	0	32	0	0
T122	2339	2	0	0
T125	0	6	0	0
T133	1094	0	0	0
T165	0	11	0	0
T169	0	7	0	0
T170	0	5	0	0
T171	0	71	0	0
T173	22492	0	0	0
T174	0	48	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	995	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	26	0	0
T112	15357	27	0	0
T117	20074	22	0	0
T165	0	17	0	0
T169	0	6	0	0
T170	0	12	0	0
T171	0	72	0	0
T172	0	18	0	0
T173	22492	0	0	0
T174	0	59	0	0
T175	35002	0	0	0
T176	0	9	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	992	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	16	0	0
T112	15357	19	0	0
T117	0	13	0	0
T122	2339	4	0	0
T125	0	16	0	0
T133	1094	0	0	0
T165	0	8	0	0
T170	0	4	0	0
T171	0	57	0	0
T172	0	4	0	0
T173	22492	0	0	0
T174	0	42	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	994	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	37	0	0
T112	15357	48	0	0
T117	20074	29	0	0
T125	0	23	0	0
T165	0	24	0	0
T169	0	4	0	0
T170	0	3	0	0
T171	0	83	0	0
T172	0	1	0	0
T173	22492	0	0	0
T174	0	62	0	0
T175	35002	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	930	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	7	0	0
T112	15357	33	0	0
T117	20074	17	0	0
T125	0	2	0	0
T165	0	14	0	0
T170	0	16	0	0
T171	0	85	0	0
T172	0	11	0	0
T173	22492	0	0	0
T174	0	62	0	0
T175	35002	0	0	0
T176	0	8	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	976	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	17	0	0
T112	15357	24	0	0
T117	0	24	0	0
T122	2339	9	0	0
T125	0	11	0	0
T133	1094	0	0	0
T165	0	36	0	0
T170	0	3	0	0
T171	0	73	0	0
T172	0	2	0	0
T173	22492	0	0	0
T174	0	82	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32783348	983	0	0
T6	21816	0	0	0
T51	9454	0	0	0
T98	10206	0	0	0
T99	3436	0	0	0
T100	2561	0	0	0
T105	14948	16	0	0
T112	15357	25	0	0
T117	0	34	0	0
T122	2339	10	0	0
T125	0	8	0	0
T133	1094	0	0	0
T165	0	18	0	0
T169	0	1	0	0
T170	0	12	0	0
T171	0	76	0	0
T172	0	4	0	0
T173	22492	0	0	0