Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4446764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

511783

1

T1

192

T2

3431

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4611688	1			T1	1590		T2	27586		T3	1
values[0x0]	172313	1			T1	66		T2	907		T3	1
values[0x1]	174546	1			T1	68		T2	889		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3013622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1944925

1

T1

665

T2

11710

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17004	1			T2	109		T4	1		T5	3
valid_sources[0x01]	65628	1			T2	90		T5	1		T15	38
valid_sources[0x02]	23434	1			T2	98		T4	2		T5	1
valid_sources[0x03]	22175	1			T2	144		T15	52		T16	3
valid_sources[0x04]	16374	1			T2	113		T4	2		T5	1
valid_sources[0x05]	16871	1			T2	113		T5	1		T15	34
valid_sources[0x06]	16045	1			T2	126		T4	26		T14	19
valid_sources[0x07]	14938	1			T2	89		T4	3		T15	48
valid_sources[0x08]	19446	1			T2	116		T4	3		T5	1
valid_sources[0x09]	420078	1			T2	85		T14	27		T15	42
valid_sources[0x0a]	14787	1			T2	86		T4	9		T5	1
valid_sources[0x0b]	19227	1			T2	101		T4	4		T15	44
valid_sources[0x0c]	20406	1			T2	109		T4	11		T15	42
valid_sources[0x0d]	17517	1			T2	81		T4	1		T14	7
valid_sources[0x0e]	15936	1			T2	129		T4	7		T5	1
valid_sources[0x0f]	17256	1			T2	93		T5	1		T15	22
valid_sources[0x10]	15216	1			T2	118		T4	17		T5	2
valid_sources[0x11]	15774	1			T2	117		T4	3		T15	28
valid_sources[0x12]	15087	1			T2	89		T4	3		T5	1
valid_sources[0x13]	15480	1			T2	120		T4	10		T15	42
valid_sources[0x14]	15629	1			T2	118		T4	10		T15	34
valid_sources[0x15]	43088	1			T2	110		T4	2		T15	31
valid_sources[0x16]	15457	1			T2	117		T4	2		T15	35
valid_sources[0x17]	16630	1			T2	90		T4	11		T15	44
valid_sources[0x18]	15009	1			T2	116		T4	1		T14	3
valid_sources[0x19]	15222	1			T2	107		T5	1		T15	42
valid_sources[0x1a]	16951	1			T2	117		T4	4		T5	2
valid_sources[0x1b]	15886	1			T2	120		T4	7		T15	40
valid_sources[0x1c]	15618	1			T2	107		T5	1		T14	3
valid_sources[0x1d]	21265	1			T2	138		T4	3		T5	1
valid_sources[0x1e]	14732	1			T2	75		T4	4		T5	1
valid_sources[0x1f]	16853	1			T2	71		T4	2		T14	4
valid_sources[0x20]	14934	1			T2	138		T4	1		T5	1
valid_sources[0x21]	37271	1			T2	118		T4	4		T14	1
valid_sources[0x22]	15379	1			T2	109		T4	2		T5	1
valid_sources[0x23]	14615	1			T2	109		T5	1		T14	7
valid_sources[0x24]	15023	1			T2	121		T4	3		T5	2
valid_sources[0x25]	16755	1			T2	95		T5	3		T14	4
valid_sources[0x26]	17701	1			T2	120		T4	1		T15	40
valid_sources[0x27]	36772	1			T2	113		T4	12		T14	6
valid_sources[0x28]	14938	1			T2	142		T4	3		T14	4
valid_sources[0x29]	15228	1			T2	124		T4	1		T14	7
valid_sources[0x2a]	15244	1			T2	139		T4	14		T5	2
valid_sources[0x2b]	15264	1			T2	115		T4	11		T5	1
valid_sources[0x2c]	16989	1			T2	118		T4	1		T5	1
valid_sources[0x2d]	15419	1			T2	124		T15	38		T16	4
valid_sources[0x2e]	23588	1			T2	109		T5	2		T15	47
valid_sources[0x2f]	18679	1			T2	122		T4	4		T15	35
valid_sources[0x30]	15913	1			T2	132		T4	5		T14	3
valid_sources[0x31]	22552	1			T2	101		T14	1		T15	54
valid_sources[0x32]	14756	1			T2	84		T5	2		T14	4
valid_sources[0x33]	19500	1			T2	102		T4	10		T5	1
valid_sources[0x34]	15025	1			T2	104		T15	64		T16	1
valid_sources[0x35]	17425	1			T2	95		T5	2		T15	46
valid_sources[0x36]	16120	1			T2	105		T4	4		T15	38
valid_sources[0x37]	16898	1			T2	101		T4	10		T5	1
valid_sources[0x38]	15392	1			T2	105		T4	2		T14	4
valid_sources[0x39]	17819	1			T2	86		T15	36		T16	2
valid_sources[0x3a]	17339	1			T2	126		T4	1		T15	40
valid_sources[0x3b]	17801	1			T2	120		T4	6		T5	5
valid_sources[0x3c]	16188	1			T2	87		T14	3		T15	33
valid_sources[0x3d]	16546	1			T2	103		T14	6		T15	30
valid_sources[0x3e]	15126	1			T2	135		T14	9		T15	47
valid_sources[0x3f]	16028	1			T2	105		T4	8		T5	2
valid_sources[0x40]	25784	1			T2	131		T4	8		T14	10
valid_sources[0x41]	16858	1			T2	105		T4	1		T15	20
valid_sources[0x42]	15491	1			T2	119		T4	3		T15	47
valid_sources[0x43]	18821	1			T2	102		T3	4		T4	8
valid_sources[0x44]	26952	1			T2	106		T4	13		T14	10
valid_sources[0x45]	17563	1			T2	148		T14	15		T15	31
valid_sources[0x46]	15975	1			T2	155		T5	1		T15	44
valid_sources[0x47]	23018	1			T2	142		T4	4		T15	65
valid_sources[0x48]	16111	1			T2	106		T4	15		T5	4
valid_sources[0x49]	21255	1			T2	155		T4	2		T14	1
valid_sources[0x4a]	15378	1			T2	91		T14	5		T15	42
valid_sources[0x4b]	16630	1			T2	102		T4	15		T5	1
valid_sources[0x4c]	14842	1			T2	144		T14	1		T15	35
valid_sources[0x4d]	15763	1			T2	132		T4	4		T15	48
valid_sources[0x4e]	15705	1			T2	121		T4	3		T15	39
valid_sources[0x4f]	17999	1			T2	131		T4	6		T15	27
valid_sources[0x50]	14841	1			T2	114		T5	1		T15	24
valid_sources[0x51]	15187	1			T2	77		T4	6		T5	2
valid_sources[0x52]	15424	1			T2	158		T4	5		T5	2
valid_sources[0x53]	15820	1			T2	116		T4	12		T14	4
valid_sources[0x54]	16400	1			T2	144		T15	56		T16	4
valid_sources[0x55]	18476	1			T2	166		T4	11		T14	3
valid_sources[0x56]	24481	1			T2	139		T4	2		T14	2
valid_sources[0x57]	16139	1			T2	122		T5	1		T15	47
valid_sources[0x58]	14959	1			T2	88		T5	2		T15	48
valid_sources[0x59]	15420	1			T2	163		T4	6		T5	1
valid_sources[0x5a]	17890	1			T2	106		T4	3		T5	1
valid_sources[0x5b]	16983	1			T2	119		T4	20		T5	1
valid_sources[0x5c]	15519	1			T2	122		T5	1		T14	6
valid_sources[0x5d]	16653	1			T2	108		T14	2		T15	49
valid_sources[0x5e]	15774	1			T2	109		T4	13		T5	1
valid_sources[0x5f]	18110	1			T2	113		T4	25		T14	3
valid_sources[0x60]	28532	1			T2	81		T4	1		T15	36
valid_sources[0x61]	15245	1			T2	82		T4	13		T5	1
valid_sources[0x62]	16378	1			T2	125		T4	1		T14	7
valid_sources[0x63]	15631	1			T2	129		T15	34		T16	2
valid_sources[0x64]	17804	1			T2	112		T4	2		T5	1
valid_sources[0x65]	20998	1			T2	126		T5	1		T15	33
valid_sources[0x66]	15448	1			T2	115		T14	12		T15	46
valid_sources[0x67]	14830	1			T2	106		T5	1		T15	55
valid_sources[0x68]	15332	1			T2	114		T4	4		T14	10
valid_sources[0x69]	16145	1			T2	100		T14	2		T15	32
valid_sources[0x6a]	15122	1			T2	135		T4	5		T5	2
valid_sources[0x6b]	16829	1			T2	105		T4	9		T14	24
valid_sources[0x6c]	16972	1			T2	93		T5	2		T15	26
valid_sources[0x6d]	15090	1			T2	133		T5	1		T15	39
valid_sources[0x6e]	15915	1			T2	137		T4	11		T15	28
valid_sources[0x6f]	15413	1			T2	67		T4	3		T14	1
valid_sources[0x70]	16866	1			T2	121		T4	2		T5	4
valid_sources[0x71]	15286	1			T2	121		T4	35		T5	1
valid_sources[0x72]	15391	1			T2	122		T4	16		T14	2
valid_sources[0x73]	21458	1			T2	137		T4	5		T5	2
valid_sources[0x74]	14886	1			T2	118		T4	2		T15	59
valid_sources[0x75]	15131	1			T2	117		T4	8		T15	31
valid_sources[0x76]	16131	1			T2	129		T5	3		T14	3
valid_sources[0x77]	19550	1			T2	135		T15	46		T16	3
valid_sources[0x78]	15658	1			T2	121		T4	2		T14	8
valid_sources[0x79]	15284	1			T2	95		T4	2		T14	1
valid_sources[0x7a]	14726	1			T2	108		T4	3		T5	2
valid_sources[0x7b]	21099	1			T2	113		T4	8		T14	6
valid_sources[0x7c]	15403	1			T2	87		T4	1		T14	2
valid_sources[0x7d]	36243	1			T2	114		T15	40		T16	5
valid_sources[0x7e]	16797	1			T2	115		T14	6		T15	37
valid_sources[0x7f]	15968	1			T2	124		T4	1		T5	1
valid_sources[0x80]	15808	1			T2	96		T4	8		T15	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

275054

1

T1

99

T2

2238

T3

1

values[0x0]

all_enables

biggest_size

124692

1

T1

48

T2

642

T3

1

values[0x1]

all_enables

biggest_size

112037

1

T1

45

T2

551

T4

10