Module Definition
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Module : prim_edn_req
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reseed_ctrl.u_edn_req 98.08 100.00 92.31 100.00 100.00


Module Instance : tb.dut.u_reseed_ctrl.u_edn_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.96 100.00 91.84 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.22 100.00 91.67 100.00 u_reseed_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_packer_fifo 97.78 100.00 93.33 100.00
u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN13911100.00
ALWAYS14333100.00
CONT_ASSIGN14911100.00
ALWAYS16300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
139 1 1
143 1 1
144 1 1
146 1 1
149 1 1
163 unreachable
164 unreachable
165 unreachable
166 unreachable
167 unreachable
168 unreachable
==> MISSING_ELSE

Cond Coverage for Module : prim_edn_req
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4 

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4 

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4 

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4 

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT2,T4,T5
11CoveredT1,T2,T4
Branch Coverage for Module : prim_edn_req
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 139 3 3 100.00
IF 143 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T4
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_edn_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataOutputDiffFromPrev_A 28250419 20264366 0 0
DataOutputValid_A 28250419 88674 0 0


DataOutputDiffFromPrev_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28250419 20264366 0 0
T2 305659 258760 0 0
T3 720 0 0 0
T4 3544 1942 0 0
T5 2274 1270 0 0
T14 9312 4543 0 0
T15 42772 41678 0 0
T16 5433 4772 0 0
T17 6655 5303 0 0
T18 6940 0 0 0
T22 0 1973 0 0
T34 7231 4834 0 0
T80 0 15364 0 0

DataOutputValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 28250419 88674 0 0
T1 6747 1 0 0
T2 305659 1399 0 0
T3 720 0 0 0
T4 3544 4 0 0
T5 2274 3 0 0
T14 9312 5 0 0
T15 42772 46 0 0
T16 5433 24 0 0
T17 6655 50 0 0
T18 6940 1 0 0
T34 0 44 0 0