Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29693444	13636	0	0
attest_sw_binding_0_rd_A	29693444	971	0	0
attest_sw_binding_1_rd_A	29693444	937	0	0
attest_sw_binding_2_rd_A	29693444	824	0	0
attest_sw_binding_3_rd_A	29693444	857	0	0
attest_sw_binding_4_rd_A	29693444	935	0	0
attest_sw_binding_5_rd_A	29693444	968	0	0
attest_sw_binding_6_rd_A	29693444	909	0	0
attest_sw_binding_7_rd_A	29693444	910	0	0
intr_enable_rd_A	29693444	1327	0	0
key_version_rd_A	29693444	974	0	0
max_creator_key_ver_regwen_rd_A	29693444	945	0	0
max_owner_int_key_ver_regwen_rd_A	29693444	864	0	0
max_owner_key_ver_regwen_rd_A	29693444	999	0	0
reseed_interval_regwen_rd_A	29693444	863	0	0
salt_0_rd_A	29693444	894	0	0
salt_1_rd_A	29693444	906	0	0
salt_2_rd_A	29693444	873	0	0
salt_3_rd_A	29693444	953	0	0
salt_4_rd_A	29693444	877	0	0
salt_5_rd_A	29693444	847	0	0
salt_6_rd_A	29693444	872	0	0
salt_7_rd_A	29693444	1053	0	0
sealing_sw_binding_0_rd_A	29693444	989	0	0
sealing_sw_binding_1_rd_A	29693444	835	0	0
sealing_sw_binding_2_rd_A	29693444	943	0	0
sealing_sw_binding_3_rd_A	29693444	943	0	0
sealing_sw_binding_4_rd_A	29693444	917	0	0
sealing_sw_binding_5_rd_A	29693444	898	0	0
sealing_sw_binding_6_rd_A	29693444	947	0	0
sealing_sw_binding_7_rd_A	29693444	992	0	0
sideload_clear_rd_A	29693444	868	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	13636	0	0
T25	213108	0	0	0
T26	25806	0	0	0
T44	101737	0	0	0
T45	2586	0	0	0
T75	25767	0	0	0
T76	6513	0	0	0
T77	6774	2	0	0
T78	15220	0	0	0
T99	22915	373	0	0
T110	0	806	0	0
T114	0	562	0	0
T121	0	262	0	0
T122	0	538	0	0
T124	0	304	0	0
T128	6861	0	0	0
T129	0	2	0	0
T130	0	7	0	0
T165	0	4	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	971	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	23	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	37	0	0
T116	24352	86	0	0
T118	0	42	0	0
T121	14835	17	0	0
T122	12972	0	0	0
T132	2174	0	0	0
T148	0	3	0	0
T166	0	14	0	0
T167	0	11	0	0
T168	0	5	0	0
T169	0	8	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	937	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	8	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	26	0	0
T116	24352	80	0	0
T118	0	56	0	0
T121	14835	31	0	0
T122	12972	0	0	0
T124	0	6	0	0
T126	0	7	0	0
T132	2174	0	0	0
T148	0	9	0	0
T166	0	5	0	0
T167	0	8	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	824	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	24	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	39	0	0
T116	24352	72	0	0
T118	0	40	0	0
T121	14835	1	0	0
T122	12972	0	0	0
T132	2174	0	0	0
T166	0	7	0	0
T167	0	10	0	0
T168	0	1	0	0
T169	0	13	0	0
T170	0	4	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	857	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	27	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	24	0	0
T116	24352	62	0	0
T118	0	54	0	0
T121	14835	3	0	0
T122	12972	0	0	0
T126	0	1	0	0
T132	2174	0	0	0
T148	0	10	0	0
T167	0	12	0	0
T168	0	1	0	0
T169	0	12	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	935	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	31	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	35	0	0
T116	24352	68	0	0
T118	0	43	0	0
T122	12972	0	0	0
T124	0	5	0	0
T132	2174	0	0	0
T135	1082	0	0	0
T148	0	2	0	0
T166	0	1	0	0
T167	0	16	0	0
T168	0	1	0	0
T169	0	6	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	968	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	32	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	57	0	0
T116	24352	77	0	0
T118	0	22	0	0
T121	14835	35	0	0
T122	12972	0	0	0
T132	2174	0	0	0
T148	0	28	0	0
T166	0	8	0	0
T167	0	15	0	0
T168	0	6	0	0
T169	0	10	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	909	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	30	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	36	0	0
T116	24352	98	0	0
T118	0	21	0	0
T121	14835	5	0	0
T122	12972	0	0	0
T124	0	6	0	0
T132	2174	0	0	0
T166	0	3	0	0
T167	0	7	0	0
T168	0	7	0	0
T169	0	20	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	910	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	13	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	41	0	0
T116	24352	71	0	0
T118	0	48	0	0
T121	14835	3	0	0
T122	12972	0	0	0
T124	0	9	0	0
T132	2174	0	0	0
T148	0	6	0	0
T166	0	2	0	0
T167	0	15	0	0
T168	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	1327	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	23	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	28	0	0
T116	24352	86	0	0
T118	0	40	0	0
T121	14835	10	0	0
T122	12972	0	0	0
T124	0	1	0	0
T132	2174	0	0	0
T166	0	2	0	0
T167	0	5	0	0
T171	0	10	0	0
T172	0	15	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	974	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	30	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	57	0	0
T116	24352	60	0	0
T118	0	46	0	0
T121	14835	21	0	0
T122	12972	0	0	0
T124	0	7	0	0
T132	2174	0	0	0
T148	0	4	0	0
T167	0	1	0	0
T168	0	10	0	0
T169	0	9	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	945	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	30	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	45	0	0
T116	24352	85	0	0
T118	0	34	0	0
T121	14835	9	0	0
T122	12972	0	0	0
T124	0	5	0	0
T126	0	7	0	0
T132	2174	0	0	0
T148	0	22	0	0
T167	0	10	0	0
T168	0	3	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	864	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	18	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	31	0	0
T116	24352	70	0	0
T118	0	55	0	0
T122	12972	0	0	0
T124	0	4	0	0
T126	0	8	0	0
T132	2174	0	0	0
T135	1082	0	0	0
T148	0	1	0	0
T167	0	13	0	0
T169	0	4	0	0
T170	0	4	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	999	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	21	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	26	0	0
T116	24352	80	0	0
T118	0	54	0	0
T121	14835	32	0	0
T122	12972	0	0	0
T124	0	13	0	0
T132	2174	0	0	0
T148	0	4	0	0
T166	0	7	0	0
T167	0	5	0	0
T168	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	863	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	17	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	38	0	0
T116	24352	82	0	0
T118	0	41	0	0
T121	14835	2	0	0
T122	12972	0	0	0
T124	0	3	0	0
T132	2174	0	0	0
T148	0	5	0	0
T167	0	8	0	0
T168	0	2	0	0
T169	0	6	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	894	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	12	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	33	0	0
T116	24352	71	0	0
T118	0	45	0	0
T121	14835	10	0	0
T122	12972	0	0	0
T132	2174	0	0	0
T148	0	5	0	0
T166	0	3	0	0
T167	0	8	0	0
T168	0	9	0	0
T169	0	3	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	906	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	30	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	41	0	0
T116	24352	101	0	0
T118	0	35	0	0
T121	14835	6	0	0
T122	12972	0	0	0
T126	0	16	0	0
T132	2174	0	0	0
T167	0	4	0	0
T169	0	6	0	0
T170	0	22	0	0
T173	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	873	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	34	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	22	0	0
T116	24352	71	0	0
T118	0	44	0	0
T121	14835	7	0	0
T122	12972	0	0	0
T124	0	3	0	0
T126	0	11	0	0
T132	2174	0	0	0
T148	0	2	0	0
T166	0	7	0	0
T167	0	12	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	953	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	30	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	24	0	0
T116	24352	80	0	0
T118	0	29	0	0
T121	14835	8	0	0
T122	12972	0	0	0
T126	0	11	0	0
T132	2174	0	0	0
T148	0	7	0	0
T166	0	7	0	0
T167	0	6	0	0
T168	0	1	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	877	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	15	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	29	0	0
T116	24352	54	0	0
T118	0	37	0	0
T121	14835	18	0	0
T122	12972	0	0	0
T124	0	15	0	0
T132	2174	0	0	0
T167	0	4	0	0
T168	0	5	0	0
T169	0	4	0	0
T170	0	9	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	847	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	25	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	35	0	0
T116	24352	84	0	0
T118	0	38	0	0
T121	14835	22	0	0
T122	12972	0	0	0
T126	0	6	0	0
T132	2174	0	0	0
T148	0	7	0	0
T167	0	9	0	0
T173	0	17	0	0
T174	0	10	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	872	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	20	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	38	0	0
T116	24352	66	0	0
T118	0	21	0	0
T121	14835	8	0	0
T122	12972	0	0	0
T126	0	2	0	0
T132	2174	0	0	0
T167	0	9	0	0
T168	0	9	0	0
T169	0	10	0	0
T170	0	1	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	1053	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	23	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	21	0	0
T116	24352	89	0	0
T118	0	60	0	0
T121	14835	9	0	0
T122	12972	0	0	0
T124	0	9	0	0
T126	0	3	0	0
T132	2174	0	0	0
T148	0	16	0	0
T167	0	9	0	0
T168	0	7	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	989	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	38	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	39	0	0
T116	24352	69	0	0
T118	0	23	0	0
T122	12972	0	0	0
T124	0	7	0	0
T126	0	3	0	0
T132	2174	0	0	0
T135	1082	0	0	0
T148	0	1	0	0
T166	0	8	0	0
T167	0	8	0	0
T169	0	1	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	835	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	15	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	34	0	0
T116	24352	72	0	0
T118	0	51	0	0
T122	12972	0	0	0
T124	0	2	0	0
T132	2174	0	0	0
T135	1082	0	0	0
T148	0	20	0	0
T166	0	4	0	0
T167	0	9	0	0
T168	0	4	0	0
T169	0	15	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	943	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	35	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	22	0	0
T116	24352	95	0	0
T118	0	36	0	0
T121	14835	15	0	0
T122	12972	0	0	0
T126	0	5	0	0
T132	2174	0	0	0
T148	0	3	0	0
T167	0	10	0	0
T168	0	9	0	0
T169	0	12	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	943	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	24	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	32	0	0
T116	24352	76	0	0
T118	0	26	0	0
T122	12972	0	0	0
T124	0	12	0	0
T126	0	9	0	0
T132	2174	0	0	0
T135	1082	0	0	0
T148	0	12	0	0
T166	0	1	0	0
T167	0	15	0	0
T168	0	3	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	917	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	19	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	62	0	0
T116	24352	69	0	0
T118	0	56	0	0
T121	14835	25	0	0
T122	12972	0	0	0
T124	0	6	0	0
T132	2174	0	0	0
T166	0	4	0	0
T167	0	4	0	0
T168	0	1	0	0
T169	0	1	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	898	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	24	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	42	0	0
T116	24352	66	0	0
T118	0	53	0	0
T121	14835	18	0	0
T122	12972	0	0	0
T124	0	14	0	0
T132	2174	0	0	0
T167	0	4	0	0
T168	0	5	0	0
T169	0	6	0	0
T173	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	947	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	25	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	41	0	0
T116	24352	56	0	0
T118	0	59	0	0
T121	14835	7	0	0
T122	12972	0	0	0
T124	0	1	0	0
T132	2174	0	0	0
T148	0	7	0	0
T166	0	2	0	0
T167	0	10	0	0
T168	0	5	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	992	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	23	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	28	0	0
T116	24352	93	0	0
T118	0	34	0	0
T121	14835	11	0	0
T122	12972	0	0	0
T124	0	4	0	0
T126	0	4	0	0
T132	2174	0	0	0
T148	0	3	0	0
T167	0	6	0	0
T168	0	9	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29693444	868	0	0
T26	25806	0	0	0
T40	4873	0	0	0
T77	6774	34	0	0
T78	15220	0	0	0
T79	24569	0	0	0
T115	23977	29	0	0
T116	24352	67	0	0
T118	0	30	0	0
T121	14835	9	0	0
T122	12972	0	0	0
T124	0	1	0	0
T126	0	3	0	0
T132	2174	0	0	0
T148	0	6	0	0
T167	0	17	0	0
T168	0	7	0	0