Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4361829	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

588866

1

T1

279

T2

272

T3

138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4571227	1			T1	10489		T2	945		T3	283
values[0x0]	187772	1			T1	62		T2	83		T3	54
values[0x1]	191696	1			T1	59		T2	70		T3	64

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2963536	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1987159

1

T1

3721

T2

497

T3

200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20035	1			T2	7		T15	1		T4	143
valid_sources[0x01]	17197	1			T2	4		T15	1		T4	136
valid_sources[0x02]	20132	1			T2	6		T15	3		T4	158
valid_sources[0x03]	20318	1			T2	2		T15	1		T4	114
valid_sources[0x04]	22729	1			T2	6		T3	1		T15	3
valid_sources[0x05]	15688	1			T2	7		T15	1		T4	214
valid_sources[0x06]	26424	1			T1	10610		T2	3		T15	7
valid_sources[0x07]	16128	1			T2	2		T15	1		T4	150
valid_sources[0x08]	21762	1			T2	1		T15	1		T4	132
valid_sources[0x09]	16067	1			T2	3		T3	7		T15	3
valid_sources[0x0a]	21781	1			T2	3		T15	7		T4	132
valid_sources[0x0b]	16905	1			T2	7		T4	186		T6	3
valid_sources[0x0c]	17273	1			T2	3		T15	15		T4	144
valid_sources[0x0d]	18412	1			T2	1		T15	3		T4	128
valid_sources[0x0e]	17528	1			T2	4		T3	2		T15	8
valid_sources[0x0f]	16027	1			T2	7		T4	141		T6	2
valid_sources[0x10]	27010	1			T2	5		T15	2		T4	163
valid_sources[0x11]	15249	1			T2	4		T15	4		T4	158
valid_sources[0x12]	16733	1			T2	4		T3	2		T15	2
valid_sources[0x13]	15664	1			T2	3		T15	4		T4	158
valid_sources[0x14]	15924	1			T2	4		T4	146		T6	3
valid_sources[0x15]	70807	1			T2	7		T4	131		T6	1
valid_sources[0x16]	49685	1			T2	3		T3	2		T4	178
valid_sources[0x17]	17208	1			T15	1		T4	128		T6	2
valid_sources[0x18]	16927	1			T2	9		T4	212		T6	2
valid_sources[0x19]	26098	1			T2	5		T15	3		T4	145
valid_sources[0x1a]	15823	1			T2	5		T4	192		T6	9
valid_sources[0x1b]	19895	1			T2	4		T15	2		T4	223
valid_sources[0x1c]	19653	1			T2	3		T15	2		T4	119
valid_sources[0x1d]	17565	1			T2	4		T15	3		T4	153
valid_sources[0x1e]	15324	1			T2	2		T15	4		T4	166
valid_sources[0x1f]	17002	1			T2	5		T15	2		T4	137
valid_sources[0x20]	22134	1			T2	7		T15	5		T4	153
valid_sources[0x21]	16097	1			T2	2		T15	6		T4	205
valid_sources[0x22]	16293	1			T2	6		T15	1		T4	201
valid_sources[0x23]	15467	1			T15	2		T4	151		T6	6
valid_sources[0x24]	19064	1			T2	3		T15	4		T4	115
valid_sources[0x25]	20432	1			T2	1		T15	4		T4	119
valid_sources[0x26]	15882	1			T2	4		T15	9		T4	158
valid_sources[0x27]	15430	1			T2	8		T3	3		T15	12
valid_sources[0x28]	18621	1			T2	4		T3	4		T15	7
valid_sources[0x29]	18202	1			T2	3		T3	6		T15	5
valid_sources[0x2a]	16083	1			T2	3		T4	205		T6	5
valid_sources[0x2b]	15909	1			T2	1		T15	8		T4	146
valid_sources[0x2c]	23375	1			T2	3		T15	2		T4	171
valid_sources[0x2d]	16444	1			T2	4		T15	5		T4	150
valid_sources[0x2e]	18286	1			T2	5		T15	4		T4	213
valid_sources[0x2f]	52049	1			T2	4		T15	8		T4	180
valid_sources[0x30]	17086	1			T2	1		T4	104		T6	3
valid_sources[0x31]	17283	1			T2	2		T3	34		T4	223
valid_sources[0x32]	16866	1			T2	7		T15	7		T4	160
valid_sources[0x33]	15667	1			T2	4		T15	2		T4	117
valid_sources[0x34]	22040	1			T2	10		T15	6		T4	128
valid_sources[0x35]	17660	1			T2	9		T3	31		T15	4
valid_sources[0x36]	19301	1			T2	1		T15	2		T4	149
valid_sources[0x37]	16032	1			T2	4		T15	7		T4	155
valid_sources[0x38]	16399	1			T2	7		T4	168		T6	2
valid_sources[0x39]	40135	1			T2	1		T15	5		T4	130
valid_sources[0x3a]	15928	1			T2	4		T4	156		T6	3
valid_sources[0x3b]	17489	1			T2	4		T15	3		T4	142
valid_sources[0x3c]	17726	1			T2	11		T15	2		T4	152
valid_sources[0x3d]	16875	1			T2	10		T15	2		T4	99
valid_sources[0x3e]	17537	1			T3	7		T15	3		T4	171
valid_sources[0x3f]	15571	1			T4	150		T6	5		T5	17
valid_sources[0x40]	17206	1			T2	7		T3	15		T15	2
valid_sources[0x41]	17315	1			T2	5		T4	177		T6	5
valid_sources[0x42]	18568	1			T2	7		T15	14		T4	177
valid_sources[0x43]	17714	1			T2	6		T15	5		T4	165
valid_sources[0x44]	16470	1			T2	4		T15	5		T4	215
valid_sources[0x45]	18638	1			T2	3		T15	6		T4	176
valid_sources[0x46]	16610	1			T2	6		T15	7		T4	177
valid_sources[0x47]	17766	1			T2	3		T15	2		T4	160
valid_sources[0x48]	15457	1			T2	6		T15	11		T4	175
valid_sources[0x49]	17934	1			T2	3		T15	1		T4	146
valid_sources[0x4a]	18183	1			T2	2		T15	5		T4	162
valid_sources[0x4b]	18479	1			T2	4		T15	6		T4	185
valid_sources[0x4c]	58590	1			T2	2		T4	191		T6	3
valid_sources[0x4d]	16309	1			T2	5		T3	20		T4	151
valid_sources[0x4e]	18638	1			T2	2		T15	2		T4	168
valid_sources[0x4f]	16530	1			T2	9		T4	174		T6	4
valid_sources[0x50]	15928	1			T2	3		T15	2		T4	156
valid_sources[0x51]	16400	1			T2	5		T4	208		T6	4
valid_sources[0x52]	15562	1			T2	2		T15	17		T4	141
valid_sources[0x53]	28595	1			T2	8		T15	1		T4	150
valid_sources[0x54]	16544	1			T2	4		T3	1		T4	154
valid_sources[0x55]	27504	1			T2	5		T3	18		T15	5
valid_sources[0x56]	16417	1			T2	6		T3	43		T15	5
valid_sources[0x57]	17653	1			T2	12		T15	4		T4	163
valid_sources[0x58]	17652	1			T2	4		T15	10		T4	131
valid_sources[0x59]	24972	1			T2	9		T3	4		T15	3
valid_sources[0x5a]	28720	1			T2	6		T15	2		T4	164
valid_sources[0x5b]	16079	1			T2	1		T15	4		T4	126
valid_sources[0x5c]	15783	1			T2	1		T15	5		T4	153
valid_sources[0x5d]	18466	1			T2	5		T15	3		T4	148
valid_sources[0x5e]	16642	1			T2	7		T3	15		T15	8
valid_sources[0x5f]	58648	1			T2	4		T3	9		T15	2
valid_sources[0x60]	15927	1			T2	2		T4	149		T6	4
valid_sources[0x61]	40196	1			T2	5		T3	3		T15	12
valid_sources[0x62]	16861	1			T3	4		T15	4		T4	170
valid_sources[0x63]	19983	1			T2	9		T15	1		T4	148
valid_sources[0x64]	20541	1			T2	3		T15	4		T4	196
valid_sources[0x65]	15680	1			T2	6		T15	8		T4	179
valid_sources[0x66]	15389	1			T2	5		T3	5		T15	5
valid_sources[0x67]	16469	1			T2	6		T4	154		T6	1
valid_sources[0x68]	16530	1			T2	7		T3	10		T4	131
valid_sources[0x69]	20943	1			T2	4		T3	2		T15	2
valid_sources[0x6a]	15174	1			T2	2		T4	134		T17	2
valid_sources[0x6b]	20896	1			T2	8		T15	2		T4	156
valid_sources[0x6c]	16262	1			T2	5		T15	1		T4	176
valid_sources[0x6d]	21655	1			T2	6		T15	7		T4	98
valid_sources[0x6e]	17641	1			T2	5		T3	1		T4	156
valid_sources[0x6f]	15918	1			T2	6		T15	3		T4	128
valid_sources[0x70]	17762	1			T2	6		T15	14		T4	188
valid_sources[0x71]	16187	1			T2	1		T15	5		T4	130
valid_sources[0x72]	18082	1			T2	5		T15	2		T4	169
valid_sources[0x73]	16083	1			T2	3		T15	3		T4	139
valid_sources[0x74]	21477	1			T2	7		T15	4		T4	168
valid_sources[0x75]	18779	1			T2	4		T15	11		T4	176
valid_sources[0x76]	16130	1			T2	2		T15	4		T4	133
valid_sources[0x77]	17749	1			T2	3		T15	1		T4	128
valid_sources[0x78]	44331	1			T2	1		T3	26		T15	1
valid_sources[0x79]	17416	1			T2	7		T15	2		T4	126
valid_sources[0x7a]	16644	1			T2	3		T3	2		T15	25
valid_sources[0x7b]	16111	1			T2	8		T15	1		T4	152
valid_sources[0x7c]	18320	1			T2	4		T15	5		T4	131
valid_sources[0x7d]	15230	1			T2	2		T15	6		T4	163
valid_sources[0x7e]	19184	1			T2	7		T4	164		T6	6
valid_sources[0x7f]	16668	1			T2	6		T15	10		T4	135
valid_sources[0x80]	15417	1			T2	1		T15	4		T4	163

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

328009

1

T1

235

T2

226

T3

83

values[0x0]

all_enables

biggest_size

136447

1

T1

30

T2

33

T3

27

values[0x1]

all_enables

biggest_size

124410

1

T1

14

T2

13

T3

28