Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	34354925	17565	0	0
attest_sw_binding_0_rd_A	34354925	730	0	0
attest_sw_binding_1_rd_A	34354925	903	0	0
attest_sw_binding_2_rd_A	34354925	783	0	0
attest_sw_binding_3_rd_A	34354925	788	0	0
attest_sw_binding_4_rd_A	34354925	840	0	0
attest_sw_binding_5_rd_A	34354925	787	0	0
attest_sw_binding_6_rd_A	34354925	848	0	0
attest_sw_binding_7_rd_A	34354925	920	0	0
intr_enable_rd_A	34354925	1484	0	0
key_version_rd_A	34354925	852	0	0
max_creator_key_ver_regwen_rd_A	34354925	770	0	0
max_owner_int_key_ver_regwen_rd_A	34354925	960	0	0
max_owner_key_ver_regwen_rd_A	34354925	785	0	0
reseed_interval_regwen_rd_A	34354925	815	0	0
salt_0_rd_A	34354925	779	0	0
salt_1_rd_A	34354925	1009	0	0
salt_2_rd_A	34354925	860	0	0
salt_3_rd_A	34354925	862	0	0
salt_4_rd_A	34354925	904	0	0
salt_5_rd_A	34354925	848	0	0
salt_6_rd_A	34354925	774	0	0
salt_7_rd_A	34354925	888	0	0
sealing_sw_binding_0_rd_A	34354925	810	0	0
sealing_sw_binding_1_rd_A	34354925	877	0	0
sealing_sw_binding_2_rd_A	34354925	850	0	0
sealing_sw_binding_3_rd_A	34354925	869	0	0
sealing_sw_binding_4_rd_A	34354925	786	0	0
sealing_sw_binding_5_rd_A	34354925	864	0	0
sealing_sw_binding_6_rd_A	34354925	804	0	0
sealing_sw_binding_7_rd_A	34354925	866	0	0
sideload_clear_rd_A	34354925	838	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	17565	0	0
T25	941014	0	0	0
T43	18797	801	0	0
T100	1735	0	0	0
T101	4821	114	0	0
T102	22126	74	0	0
T115	0	12	0	0
T116	0	462	0	0
T122	0	22	0	0
T123	0	29	0	0
T125	0	272	0	0
T126	0	253	0	0
T127	3135	0	0	0
T128	3780	0	0	0
T129	1901	0	0	0
T130	5575	0	0	0
T131	31832	0	0	0
T154	0	54	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	730	0	0
T44	12833	0	0	0
T102	22126	32	0	0
T115	8611	21	0	0
T118	12712	39	0	0
T119	0	19	0	0
T125	7469	0	0	0
T126	0	14	0	0
T138	6646	0	0	0
T176	3184	14	0	0
T177	0	6	0	0
T178	0	12	0	0
T179	0	6	0	0
T180	0	8	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	903	0	0
T44	12833	0	0	0
T102	22126	78	0	0
T115	8611	30	0	0
T118	12712	35	0	0
T119	0	45	0	0
T125	7469	4	0	0
T126	0	8	0	0
T138	6646	0	0	0
T176	3184	12	0	0
T177	0	7	0	0
T178	0	11	0	0
T180	0	5	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	783	0	0
T44	12833	0	0	0
T102	22126	40	0	0
T115	8611	26	0	0
T118	12712	49	0	0
T119	0	36	0	0
T125	7469	0	0	0
T126	0	3	0	0
T138	6646	0	0	0
T176	3184	17	0	0
T178	0	13	0	0
T180	0	4	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	19	0	0
T185	0	84	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	788	0	0
T44	12833	0	0	0
T102	22126	46	0	0
T115	8611	5	0	0
T118	12712	23	0	0
T119	0	50	0	0
T125	7469	0	0	0
T126	0	27	0	0
T138	6646	0	0	0
T176	3184	2	0	0
T177	0	6	0	0
T178	0	12	0	0
T179	0	7	0	0
T180	0	6	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	840	0	0
T44	12833	0	0	0
T102	22126	74	0	0
T115	8611	6	0	0
T118	12712	38	0	0
T119	0	26	0	0
T125	7469	4	0	0
T138	6646	0	0	0
T176	3184	8	0	0
T177	0	6	0	0
T179	0	5	0	0
T180	0	12	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	1	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	787	0	0
T44	12833	0	0	0
T102	22126	41	0	0
T115	8611	12	0	0
T118	12712	45	0	0
T119	0	33	0	0
T125	7469	2	0	0
T126	0	19	0	0
T138	6646	0	0	0
T176	3184	5	0	0
T177	0	5	0	0
T178	0	5	0	0
T180	0	2	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	848	0	0
T44	12833	0	0	0
T102	22126	67	0	0
T115	8611	23	0	0
T118	12712	58	0	0
T119	0	45	0	0
T125	7469	0	0	0
T126	0	4	0	0
T138	6646	0	0	0
T176	3184	18	0	0
T177	0	1	0	0
T178	0	8	0	0
T179	0	20	0	0
T180	0	10	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	920	0	0
T44	12833	0	0	0
T102	22126	66	0	0
T115	8611	33	0	0
T118	12712	60	0	0
T119	0	41	0	0
T125	7469	1	0	0
T126	0	21	0	0
T138	6646	0	0	0
T176	3184	5	0	0
T177	0	7	0	0
T178	0	8	0	0
T179	0	11	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	1484	0	0
T44	12833	0	0	0
T102	22126	41	0	0
T115	8611	32	0	0
T118	12712	43	0	0
T125	7469	0	0	0
T126	0	12	0	0
T138	6646	0	0	0
T139	0	14	0	0
T176	3184	12	0	0
T177	0	3	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T186	0	33	0	0
T187	0	17	0	0
T188	0	6	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	852	0	0
T44	12833	0	0	0
T102	22126	67	0	0
T115	8611	15	0	0
T118	12712	47	0	0
T119	0	46	0	0
T125	7469	0	0	0
T126	0	19	0	0
T138	6646	0	0	0
T176	3184	10	0	0
T177	0	5	0	0
T178	0	10	0	0
T180	0	15	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	5	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	770	0	0
T44	12833	0	0	0
T102	22126	72	0	0
T115	8611	12	0	0
T118	12712	36	0	0
T119	0	33	0	0
T125	7469	12	0	0
T126	0	25	0	0
T138	6646	0	0	0
T176	3184	10	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	7	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	960	0	0
T44	12833	0	0	0
T102	22126	54	0	0
T115	8611	16	0	0
T118	12712	38	0	0
T119	0	51	0	0
T125	7469	16	0	0
T126	0	27	0	0
T138	6646	0	0	0
T176	3184	14	0	0
T177	0	1	0	0
T178	0	16	0	0
T180	0	6	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	785	0	0
T44	12833	0	0	0
T102	22126	63	0	0
T115	8611	10	0	0
T118	12712	49	0	0
T119	0	25	0	0
T125	7469	0	0	0
T126	0	12	0	0
T138	6646	0	0	0
T176	3184	11	0	0
T177	0	5	0	0
T178	0	8	0	0
T179	0	5	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	16	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	815	0	0
T44	12833	0	0	0
T102	22126	58	0	0
T115	8611	17	0	0
T118	12712	32	0	0
T119	0	23	0	0
T125	7469	5	0	0
T126	0	16	0	0
T138	6646	0	0	0
T176	3184	11	0	0
T177	0	2	0	0
T178	0	10	0	0
T179	0	7	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	779	0	0
T44	12833	0	0	0
T102	22126	56	0	0
T115	8611	1	0	0
T118	12712	32	0	0
T119	0	30	0	0
T125	7469	0	0	0
T126	0	12	0	0
T138	6646	0	0	0
T176	3184	5	0	0
T178	0	1	0	0
T179	0	7	0	0
T180	0	9	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	14	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	1009	0	0
T44	12833	0	0	0
T102	22126	74	0	0
T115	8611	8	0	0
T118	12712	50	0	0
T119	0	64	0	0
T125	7469	0	0	0
T126	0	9	0	0
T138	6646	0	0	0
T176	3184	14	0	0
T179	0	11	0	0
T180	0	22	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	17	0	0
T185	0	72	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	860	0	0
T44	12833	0	0	0
T102	22126	63	0	0
T115	8611	8	0	0
T118	12712	36	0	0
T119	0	17	0	0
T125	7469	0	0	0
T126	0	24	0	0
T138	6646	0	0	0
T176	3184	11	0	0
T177	0	5	0	0
T178	0	1	0	0
T179	0	8	0	0
T180	0	10	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	862	0	0
T44	12833	0	0	0
T102	22126	56	0	0
T115	8611	26	0	0
T118	12712	36	0	0
T119	0	21	0	0
T125	7469	1	0	0
T126	0	6	0	0
T138	6646	0	0	0
T176	3184	20	0	0
T177	0	4	0	0
T178	0	7	0	0
T179	0	7	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	904	0	0
T44	12833	0	0	0
T102	22126	54	0	0
T115	8611	13	0	0
T118	12712	34	0	0
T119	0	47	0	0
T125	7469	4	0	0
T126	0	25	0	0
T138	6646	0	0	0
T176	3184	12	0	0
T177	0	8	0	0
T178	0	13	0	0
T180	0	31	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	848	0	0
T44	12833	0	0	0
T102	22126	62	0	0
T115	8611	23	0	0
T118	12712	33	0	0
T119	0	38	0	0
T125	7469	6	0	0
T126	0	6	0	0
T138	6646	0	0	0
T176	3184	2	0	0
T177	0	1	0	0
T178	0	6	0	0
T179	0	26	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	774	0	0
T44	12833	0	0	0
T102	22126	56	0	0
T115	8611	9	0	0
T118	12712	32	0	0
T119	0	29	0	0
T125	7469	0	0	0
T126	0	13	0	0
T138	6646	0	0	0
T176	3184	8	0	0
T177	0	8	0	0
T178	0	7	0	0
T179	0	9	0	0
T180	0	13	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	888	0	0
T44	12833	0	0	0
T102	22126	56	0	0
T115	8611	16	0	0
T118	12712	14	0	0
T119	0	33	0	0
T125	7469	2	0	0
T126	0	15	0	0
T138	6646	0	0	0
T176	3184	16	0	0
T177	0	4	0	0
T178	0	7	0	0
T179	0	7	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	810	0	0
T44	12833	0	0	0
T102	22126	49	0	0
T115	8611	27	0	0
T118	12712	23	0	0
T119	0	63	0	0
T125	7469	6	0	0
T126	0	14	0	0
T138	6646	0	0	0
T176	3184	2	0	0
T177	0	6	0	0
T178	0	14	0	0
T180	0	10	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	877	0	0
T44	12833	0	0	0
T102	22126	58	0	0
T115	8611	13	0	0
T118	12712	39	0	0
T119	0	23	0	0
T125	7469	0	0	0
T138	6646	0	0	0
T176	3184	9	0	0
T177	0	7	0	0
T178	0	13	0	0
T179	0	7	0	0
T180	0	4	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	8	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	850	0	0
T44	12833	0	0	0
T102	22126	61	0	0
T115	8611	29	0	0
T118	12712	23	0	0
T119	0	39	0	0
T125	7469	0	0	0
T126	0	37	0	0
T138	6646	0	0	0
T176	3184	4	0	0
T177	0	3	0	0
T178	0	11	0	0
T179	0	4	0	0
T180	0	2	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	869	0	0
T44	12833	0	0	0
T102	22126	57	0	0
T115	8611	7	0	0
T118	12712	52	0	0
T119	0	53	0	0
T125	7469	10	0	0
T126	0	23	0	0
T138	6646	0	0	0
T176	3184	12	0	0
T177	0	9	0	0
T179	0	7	0	0
T180	0	6	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	786	0	0
T44	12833	0	0	0
T102	22126	49	0	0
T115	8611	6	0	0
T118	12712	50	0	0
T119	0	32	0	0
T125	7469	0	0	0
T126	0	5	0	0
T138	6646	0	0	0
T176	3184	15	0	0
T177	0	6	0	0
T178	0	6	0	0
T180	0	8	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	23	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	864	0	0
T44	12833	0	0	0
T102	22126	54	0	0
T115	8611	9	0	0
T118	12712	28	0	0
T119	0	23	0	0
T125	7469	0	0	0
T126	0	5	0	0
T138	6646	0	0	0
T176	3184	6	0	0
T178	0	13	0	0
T180	0	8	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	13	0	0
T185	0	85	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	804	0	0
T44	12833	0	0	0
T102	22126	43	0	0
T115	8611	11	0	0
T118	12712	33	0	0
T119	0	40	0	0
T125	7469	1	0	0
T126	0	9	0	0
T138	6646	0	0	0
T176	3184	10	0	0
T177	0	2	0	0
T178	0	14	0	0
T180	0	8	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	866	0	0
T44	12833	0	0	0
T102	22126	61	0	0
T115	8611	27	0	0
T118	12712	48	0	0
T119	0	27	0	0
T125	7469	3	0	0
T126	0	12	0	0
T138	6646	0	0	0
T176	3184	12	0	0
T177	0	8	0	0
T178	0	8	0	0
T179	0	2	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34354925	838	0	0
T44	12833	0	0	0
T102	22126	50	0	0
T115	8611	17	0	0
T118	12712	32	0	0
T119	0	37	0	0
T125	7469	0	0	0
T138	6646	0	0	0
T176	3184	5	0	0
T178	0	19	0	0
T180	0	15	0	0
T181	16789	0	0	0
T182	7604	0	0	0
T183	2657	0	0	0
T184	0	13	0	0
T185	0	94	0	0
T189	0	15	0	0