Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5644795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

660713

1

T1

559

T2

145

T3

146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5903901	1			T1	864		T2	7675		T3	7689
values[0x0]	198869	1			T1	226		T2	31		T3	46
values[0x1]	202738	1			T1	209		T2	46		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3828292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2477216

1

T1

750

T2

2582

T3

2607

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20268	1			T3	24		T4	5		T13	34
valid_sources[0x01]	28467	1			T1	19		T3	13		T4	5
valid_sources[0x02]	20181	1			T3	33		T13	35		T15	2
valid_sources[0x03]	20156	1			T1	7		T3	22		T4	5
valid_sources[0x04]	21023	1			T1	6		T3	18		T13	22
valid_sources[0x05]	21595	1			T1	6		T3	20		T4	11
valid_sources[0x06]	21986	1			T1	1		T3	33		T4	3
valid_sources[0x07]	20576	1			T3	23		T4	3		T13	33
valid_sources[0x08]	19793	1			T3	11		T4	3		T13	22
valid_sources[0x09]	23750	1			T1	6		T3	3		T4	2
valid_sources[0x0a]	22064	1			T1	6		T3	24		T4	2
valid_sources[0x0b]	19940	1			T1	6		T3	34		T4	7
valid_sources[0x0c]	20905	1			T1	4		T3	18		T4	3
valid_sources[0x0d]	22016	1			T1	1		T3	49		T4	3
valid_sources[0x0e]	20312	1			T1	1		T3	35		T4	11
valid_sources[0x0f]	20900	1			T3	16		T4	6		T13	20
valid_sources[0x10]	20013	1			T3	28		T4	2		T13	33
valid_sources[0x11]	20836	1			T1	5		T3	50		T4	8
valid_sources[0x12]	20770	1			T1	5		T3	41		T4	1
valid_sources[0x13]	20324	1			T3	32		T4	11		T13	31
valid_sources[0x14]	29458	1			T1	1		T3	61		T4	4
valid_sources[0x15]	21314	1			T3	22		T4	4		T13	39
valid_sources[0x16]	21027	1			T1	1		T3	10		T4	1
valid_sources[0x17]	20530	1			T1	11		T3	9		T4	9
valid_sources[0x18]	19580	1			T1	6		T3	7		T4	4
valid_sources[0x19]	22400	1			T1	16		T3	48		T4	6
valid_sources[0x1a]	20207	1			T3	18		T4	3		T13	32
valid_sources[0x1b]	28115	1			T1	18		T3	23		T4	7
valid_sources[0x1c]	20559	1			T1	13		T3	19		T4	7
valid_sources[0x1d]	20714	1			T1	3		T3	10		T4	4
valid_sources[0x1e]	20111	1			T1	7		T3	39		T4	8
valid_sources[0x1f]	21175	1			T1	2		T3	20		T4	2
valid_sources[0x20]	20624	1			T3	31		T4	8		T13	16
valid_sources[0x21]	20231	1			T1	6		T3	64		T4	4
valid_sources[0x22]	20475	1			T1	2		T3	14		T4	5
valid_sources[0x23]	20678	1			T1	5		T3	54		T4	5
valid_sources[0x24]	21520	1			T1	1		T3	19		T4	1
valid_sources[0x25]	21323	1			T1	7		T3	65		T4	13
valid_sources[0x26]	20918	1			T1	9		T3	9		T4	6
valid_sources[0x27]	20873	1			T1	6		T3	29		T13	27
valid_sources[0x28]	23161	1			T1	9		T3	40		T4	2
valid_sources[0x29]	20329	1			T1	2		T3	27		T4	2
valid_sources[0x2a]	28431	1			T3	13		T4	8		T13	30
valid_sources[0x2b]	20438	1			T1	11		T3	29		T4	1
valid_sources[0x2c]	21928	1			T3	48		T4	2		T13	26
valid_sources[0x2d]	22688	1			T1	3		T3	12		T4	7
valid_sources[0x2e]	21963	1			T1	1		T3	39		T4	3
valid_sources[0x2f]	20779	1			T1	7		T3	19		T4	6
valid_sources[0x30]	20067	1			T1	3		T3	14		T4	4
valid_sources[0x31]	21203	1			T1	1		T3	17		T4	10
valid_sources[0x32]	25694	1			T1	4		T3	57		T4	4
valid_sources[0x33]	40655	1			T1	2		T3	15		T4	10
valid_sources[0x34]	21667	1			T1	3		T3	42		T13	28
valid_sources[0x35]	20283	1			T1	7		T3	50		T4	4
valid_sources[0x36]	20374	1			T1	1		T3	40		T4	6
valid_sources[0x37]	20615	1			T1	4		T3	16		T13	35
valid_sources[0x38]	23489	1			T1	2		T3	31		T4	4
valid_sources[0x39]	34135	1			T1	6		T3	30		T4	4
valid_sources[0x3a]	20082	1			T1	19		T3	1		T4	5
valid_sources[0x3b]	20497	1			T3	39		T4	10		T13	34
valid_sources[0x3c]	21347	1			T3	11		T4	9		T13	36
valid_sources[0x3d]	20786	1			T1	3		T3	49		T4	1
valid_sources[0x3e]	21220	1			T1	2		T3	32		T4	10
valid_sources[0x3f]	20035	1			T1	5		T3	29		T4	3
valid_sources[0x40]	32205	1			T1	11		T3	42		T13	19
valid_sources[0x41]	20201	1			T3	26		T4	2		T13	38
valid_sources[0x42]	20766	1			T1	1		T3	39		T4	1
valid_sources[0x43]	20302	1			T1	19		T3	11		T4	12
valid_sources[0x44]	21565	1			T1	2		T3	47		T4	1
valid_sources[0x45]	20463	1			T1	1		T3	26		T4	8
valid_sources[0x46]	25165	1			T1	4		T3	58		T4	6
valid_sources[0x47]	21957	1			T1	3		T3	20		T4	3
valid_sources[0x48]	47208	1			T1	2		T3	78		T4	2
valid_sources[0x49]	22092	1			T1	1		T3	24		T4	2
valid_sources[0x4a]	22402	1			T1	8		T3	21		T4	6
valid_sources[0x4b]	24642	1			T1	2		T3	28		T4	12
valid_sources[0x4c]	28745	1			T1	4		T3	40		T4	6
valid_sources[0x4d]	51329	1			T1	4		T3	6		T4	9
valid_sources[0x4e]	22314	1			T1	5		T3	21		T4	2
valid_sources[0x4f]	23047	1			T1	1		T3	33		T4	1
valid_sources[0x50]	22014	1			T1	3		T3	42		T4	2
valid_sources[0x51]	22406	1			T1	7		T3	9		T4	9
valid_sources[0x52]	20790	1			T1	7		T3	19		T4	4
valid_sources[0x53]	19679	1			T1	5		T3	45		T4	2
valid_sources[0x54]	19590	1			T1	3		T3	23		T4	4
valid_sources[0x55]	21532	1			T3	27		T4	8		T13	32
valid_sources[0x56]	90414	1			T1	2		T3	54		T4	7
valid_sources[0x57]	21028	1			T3	20		T4	4		T13	28
valid_sources[0x58]	20638	1			T1	2		T3	22		T4	8
valid_sources[0x59]	20329	1			T1	5		T3	4		T4	1
valid_sources[0x5a]	20181	1			T1	5		T3	43		T13	27
valid_sources[0x5b]	21131	1			T1	11		T3	40		T4	2
valid_sources[0x5c]	25387	1			T1	1		T3	77		T4	3
valid_sources[0x5d]	20267	1			T1	1		T3	54		T4	8
valid_sources[0x5e]	19911	1			T3	47		T4	3		T13	16
valid_sources[0x5f]	22042	1			T3	20		T4	1		T13	28
valid_sources[0x60]	21339	1			T1	13		T3	19		T4	3
valid_sources[0x61]	24225	1			T1	2		T3	33		T4	16
valid_sources[0x62]	24329	1			T1	4		T3	41		T4	4
valid_sources[0x63]	21844	1			T1	10		T3	59		T4	1
valid_sources[0x64]	32442	1			T1	13		T3	11		T4	2
valid_sources[0x65]	22180	1			T1	7		T3	29		T4	4
valid_sources[0x66]	21050	1			T1	12		T3	41		T4	1
valid_sources[0x67]	27089	1			T1	2		T3	77		T4	3
valid_sources[0x68]	20867	1			T1	3		T3	34		T4	7
valid_sources[0x69]	21188	1			T1	1		T3	41		T4	6
valid_sources[0x6a]	21971	1			T1	2		T3	11		T4	4
valid_sources[0x6b]	21347	1			T1	1		T3	26		T4	6
valid_sources[0x6c]	20036	1			T1	8		T3	35		T4	1
valid_sources[0x6d]	28093	1			T1	5		T3	45		T4	3
valid_sources[0x6e]	20907	1			T1	3		T3	39		T4	7
valid_sources[0x6f]	23861	1			T1	7		T3	18		T4	13
valid_sources[0x70]	19834	1			T1	2		T3	20		T4	2
valid_sources[0x71]	30500	1			T1	2		T3	11		T13	28
valid_sources[0x72]	20924	1			T3	14		T4	5		T13	33
valid_sources[0x73]	21045	1			T1	24		T3	26		T4	3
valid_sources[0x74]	23310	1			T1	8		T3	39		T4	2
valid_sources[0x75]	32338	1			T1	5		T3	28		T4	2
valid_sources[0x76]	28785	1			T1	7		T3	68		T4	1
valid_sources[0x77]	22510	1			T1	5		T3	26		T4	3
valid_sources[0x78]	22393	1			T1	6		T3	17		T4	4
valid_sources[0x79]	24710	1			T3	17		T4	3		T13	33
valid_sources[0x7a]	20815	1			T1	7		T3	52		T4	2
valid_sources[0x7b]	38787	1			T1	1		T3	17		T4	4
valid_sources[0x7c]	21050	1			T3	51		T4	4		T13	29
valid_sources[0x7d]	30485	1			T1	9		T3	6		T4	4
valid_sources[0x7e]	22901	1			T1	6		T3	37		T4	6
valid_sources[0x7f]	20970	1			T1	5		T3	18		T4	10
valid_sources[0x80]	20454	1			T1	6		T3	16		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

386634

1

T1

294

T2

120

T3

126

values[0x0]

all_enables

biggest_size

144120

1

T1

143

T2

12

T3

19

values[0x1]

all_enables

biggest_size

129959

1

T1

122

T2

13

T3

1