SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_keymgr_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.08 | 96.15 | 98.39 | 99.96 | 95.92 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 890 | 890 | 0 | 0 |
OutputsKnown_A | 35439713 | 35263756 | 0 | 0 |
gen_flops.OutputDelay_A | 35439713 | 35255899 | 0 | 2670 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 890 | 890 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 35439713 | 35263756 | 0 | 0 |
T1 | 15331 | 15267 | 0 | 0 |
T2 | 81666 | 81570 | 0 | 0 |
T3 | 73777 | 73681 | 0 | 0 |
T4 | 10324 | 10193 | 0 | 0 |
T13 | 73198 | 73067 | 0 | 0 |
T14 | 8383 | 8245 | 0 | 0 |
T15 | 2263 | 2166 | 0 | 0 |
T16 | 5716 | 5657 | 0 | 0 |
T17 | 821 | 769 | 0 | 0 |
T18 | 4311 | 4226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 35439713 | 35255899 | 0 | 2670 |
T1 | 15331 | 15264 | 0 | 3 |
T2 | 81666 | 81567 | 0 | 3 |
T3 | 73777 | 73678 | 0 | 3 |
T4 | 10324 | 10187 | 0 | 3 |
T13 | 73198 | 73061 | 0 | 3 |
T14 | 8383 | 8239 | 0 | 3 |
T15 | 2263 | 2163 | 0 | 3 |
T16 | 5716 | 5654 | 0 | 3 |
T17 | 821 | 766 | 0 | 3 |
T18 | 4311 | 4223 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |