Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	37290954	21075	0	0
attest_sw_binding_0_rd_A	37290954	1178	0	0
attest_sw_binding_1_rd_A	37290954	1017	0	0
attest_sw_binding_2_rd_A	37290954	1217	0	0
attest_sw_binding_3_rd_A	37290954	1185	0	0
attest_sw_binding_4_rd_A	37290954	1034	0	0
attest_sw_binding_5_rd_A	37290954	1122	0	0
attest_sw_binding_6_rd_A	37290954	1150	0	0
attest_sw_binding_7_rd_A	37290954	1182	0	0
intr_enable_rd_A	37290954	2070	0	0
key_version_rd_A	37290954	1194	0	0
max_creator_key_ver_regwen_rd_A	37290954	1149	0	0
max_owner_int_key_ver_regwen_rd_A	37290954	1093	0	0
max_owner_key_ver_regwen_rd_A	37290954	1273	0	0
reseed_interval_regwen_rd_A	37290954	1218	0	0
salt_0_rd_A	37290954	1280	0	0
salt_1_rd_A	37290954	1291	0	0
salt_2_rd_A	37290954	1142	0	0
salt_3_rd_A	37290954	1180	0	0
salt_4_rd_A	37290954	1140	0	0
salt_5_rd_A	37290954	1193	0	0
salt_6_rd_A	37290954	1158	0	0
salt_7_rd_A	37290954	1227	0	0
sealing_sw_binding_0_rd_A	37290954	1143	0	0
sealing_sw_binding_1_rd_A	37290954	1310	0	0
sealing_sw_binding_2_rd_A	37290954	1182	0	0
sealing_sw_binding_3_rd_A	37290954	1199	0	0
sealing_sw_binding_4_rd_A	37290954	1254	0	0
sealing_sw_binding_5_rd_A	37290954	1176	0	0
sealing_sw_binding_6_rd_A	37290954	1079	0	0
sealing_sw_binding_7_rd_A	37290954	1175	0	0
sideload_clear_rd_A	37290954	1118	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	21075	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T86	9237	0	0	0
T91	15700	21	0	0
T92	20685	1094	0	0
T106	0	296	0	0
T107	0	176	0	0
T119	0	33	0	0
T120	0	179	0	0
T121	0	44	0	0
T123	0	149	0	0
T124	0	314	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T128	0	1	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1178	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	33	0	0
T107	14555	23	0	0
T112	0	35	0	0
T124	0	12	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	8	0	0
T158	0	9	0	0
T159	0	7	0	0
T160	0	3	0	0
T161	0	9	0	0
T162	0	8	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1017	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	44	0	0
T107	14555	13	0	0
T112	0	29	0	0
T124	0	14	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	5	0	0
T158	0	16	0	0
T160	0	1	0	0
T161	0	11	0	0
T162	0	5	0	0
T163	0	3	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1217	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	78	0	0
T107	14555	4	0	0
T112	0	38	0	0
T124	0	9	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	8	0	0
T158	0	8	0	0
T159	0	4	0	0
T160	0	7	0	0
T161	0	4	0	0
T162	0	10	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1185	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	54	0	0
T107	14555	10	0	0
T112	0	40	0	0
T116	0	20	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	3	0	0
T158	0	22	0	0
T159	0	12	0	0
T160	0	5	0	0
T161	0	14	0	0
T162	0	15	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1034	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	40	0	0
T107	14555	12	0	0
T112	12149	25	0	0
T124	0	9	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	8	0	0
T159	0	4	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	6	0	0
T163	0	22	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1122	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	55	0	0
T107	14555	28	0	0
T112	0	22	0	0
T124	0	8	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	4	0	0
T158	0	6	0	0
T159	0	6	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	8	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1150	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	54	0	0
T107	14555	25	0	0
T112	0	40	0	0
T124	0	11	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	1	0	0
T158	0	5	0	0
T159	0	3	0	0
T160	0	4	0	0
T161	0	12	0	0
T162	0	3	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1182	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	54	0	0
T107	14555	11	0	0
T112	12149	37	0	0
T124	0	5	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	3	0	0
T159	0	13	0	0
T160	0	3	0	0
T161	0	12	0	0
T162	0	9	0	0
T163	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	2070	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T39	271979	24	0	0
T40	964739	0	0	0
T41	7370	0	0	0
T43	283279	12	0	0
T45	10435	0	0	0
T60	21838	0	0	0
T91	15700	82	0	0
T107	0	14	0	0
T112	0	35	0	0
T124	0	6	0	0
T125	7128	0	0	0
T136	0	11	0	0
T157	0	5	0	0
T158	0	1	0	0
T159	0	5	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1194	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	52	0	0
T107	14555	14	0	0
T112	0	52	0	0
T124	0	10	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	5	0	0
T158	0	8	0	0
T159	0	8	0	0
T160	0	8	0	0
T161	0	11	0	0
T162	0	9	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1149	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	39	0	0
T107	14555	7	0	0
T112	0	33	0	0
T124	0	16	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	15	0	0
T158	0	7	0	0
T159	0	8	0	0
T160	0	8	0	0
T161	0	18	0	0
T162	0	3	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1093	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	29	0	0
T107	14555	10	0	0
T112	0	45	0	0
T124	0	4	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	7	0	0
T158	0	8	0	0
T159	0	1	0	0
T161	0	7	0	0
T162	0	7	0	0
T163	0	19	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1273	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	79	0	0
T107	14555	23	0	0
T112	0	45	0	0
T124	0	11	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	5	0	0
T158	0	4	0	0
T159	0	2	0	0
T161	0	29	0	0
T162	0	9	0	0
T163	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1218	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	57	0	0
T107	14555	28	0	0
T112	0	40	0	0
T116	0	2	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	10	0	0
T158	0	13	0	0
T159	0	5	0	0
T161	0	21	0	0
T162	0	18	0	0
T163	0	34	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1280	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	74	0	0
T107	14555	12	0	0
T112	0	39	0	0
T124	0	12	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	8	0	0
T158	0	10	0	0
T159	0	8	0	0
T160	0	8	0	0
T161	0	18	0	0
T162	0	18	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1291	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	70	0	0
T107	14555	30	0	0
T112	0	42	0	0
T124	0	16	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	9	0	0
T158	0	6	0	0
T159	0	8	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	7	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1142	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	44	0	0
T107	14555	8	0	0
T112	12149	39	0	0
T124	0	8	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	7	0	0
T159	0	9	0	0
T160	0	2	0	0
T161	0	20	0	0
T162	0	4	0	0
T163	0	2	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1180	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	54	0	0
T107	14555	17	0	0
T112	0	42	0	0
T124	0	10	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	13	0	0
T158	0	1	0	0
T159	0	6	0	0
T161	0	15	0	0
T162	0	1	0	0
T163	0	9	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1140	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	29	0	0
T107	14555	10	0	0
T112	12149	57	0	0
T124	0	6	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	18	0	0
T159	0	1	0	0
T160	0	16	0	0
T161	0	7	0	0
T162	0	2	0	0
T163	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1193	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	70	0	0
T107	14555	7	0	0
T112	0	46	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	9	0	0
T158	0	7	0	0
T159	0	8	0	0
T160	0	4	0	0
T161	0	10	0	0
T162	0	10	0	0
T163	0	18	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1158	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	28	0	0
T107	14555	13	0	0
T112	0	36	0	0
T124	0	11	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	6	0	0
T158	0	10	0	0
T159	0	9	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	6	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1227	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	58	0	0
T107	14555	3	0	0
T112	12149	24	0	0
T116	0	23	0	0
T124	0	13	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	17	0	0
T159	0	11	0	0
T161	0	14	0	0
T162	0	14	0	0
T164	0	8	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1143	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	56	0	0
T107	14555	8	0	0
T112	0	69	0	0
T124	0	6	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	5	0	0
T158	0	14	0	0
T159	0	7	0	0
T160	0	2	0	0
T161	0	14	0	0
T162	0	3	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1310	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	65	0	0
T107	14555	17	0	0
T112	0	50	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	6	0	0
T158	0	10	0	0
T159	0	8	0	0
T160	0	4	0	0
T161	0	14	0	0
T162	0	22	0	0
T163	0	19	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1182	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	68	0	0
T107	14555	13	0	0
T112	0	30	0	0
T116	0	30	0	0
T124	0	15	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	1	0	0
T158	0	10	0	0
T159	0	6	0	0
T161	0	4	0	0
T163	0	5	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1199	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	39	0	0
T107	14555	20	0	0
T112	0	29	0	0
T124	0	8	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	3	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	10	0	0
T161	0	13	0	0
T162	0	10	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1254	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	40	0	0
T107	14555	8	0	0
T112	12149	46	0	0
T116	0	16	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T158	0	9	0	0
T159	0	2	0	0
T160	0	5	0	0
T161	0	7	0	0
T162	0	15	0	0
T163	0	29	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1176	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	72	0	0
T112	12149	44	0	0
T116	0	21	0	0
T124	0	5	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	4	0	0
T158	0	8	0	0
T159	0	3	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	27	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1079	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	54	0	0
T107	14555	11	0	0
T112	0	21	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	1	0	0
T158	0	12	0	0
T159	0	10	0	0
T160	0	2	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	11	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1175	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	61	0	0
T107	14555	6	0	0
T112	0	33	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	6	0	0
T158	0	14	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	10	0	0
T162	0	5	0	0
T163	0	2	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37290954	1118	0	0
T5	16902	0	0	0
T24	13177	0	0	0
T47	8880	0	0	0
T60	21838	0	0	0
T91	15700	64	0	0
T107	14555	10	0	0
T112	0	46	0	0
T116	0	10	0	0
T125	7128	0	0	0
T126	19054	0	0	0
T127	125007	0	0	0
T157	1843	3	0	0
T158	0	10	0	0
T159	0	10	0	0
T161	0	8	0	0
T162	0	10	0	0
T164	0	6	0	0