Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3994834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

565428

1

T1

1427

T2

390

T3

127

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4187600	1			T1	3270		T2	654		T3	5356
values[0x0]	185122	1			T1	482		T2	157		T3	37
values[0x1]	187540	1			T1	499		T2	138		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2718687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1841575

1

T1

2230

T2

515

T3

1861

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14643	1			T1	41		T3	18		T4	25
valid_sources[0x01]	40742	1			T1	58		T3	38		T4	28
valid_sources[0x02]	14299	1			T1	55		T3	31		T4	26
valid_sources[0x03]	20597	1			T1	41		T3	17		T4	29
valid_sources[0x04]	14328	1			T1	23		T3	42		T4	25
valid_sources[0x05]	14525	1			T1	19		T3	15		T4	16
valid_sources[0x06]	15080	1			T1	8		T3	21		T4	31
valid_sources[0x07]	15164	1			T1	5		T3	19		T4	20
valid_sources[0x08]	16217	1			T1	4		T3	13		T4	19
valid_sources[0x09]	17320	1			T1	9		T3	34		T4	22
valid_sources[0x0a]	19826	1			T3	10		T4	34		T13	3
valid_sources[0x0b]	14609	1			T3	33		T4	19		T13	2
valid_sources[0x0c]	26559	1			T1	10		T3	39		T4	38
valid_sources[0x0d]	14538	1			T1	6		T3	10		T4	28
valid_sources[0x0e]	17220	1			T1	15		T3	7		T4	24
valid_sources[0x0f]	15980	1			T1	32		T3	22		T4	17
valid_sources[0x10]	19392	1			T3	34		T4	23		T15	5
valid_sources[0x11]	16510	1			T1	47		T3	21		T4	26
valid_sources[0x12]	15080	1			T1	19		T3	32		T4	18
valid_sources[0x13]	17271	1			T1	62		T3	11		T4	34
valid_sources[0x14]	14232	1			T1	18		T3	25		T4	30
valid_sources[0x15]	22373	1			T1	19		T3	28		T4	31
valid_sources[0x16]	14882	1			T1	24		T3	19		T4	32
valid_sources[0x17]	20197	1			T1	26		T3	19		T4	32
valid_sources[0x18]	14361	1			T1	6		T3	36		T4	31
valid_sources[0x19]	14871	1			T1	16		T3	15		T4	22
valid_sources[0x1a]	14980	1			T1	18		T3	8		T4	26
valid_sources[0x1b]	37941	1			T1	11		T3	26		T4	33
valid_sources[0x1c]	14983	1			T1	18		T3	35		T4	22
valid_sources[0x1d]	15536	1			T1	41		T3	16		T4	29
valid_sources[0x1e]	14627	1			T1	3		T3	18		T4	33
valid_sources[0x1f]	14879	1			T3	21		T4	33		T15	5
valid_sources[0x20]	16993	1			T1	8		T3	10		T4	28
valid_sources[0x21]	14472	1			T1	10		T3	9		T4	30
valid_sources[0x22]	25395	1			T3	5		T4	16		T15	4
valid_sources[0x23]	14157	1			T1	4		T3	17		T4	34
valid_sources[0x24]	16230	1			T1	7		T3	9		T4	28
valid_sources[0x25]	15057	1			T3	38		T4	35		T13	4
valid_sources[0x26]	20845	1			T1	8		T3	15		T4	31
valid_sources[0x27]	15228	1			T1	12		T3	21		T4	19
valid_sources[0x28]	16080	1			T1	5		T3	22		T4	33
valid_sources[0x29]	15712	1			T1	8		T3	20		T4	24
valid_sources[0x2a]	17746	1			T1	6		T3	22		T4	25
valid_sources[0x2b]	15588	1			T1	55		T3	29		T4	27
valid_sources[0x2c]	16608	1			T1	42		T3	15		T4	32
valid_sources[0x2d]	15682	1			T1	13		T3	21		T4	33
valid_sources[0x2e]	14698	1			T1	38		T3	17		T4	23
valid_sources[0x2f]	16859	1			T3	19		T4	28		T14	137
valid_sources[0x30]	14770	1			T1	9		T3	15		T4	19
valid_sources[0x31]	14098	1			T1	15		T3	23		T4	33
valid_sources[0x32]	24525	1			T1	34		T3	9		T4	26
valid_sources[0x33]	59304	1			T3	7		T4	33		T13	20
valid_sources[0x34]	15693	1			T3	19		T4	27		T13	7
valid_sources[0x35]	14087	1			T3	19		T4	45		T15	4
valid_sources[0x36]	14847	1			T3	58		T4	34		T13	3
valid_sources[0x37]	15123	1			T1	7		T3	48		T4	36
valid_sources[0x38]	17431	1			T1	7		T3	10		T4	26
valid_sources[0x39]	15349	1			T1	9		T3	11		T4	21
valid_sources[0x3a]	17571	1			T1	33		T3	27		T4	26
valid_sources[0x3b]	20365	1			T1	3		T3	21		T4	32
valid_sources[0x3c]	15764	1			T1	17		T3	2		T4	31
valid_sources[0x3d]	42144	1			T1	1		T3	47		T4	22
valid_sources[0x3e]	14293	1			T3	22		T4	31		T15	7
valid_sources[0x3f]	19400	1			T1	29		T3	19		T4	31
valid_sources[0x40]	14933	1			T3	34		T4	27		T15	5
valid_sources[0x41]	16140	1			T1	12		T3	15		T4	31
valid_sources[0x42]	15020	1			T3	8		T4	36		T13	1
valid_sources[0x43]	15039	1			T1	10		T3	25		T4	30
valid_sources[0x44]	15383	1			T1	1		T3	22		T4	18
valid_sources[0x45]	15069	1			T1	24		T3	8		T4	34
valid_sources[0x46]	14462	1			T1	36		T3	26		T4	24
valid_sources[0x47]	15418	1			T1	4		T3	13		T4	23
valid_sources[0x48]	15601	1			T1	24		T3	19		T4	27
valid_sources[0x49]	15283	1			T1	7		T3	29		T4	28
valid_sources[0x4a]	26983	1			T1	1		T3	9		T4	36
valid_sources[0x4b]	14912	1			T1	5		T3	2		T4	37
valid_sources[0x4c]	15122	1			T1	15		T3	41		T4	21
valid_sources[0x4d]	15240	1			T1	21		T3	24		T4	26
valid_sources[0x4e]	32961	1			T1	5		T3	20		T4	27
valid_sources[0x4f]	14362	1			T1	12		T3	7		T4	18
valid_sources[0x50]	18718	1			T3	47		T4	32		T15	6
valid_sources[0x51]	26613	1			T1	3		T3	26		T4	36
valid_sources[0x52]	15803	1			T3	8		T4	28		T13	5
valid_sources[0x53]	14821	1			T1	13		T3	19		T4	33
valid_sources[0x54]	15749	1			T1	1		T3	17		T4	40
valid_sources[0x55]	17600	1			T1	27		T3	22		T4	33
valid_sources[0x56]	17973	1			T1	34		T3	10		T4	28
valid_sources[0x57]	19520	1			T1	11		T3	15		T4	26
valid_sources[0x58]	15213	1			T1	51		T3	21		T4	24
valid_sources[0x59]	14359	1			T1	32		T3	39		T4	22
valid_sources[0x5a]	19357	1			T1	1		T3	10		T4	37
valid_sources[0x5b]	16697	1			T1	41		T3	22		T4	29
valid_sources[0x5c]	15840	1			T1	2		T3	14		T4	32
valid_sources[0x5d]	16392	1			T1	18		T3	27		T4	27
valid_sources[0x5e]	15408	1			T3	10		T4	20		T13	4
valid_sources[0x5f]	45428	1			T1	9		T3	44		T4	32
valid_sources[0x60]	14793	1			T1	14		T3	36		T4	30
valid_sources[0x61]	14511	1			T1	37		T3	16		T4	34
valid_sources[0x62]	15054	1			T3	17		T4	28		T13	8
valid_sources[0x63]	14489	1			T3	31		T4	31		T13	6
valid_sources[0x64]	31602	1			T1	15		T3	24		T4	28
valid_sources[0x65]	14044	1			T1	21		T3	51		T4	25
valid_sources[0x66]	15427	1			T3	47		T4	20		T15	4
valid_sources[0x67]	14825	1			T3	10		T4	30		T14	42
valid_sources[0x68]	15755	1			T1	19		T3	14		T4	24
valid_sources[0x69]	14281	1			T1	97		T3	39		T4	31
valid_sources[0x6a]	15606	1			T1	11		T3	22		T4	26
valid_sources[0x6b]	14770	1			T1	9		T3	18		T4	32
valid_sources[0x6c]	16345	1			T1	24		T3	17		T4	29
valid_sources[0x6d]	14576	1			T3	8		T4	27		T13	9
valid_sources[0x6e]	14551	1			T1	8		T3	15		T4	18
valid_sources[0x6f]	14186	1			T1	22		T3	16		T4	31
valid_sources[0x70]	15461	1			T1	1		T3	11		T4	18
valid_sources[0x71]	16318	1			T1	14		T3	14		T4	43
valid_sources[0x72]	15585	1			T3	19		T4	28		T13	8
valid_sources[0x73]	14972	1			T1	17		T3	24		T4	23
valid_sources[0x74]	14129	1			T1	19		T3	27		T4	29
valid_sources[0x75]	13836	1			T1	43		T3	13		T4	28
valid_sources[0x76]	14513	1			T1	2		T3	18		T4	32
valid_sources[0x77]	15221	1			T1	51		T3	16		T4	23
valid_sources[0x78]	15545	1			T1	25		T3	2		T4	39
valid_sources[0x79]	16303	1			T3	44		T4	36		T13	2
valid_sources[0x7a]	14980	1			T1	10		T3	27		T4	25
valid_sources[0x7b]	15977	1			T1	5		T3	21		T4	21
valid_sources[0x7c]	16406	1			T1	16		T3	37		T4	24
valid_sources[0x7d]	17022	1			T1	7		T3	45		T4	34
valid_sources[0x7e]	16268	1			T3	8		T4	31		T15	7
valid_sources[0x7f]	16899	1			T1	4		T3	11		T4	27
valid_sources[0x80]	16034	1			T1	17		T3	14		T4	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

313920

1

T1

807

T2

207

T3

103

values[0x0]

all_enables

biggest_size

132510

1

T1

324

T2

112

T3

15

values[0x1]

all_enables

biggest_size

118998

1

T1

296

T2

71

T3

9