Unified Coverage Report :: Module :: keymgr_kmac_if

Module : keymgr_kmac_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.66	100.00	90.91		54.55	92.86	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_if	96.75	100.00	90.91		100.00	92.86	100.00

---

Module Instance : tb.dut.u_kmac_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.75	100.00	90.91		100.00	92.86	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	90.91	100.00	100.00	93.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		111	111	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	157	3	3	100.00
ALWAYS	165	3	3	100.00
ALWAYS	168	56	56	100.00
CONT_ASSIGN	283	1	1	100.00
ALWAYS	291	8	8	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
ALWAYS	320	9	9	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
ALWAYS	353	4	4	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	369	7	7	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	384	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
130	1	1
131	1	1
132	1	1
134	1	1
157	1	1
158	1	1
160	1	1
165	3	3
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
179	1	1
180	1	1
182	1	1
184	1	1
186	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			==> MISSING_ELSE
204	1	1
			MISSING_ELSE
209	1	1
210	1	1
213	1	1
214	1	1
217	1	1
218	1	1
			MISSING_ELSE
			MISSING_ELSE
225	1	1
226	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
237	1	1
238	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
252	1	1
253	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			==> MISSING_ELSE
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
283	1	1
291	1	1
293	1	1
294	1	1
295	1	1
296	1	1
298	1	1
300	1	1
302	1	1
			MISSING_ELSE
308	1	1
311	1	1
312	1	1
313	1	1
318	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
332	1	1
333	1	1
334	1	1
339	1	1
341	1	1
346	1	1
347	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
359	1	1
365	1	1
369	1	1
370	1	1
371	1	1
372	1	1
374	1	1
375	1	1
376	1	1
381	1	1
384	1	1

---

Cond Coverage for Module : keymgr_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T3

 LINE       204
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       204
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       217
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T21,T22

 LINE       296
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T21,T22

 LINE       298
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       298
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T21,T22,T23

 LINE       300
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T14

 LINE       300
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       302
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T14

 LINE       302
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       321
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T11,T12
0	1	0	Covered	T1,T4,T14
1	0	0	Covered	T8,T17,T24

 LINE       323
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       327
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T24,T25
1	1	Covered	T1,T2,T3

 LINE       339
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T26,T27
1	0	Covered	T1,T2,T3

 LINE       339
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T5,T17
1	0	Covered	T8,T5,T17

 LINE       359
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T5,T17

 LINE       359
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T28,T29
1	0	Covered	T17,T28,T29

 LINE       381
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T5,T24
1	0	Covered	T17,T18,T30

 LINE       384
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : keymgr_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	6	54.55
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	247	Covered	T1,T2,T3
StError	276	Covered	T5,T11,T12
StIdle	259	Covered	T1,T2,T3
StOpWait	238	Covered	T1,T2,T3
StTx	204	Covered	T1,T2,T3
StTxLast	204	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StClean->StError	276	Not Covered
StClean->StIdle	259	Covered	T1,T2,T3
StIdle->StError	276	Covered	T5,T11,T12
StIdle->StTx	204	Covered	T1,T2,T3
StIdle->StTxLast	204	Not Covered
StOpWait->StClean	247	Covered	T1,T2,T3
StOpWait->StError	276	Not Covered
StTx->StError	276	Not Covered
StTx->StTxLast	218	Covered	T1,T2,T3
StTxLast->StError	276	Not Covered
StTxLast->StOpWait	238	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	283	2	2	100.00
IF	157	2	2	100.00
IF	165	2	2	100.00
CASE	186	21	18	85.71
IF	275	2	2	100.00
IF	293	3	3	100.00
IF	321	5	5	100.00
IF	353	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	283	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	194	if (start)
-3-:	196	if (adv_en_i)
-4-:	198	if (id_en_i)
-5-:	200	if (gen_en_i)
-6-:	204	((rounds == 5'b0)) ? 
-7-:	213	if (kmac_data_i.ready)
-8-:	217	if ((cnt == 5'(1'b1)))
-9-:	228	if (adv_en_i)
-10-:	230	if (id_en_i)
-11-:	232	if (gen_en_i)
-12-:	238	(kmac_data_i.ready) ? 
-13-:	244	if (kmac_data_i.done)
-14-:	256	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T4
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T8,T17,T18
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T14
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	275	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if (clr_err)
-2-:	295	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	323	if ((valid && adv_en_i))
-3-:	325	if ((valid && id_en_i))
-4-:	327	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T4,T8
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if ((!rst_ni))
-2-:	355	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	891	891	0	0
GenRemBytes_A	891	891	0	0
IdRemBytes_A	891	891	0	0
LastStrb_A	24506809	17244000	0	0
u_state_regs_A	25123574	24956471	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506809	17244000	0	0
T1	40373	11225	0	0
T2	4544	582	0	0
T3	25728	23194	0	0
T4	70554	3694	0	0
T5	19093	1051	0	0
T8	2951	99	0	0
T13	7726	1120	0	0
T14	13483	8580	0	0
T15	4976	125	0	0
T16	10796	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25123574	24956471	0	0
T1	40373	40184	0	0
T2	4544	4462	0	0
T3	25728	25643	0	0
T4	70554	69619	0	0
T5	23698	16983	0	0
T8	6300	6166	0	0
T13	7726	7619	0	0
T14	13483	13403	0	0
T15	11096	10944	0	0
T16	10796	10731	0	0

Line Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		111	111	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	157	3	3	100.00
ALWAYS	165	3	3	100.00
ALWAYS	168	56	56	100.00
CONT_ASSIGN	283	1	1	100.00
ALWAYS	291	8	8	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
ALWAYS	320	9	9	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
ALWAYS	353	4	4	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	369	7	7	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	384	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
130	1	1
131	1	1
132	1	1
134	1	1
157	1	1
158	1	1
160	1	1
165	3	3
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
179	1	1
180	1	1
182	1	1
184	1	1
186	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			==> MISSING_ELSE
204	1	1
			MISSING_ELSE
209	1	1
210	1	1
213	1	1
214	1	1
217	1	1
218	1	1
			MISSING_ELSE
			MISSING_ELSE
225	1	1
226	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
			MISSING_ELSE
237	1	1
238	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
252	1	1
253	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			==> MISSING_ELSE
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
283	1	1
291	1	1
293	1	1
294	1	1
295	1	1
296	1	1
298	1	1
300	1	1
302	1	1
			MISSING_ELSE
308	1	1
311	1	1
312	1	1
313	1	1
318	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
			MISSING_ELSE
332	1	1
333	1	1
334	1	1
339	1	1
341	1	1
346	1	1
347	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
359	1	1
365	1	1
369	1	1
370	1	1
371	1	1
372	1	1
374	1	1
375	1	1
376	1	1
381	1	1
384	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T3

 LINE       204
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       204
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       217
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T1,T3,T14
1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({DecoyOutputCopies {entropy_i[0]}}))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       296
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T21,T22

 LINE       296
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T21,T22

 LINE       298
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       298
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T21,T22,T23

 LINE       300
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T14

 LINE       300
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       302
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T14

 LINE       302
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       321
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T11,T12
0	1	0	Covered	T1,T4,T14
1	0	0	Covered	T8,T17,T24

 LINE       323
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       327
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T24,T25
1	1	Covered	T1,T2,T3

 LINE       339
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T26,T27
1	0	Covered	T1,T2,T3

 LINE       339
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T5,T17
1	0	Covered	T8,T5,T17

 LINE       359
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T5,T17

 LINE       359
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T28,T29
1	0	Covered	T17,T28,T29

 LINE       381
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T5,T24
1	0	Covered	T17,T18,T30

 LINE       384
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	247	Covered	T1,T2,T3
StError	276	Covered	T5,T11,T12
StIdle	259	Covered	T1,T2,T3
StOpWait	238	Covered	T1,T2,T3
StTx	204	Covered	T1,T2,T3
StTxLast	204	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StClean->StError	276	Excluded
StClean->StIdle	259	Covered	T1,T2,T3
StIdle->StError	276	Covered	T5,T11,T12
StIdle->StTx	204	Covered	T1,T2,T3
StIdle->StTxLast	204	Excluded
StOpWait->StClean	247	Covered	T1,T2,T3
StOpWait->StError	276	Excluded
StTx->StError	276	Excluded
StTx->StTxLast	218	Covered	T1,T2,T3
StTxLast->StError	276	Excluded
StTxLast->StOpWait	238	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	283	2	2	100.00
IF	157	2	2	100.00
IF	165	2	2	100.00
CASE	186	21	18	85.71
IF	275	2	2	100.00
IF	293	3	3	100.00
IF	321	5	5	100.00
IF	353	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	283	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	194	if (start)
-3-:	196	if (adv_en_i)
-4-:	198	if (id_en_i)
-5-:	200	if (gen_en_i)
-6-:	204	((rounds == 5'b0)) ? 
-7-:	213	if (kmac_data_i.ready)
-8-:	217	if ((cnt == 5'(1'b1)))
-9-:	228	if (adv_en_i)
-10-:	230	if (id_en_i)
-11-:	232	if (gen_en_i)
-12-:	238	(kmac_data_i.ready) ? 
-13-:	244	if (kmac_data_i.done)
-14-:	256	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T13
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T4
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T8,T17,T18
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T14
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T11,T12

	LineNo.	Expression
-1-:	275	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if (clr_err)
-2-:	295	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	323	if ((valid && adv_en_i))
-3-:	325	if ((valid && id_en_i))
-4-:	327	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T4,T8
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if ((!rst_ni))
-2-:	355	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	891	891	0	0
GenRemBytes_A	891	891	0	0
IdRemBytes_A	891	891	0	0
LastStrb_A	24506809	17244000	0	0
u_state_regs_A	25123574	24956471	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	891	891	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24506809	17244000	0	0
T1	40373	11225	0	0
T2	4544	582	0	0
T3	25728	23194	0	0
T4	70554	3694	0	0
T5	19093	1051	0	0
T8	2951	99	0	0
T13	7726	1120	0	0
T14	13483	8580	0	0
T15	4976	125	0	0
T16	10796	531	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25123574	24956471	0	0
T1	40373	40184	0	0
T2	4544	4462	0	0
T3	25728	25643	0	0
T4	70554	69619	0	0
T5	23698	16983	0	0
T8	6300	6166	0	0
T13	7726	7619	0	0
T14	13483	13403	0	0
T15	11096	10944	0	0
T16	10796	10731	0	0