Module Definition
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Module Instance : tb.dut.u_sideload_ctrl.u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_sideload_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.08 96.15 98.39 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=3,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_sideload_ctrl.u_mubi_buf

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[0].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[1].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[2].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[3].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[4].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[5].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[6].u_mubi_buf

SCORELINE
100.00 100.00
tb.dut.gen_sw_assigns[7].u_mubi_buf

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 8019 8019 0 0
OutputsKnown_A 226112166 224608239 0 0
gen_no_flops.OutputDelay_A 226112166 224608239 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8019 8019 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T4 9 9 0 0
T5 9 9 0 0
T8 9 9 0 0
T13 9 9 0 0
T14 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 226112166 224608239 0 0
T1 363357 361656 0 0
T2 40896 40158 0 0
T3 231552 230787 0 0
T4 634986 626571 0 0
T5 213282 152847 0 0
T8 56700 55494 0 0
T13 69534 68571 0 0
T14 121347 120627 0 0
T15 99864 98496 0 0
T16 97164 96579 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 226112166 224608239 0 0
T1 363357 361656 0 0
T2 40896 40158 0 0
T3 231552 230787 0 0
T4 634986 626571 0 0
T5 213282 152847 0 0
T8 56700 55494 0 0
T13 69534 68571 0 0
T14 121347 120627 0 0
T15 99864 98496 0 0
T16 97164 96579 0 0

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 3 3


Assert Coverage for Instance : tb.dut.u_sideload_ctrl.u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[0].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[1].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[2].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[3].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[4].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[5].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[6].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

Line Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 2 2


Assert Coverage for Instance : tb.dut.gen_sw_assigns[7].u_mubi_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 891 891 0 0
OutputsKnown_A 25123574 24956471 0 0
gen_no_flops.OutputDelay_A 25123574 24956471 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 891 891 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 25123574 24956471 0 0
T1 40373 40184 0 0
T2 4544 4462 0 0
T3 25728 25643 0 0
T4 70554 69619 0 0
T5 23698 16983 0 0
T8 6300 6166 0 0
T13 7726 7619 0 0
T14 13483 13403 0 0
T15 11096 10944 0 0
T16 10796 10731 0 0