Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
77.78 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 1 13 92.86
Crosses 49 13 36 73.47


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 1 4 80.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 12 23 65.71 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 1 4 80.00


Automatically Generated Bins for op_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[OpDisable] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 85 1 T13 1 T18 1 T34 1
auto[OpGenId] 22 1 T54 1 T192 1 T193 1
auto[OpGenSwOut] 33 1 T98 1 T57 1 T193 1
auto[OpGenHwOut] 48 1 T13 2 T5 1 T7 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1913 1 T13 1 T88 3 T6 90
auto[StInit] 188 1 T13 2 T16 1 T18 1
auto[StCreatorRootKey] 55 1 T50 1 T37 1 T51 1
auto[StOwnerIntKey] 46 1 T13 2 T34 1 T5 1
auto[StOwnerKey] 27 1 T54 1 T60 1 T62 1
auto[StDisabled] 393 1 T3 1 T18 7 T5 2
auto[StInvalid] 44 1 T4 1 T38 1 T39 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3549 1 T1 1 T2 1 T3 2
auto[1] 188 1 T13 3 T18 1 T34 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1900 1 T13 1 T88 3 T6 90
auto[StReset] auto[1] 13 1 T47 1 T130 1 T194 1
auto[StInit] auto[0] 73 1 T13 1 T16 1 T127 1
auto[StInit] auto[1] 115 1 T13 1 T18 1 T5 1
auto[StCreatorRootKey] auto[0] 33 1 T50 1 T37 1 T51 1
auto[StCreatorRootKey] auto[1] 22 1 T24 1 T52 1 T53 1
auto[StOwnerIntKey] auto[0] 30 1 T5 1 T36 1 T55 1
auto[StOwnerIntKey] auto[1] 16 1 T13 2 T34 1 T57 1
auto[StOwnerKey] auto[0] 16 1 T60 1 T62 1 T63 1
auto[StOwnerKey] auto[1] 11 1 T54 1 T195 1 T196 1
auto[StDisabled] auto[0] 382 1 T3 1 T18 7 T5 1
auto[StDisabled] auto[1] 11 1 T5 1 T57 2 T197 1
auto[StInvalid] auto[0] 44 1 T4 1 T38 1 T39 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 12 23 65.71 12


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenSwOut]] 0 1 1
[auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]] [auto[OpDisable]] -- -- 5


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 11 1 T47 1 T130 1 T198 1
auto[StReset] auto[OpGenId] 1 1 T199 1 - - - -
auto[StReset] auto[OpGenHwOut] 1 1 T194 1 - - - -
auto[StInit] auto[OpAdvance] 50 1 T18 1 T5 1 T96 1
auto[StInit] auto[OpGenId] 8 1 T192 1 T193 1 T200 1
auto[StInit] auto[OpGenSwOut] 21 1 T98 1 T193 1 T201 2
auto[StInit] auto[OpGenHwOut] 36 1 T13 1 T7 1 T45 1
auto[StCreatorRootKey] auto[OpAdvance] 9 1 T24 1 T52 1 T195 1
auto[StCreatorRootKey] auto[OpGenId] 4 1 T26 1 T202 1 T203 1
auto[StCreatorRootKey] auto[OpGenSwOut] 3 1 T204 1 T72 1 T205 1
auto[StCreatorRootKey] auto[OpGenHwOut] 6 1 T53 1 T134 1 T206 1
auto[StOwnerIntKey] auto[OpAdvance] 4 1 T13 1 T34 1 T57 1
auto[StOwnerIntKey] auto[OpGenId] 5 1 T204 1 T207 1 T208 1
auto[StOwnerIntKey] auto[OpGenSwOut] 5 1 T27 1 T209 1 T210 1
auto[StOwnerIntKey] auto[OpGenHwOut] 2 1 T13 1 T211 1 - -
auto[StOwnerKey] auto[OpAdvance] 6 1 T195 1 T196 1 T212 1
auto[StOwnerKey] auto[OpGenId] 3 1 T54 1 T213 1 T200 1
auto[StOwnerKey] auto[OpGenSwOut] 1 1 T214 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T215 1 - - - -
auto[StDisabled] auto[OpAdvance] 5 1 T57 1 T197 1 T216 1
auto[StDisabled] auto[OpGenId] 1 1 T217 1 - - - -
auto[StDisabled] auto[OpGenSwOut] 3 1 T57 1 T218 1 T219 1
auto[StDisabled] auto[OpGenHwOut] 2 1 T5 1 T220 1 - -