Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11406

1

T1

4

T2

13

T3

4

auto[Attestation]

7994

1

T1

4

T2

9

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2823	1			T2	4		T3	1		T4	3
auto[Aes]	3565	1			T2	3		T3	2		T4	4
auto[Kmac]	3446	1			T1	8		T2	2		T3	1
auto[Otbn]	3458	1			T2	3		T3	1		T4	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7677	1			T1	8		T2	8		T3	5
auto[OpGenId]	6108	1			T2	10		T3	3		T4	6
auto[OpGenSwOut]	6078	1			T2	6		T3	1		T4	10
auto[OpGenHwOut]	7214	1			T1	8		T2	6		T3	4
auto[OpDisable]	141	1			T18	4		T43	1		T46	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10151

1

T1

8

T2

10

T3

7

auto[OpDoneFail]

17067

1

T1

8

T2

20

T3

6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6520	1			T1	1		T2	3		T3	4
auto[StInit]	4150	1			T1	2		T2	3		T3	4
auto[StCreatorRootKey]	3031	1			T1	2		T2	5		T3	1
auto[StOwnerIntKey]	2633	1			T1	2		T2	2		T3	3
auto[StOwnerKey]	2347	1			T1	2		T2	3		T3	1
auto[StDisabled]	7553	1			T1	7		T2	14		T14	7
auto[StInvalid]	984	1			T4	23		T38	22		T39	18

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	324	1			T3	1		T14	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T172	1		T57	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T17	2		T77	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T58	1		T36	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T77	1		T54	2		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T2	1		T18	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	46	1			T4	2		T38	3		T86	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	350	1			T13	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	127	1			T2	1		T34	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T18	2		T172	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T18	1		T44	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T57	1		T173	1		T174	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	188	1			T18	1		T77	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	26	1			T4	1		T39	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	340	1			T14	2		T18	1		T77	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T4	1		T13	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	72	1			T14	1		T77	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T175	1		T176	1		T177	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	50	1			T14	1		T115	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T18	2		T77	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T4	1		T38	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	334	1			T2	1		T13	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T18	1		T5	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T18	1		T115	1		T177	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T14	1		T175	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	66	1			T5	1		T115	1		T178	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	170	1			T2	1		T18	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	26	1			T86	1		T179	1		T180	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T5	3		T54	3		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	127	1			T18	1		T50	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T13	1		T177	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T13	1		T18	1		T178	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	68	1			T2	1		T128	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	240	1			T18	5		T77	1		T175	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	44	1			T39	1		T22	1		T179	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	73	1			T18	1		T5	3		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T18	1		T37	2		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	73	1			T18	1		T44	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T5	2		T19	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T18	1		T54	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	202	1			T18	2		T175	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T4	1		T38	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T18	3		T5	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T18	1		T77	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T18	1		T50	1		T19	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T91	1		T93	1		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	43	1			T175	1		T177	1		T173	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	191	1			T14	1		T5	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	26	1			T4	1		T39	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T18	1		T5	2		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T18	2		T5	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T17	1		T18	2		T34	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T19	1		T54	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T77	1		T172	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	209	1			T2	1		T18	2		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	45	1			T4	3		T38	3		T39	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T13	2		T18	3		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T4	1		T13	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T17	1		T18	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T178	1		T172	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T2	1		T81	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	175	1			T18	3		T44	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	24	1			T86	2		T179	3		T185	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	520	1			T3	1		T13	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	130	1			T2	1		T76	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T17	2		T35	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T172	1		T181	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T18	1		T35	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	260	1			T2	1		T18	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	34	1			T4	1		T38	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	436	1			T2	1		T13	1		T187	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T1	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T43	1		T184	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T1	1		T3	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T58	1		T178	2		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	288	1			T1	2		T18	2		T175	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T38	1		T179	2		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	437	1			T13	1		T18	1		T175	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T189	1		T58	1		T177	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	124	1			T17	1		T43	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T18	1		T175	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T189	1		T93	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	273	1			T18	2		T44	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T39	2		T86	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T18	1		T5	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T57	3		T23	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T2	1		T34	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T18	1		T5	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T58	1		T54	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T18	3		T77	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	24	1			T39	1		T86	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	73	1			T18	1		T5	4		T54	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	114	1			T3	1		T13	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T17	1		T18	2		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	91	1			T18	1		T35	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	89	1			T76	1		T178	1		T172	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	307	1			T18	2		T35	3		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	34	1			T4	1		T179	2		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	83	1			T18	3		T5	2		T54	7
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	112	1			T18	1		T43	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T1	1		T17	1		T184	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T2	1		T106	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	84	1			T1	1		T18	1		T178	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	267	1			T1	2		T115	2		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T4	1		T38	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T18	3		T57	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	144	1			T4	1		T5	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T17	1		T46	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T3	1		T5	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T18	1		T93	1		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	249	1			T18	1		T175	1		T115	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	27	1			T4	1		T39	1		T86	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T17	2		T77	2		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	704	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	190	1			T18	2		T44	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	707	1			T2	1		T4	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	171	1			T14	2		T77	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	734	1			T4	2		T13	1		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T14	1		T18	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	653	1			T2	2		T13	1		T18	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T2	1		T13	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	492	1			T18	6		T77	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	198	1			T18	2		T44	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	432	1			T4	1		T18	4		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	157	1			T18	1		T50	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	440	1			T4	1		T14	1		T18	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	221	1			T17	1		T18	2		T34	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	437	1			T2	1		T4	3		T18	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	158	1			T17	1		T18	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	587	1			T2	1		T4	1		T13	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T17	2		T18	1		T35	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	959	1			T2	2		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T1	1		T3	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	888	1			T1	3		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	294	1			T17	1		T18	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	887	1			T13	1		T18	3		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	169	1			T2	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	364	1			T18	4		T77	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	264	1			T17	1		T18	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	549	1			T3	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T1	2		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	505	1			T1	2		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T3	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	504	1			T4	2		T18	4		T5	1