Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31218

1

T1

20

T2

33

T3

16

auto[1]

272

1

T77

17

T106

2

T115

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31231	1			T1	20		T2	33		T3	16
auto[134217728:268435455]	16	1			T115	1		T91	1		T174	1
auto[268435456:402653183]	11	1			T77	1		T252	1		T272	1
auto[402653184:536870911]	9	1			T77	1		T115	1		T349	1
auto[536870912:671088639]	8	1			T106	1		T115	1		T320	1
auto[671088640:805306367]	7	1			T174	1		T282	1		T320	1
auto[805306368:939524095]	6	1			T174	2		T282	1		T389	1
auto[939524096:1073741823]	6	1			T77	2		T174	1		T329	1
auto[1073741824:1207959551]	12	1			T91	1		T280	1		T282	1
auto[1207959552:1342177279]	6	1			T174	1		T252	1		T344	1
auto[1342177280:1476395007]	5	1			T115	1		T252	1		T390	1
auto[1476395008:1610612735]	9	1			T174	2		T320	1		T389	1
auto[1610612736:1744830463]	10	1			T77	1		T224	1		T282	2
auto[1744830464:1879048191]	9	1			T77	1		T281	1		T349	1
auto[1879048192:2013265919]	7	1			T391	1		T285	1		T392	1
auto[2013265920:2147483647]	6	1			T174	1		T280	1		T306	1
auto[2147483648:2281701375]	5	1			T77	1		T282	1		T320	1
auto[2281701376:2415919103]	9	1			T115	2		T224	1		T320	1
auto[2415919104:2550136831]	12	1			T174	1		T281	1		T359	1
auto[2550136832:2684354559]	6	1			T224	1		T323	1		T223	1
auto[2684354560:2818572287]	10	1			T77	1		T115	1		T183	1
auto[2818572288:2952790015]	9	1			T77	1		T106	1		T115	2
auto[2952790016:3087007743]	7	1			T77	1		T91	1		T183	1
auto[3087007744:3221225471]	6	1			T174	1		T359	1		T320	1
auto[3221225472:3355443199]	13	1			T174	1		T252	1		T282	1
auto[3355443200:3489660927]	6	1			T77	1		T174	1		T320	1
auto[3489660928:3623878655]	10	1			T174	1		T280	1		T272	2
auto[3623878656:3758096383]	14	1			T183	1		T252	1		T281	1
auto[3758096384:3892314111]	8	1			T77	3		T91	1		T389	1
auto[3892314112:4026531839]	8	1			T77	1		T224	1		T282	1
auto[4026531840:4160749567]	4	1			T224	1		T393	1		T390	1
auto[4160749568:4294967295]	5	1			T77	1		T390	1		T394	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31218	1			T1	20		T2	33		T3	16
auto[0:134217727]	auto[1]	13	1			T77	1		T252	1		T280	2
auto[134217728:268435455]	auto[1]	16	1			T115	1		T91	1		T174	1
auto[268435456:402653183]	auto[1]	11	1			T77	1		T252	1		T272	1
auto[402653184:536870911]	auto[1]	9	1			T77	1		T115	1		T349	1
auto[536870912:671088639]	auto[1]	8	1			T106	1		T115	1		T320	1
auto[671088640:805306367]	auto[1]	7	1			T174	1		T282	1		T320	1
auto[805306368:939524095]	auto[1]	6	1			T174	2		T282	1		T389	1
auto[939524096:1073741823]	auto[1]	6	1			T77	2		T174	1		T329	1
auto[1073741824:1207959551]	auto[1]	12	1			T91	1		T280	1		T282	1
auto[1207959552:1342177279]	auto[1]	6	1			T174	1		T252	1		T344	1
auto[1342177280:1476395007]	auto[1]	5	1			T115	1		T252	1		T390	1
auto[1476395008:1610612735]	auto[1]	9	1			T174	2		T320	1		T389	1
auto[1610612736:1744830463]	auto[1]	10	1			T77	1		T224	1		T282	2
auto[1744830464:1879048191]	auto[1]	9	1			T77	1		T281	1		T349	1
auto[1879048192:2013265919]	auto[1]	7	1			T391	1		T285	1		T392	1
auto[2013265920:2147483647]	auto[1]	6	1			T174	1		T280	1		T306	1
auto[2147483648:2281701375]	auto[1]	5	1			T77	1		T282	1		T320	1
auto[2281701376:2415919103]	auto[1]	9	1			T115	2		T224	1		T320	1
auto[2415919104:2550136831]	auto[1]	12	1			T174	1		T281	1		T359	1
auto[2550136832:2684354559]	auto[1]	6	1			T224	1		T323	1		T223	1
auto[2684354560:2818572287]	auto[1]	10	1			T77	1		T115	1		T183	1
auto[2818572288:2952790015]	auto[1]	9	1			T77	1		T106	1		T115	2
auto[2952790016:3087007743]	auto[1]	7	1			T77	1		T91	1		T183	1
auto[3087007744:3221225471]	auto[1]	6	1			T174	1		T359	1		T320	1
auto[3221225472:3355443199]	auto[1]	13	1			T174	1		T252	1		T282	1
auto[3355443200:3489660927]	auto[1]	6	1			T77	1		T174	1		T320	1
auto[3489660928:3623878655]	auto[1]	10	1			T174	1		T280	1		T272	2
auto[3623878656:3758096383]	auto[1]	14	1			T183	1		T252	1		T281	1
auto[3758096384:3892314111]	auto[1]	8	1			T77	3		T91	1		T389	1
auto[3892314112:4026531839]	auto[1]	8	1			T77	1		T224	1		T282	1
auto[4026531840:4160749567]	auto[1]	4	1			T224	1		T393	1		T390	1
auto[4160749568:4294967295]	auto[1]	5	1			T77	1		T390	1		T394	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T3

2

T4

6

T13

1

auto[1]

1689

1

T2

5

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T4	1		T77	1		T184	1
auto[134217728:268435455]	118	1			T34	1		T5	1		T88	1
auto[268435456:402653183]	90	1			T2	1		T16	1		T18	2
auto[402653184:536870911]	114	1			T18	2		T5	1		T184	1
auto[536870912:671088639]	112	1			T16	1		T18	3		T5	1
auto[671088640:805306367]	95	1			T2	1		T18	1		T77	1
auto[805306368:939524095]	102	1			T16	1		T18	1		T5	1
auto[939524096:1073741823]	105	1			T50	1		T128	1		T172	1
auto[1073741824:1207959551]	124	1			T77	2		T86	1		T93	1
auto[1207959552:1342177279]	115	1			T18	2		T5	1		T181	1
auto[1342177280:1476395007]	96	1			T16	1		T18	2		T54	4
auto[1476395008:1610612735]	100	1			T18	2		T5	1		T50	1
auto[1610612736:1744830463]	73	1			T18	2		T58	1		T177	1
auto[1744830464:1879048191]	103	1			T2	1		T177	1		T19	1
auto[1879048192:2013265919]	95	1			T18	2		T5	1		T50	1
auto[2013265920:2147483647]	106	1			T16	1		T175	1		T115	2
auto[2147483648:2281701375]	80	1			T16	1		T18	2		T5	2
auto[2281701376:2415919103]	111	1			T18	1		T39	2		T91	1
auto[2415919104:2550136831]	89	1			T13	1		T18	1		T38	1
auto[2550136832:2684354559]	91	1			T18	2		T77	1		T5	1
auto[2684354560:2818572287]	90	1			T2	1		T3	1		T13	1
auto[2818572288:2952790015]	93	1			T127	1		T115	1		T128	1
auto[2952790016:3087007743]	102	1			T4	1		T18	2		T175	1
auto[3087007744:3221225471]	96	1			T2	1		T4	2		T18	3
auto[3221225472:3355443199]	107	1			T16	1		T18	3		T34	1
auto[3355443200:3489660927]	103	1			T16	1		T18	1		T128	1
auto[3489660928:3623878655]	104	1			T3	1		T34	2		T50	1
auto[3623878656:3758096383]	87	1			T3	1		T4	2		T18	1
auto[3758096384:3892314111]	119	1			T18	1		T34	1		T5	3
auto[3892314112:4026531839]	114	1			T18	1		T77	2		T86	1
auto[4026531840:4160749567]	93	1			T18	1		T5	1		T50	1
auto[4160749568:4294967295]	99	1			T4	1		T5	1		T115	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T4	1		T54	3		T57	1
auto[0:134217727]	auto[1]	43	1			T77	1		T184	1		T81	1
auto[134217728:268435455]	auto[0]	58	1			T34	1		T5	1		T59	2
auto[134217728:268435455]	auto[1]	60	1			T88	1		T172	1		T86	1
auto[268435456:402653183]	auto[0]	50	1			T16	1		T18	1		T106	1
auto[268435456:402653183]	auto[1]	40	1			T2	1		T18	1		T77	1
auto[402653184:536870911]	auto[0]	53	1			T18	1		T5	1		T178	1
auto[402653184:536870911]	auto[1]	61	1			T18	1		T184	1		T57	2
auto[536870912:671088639]	auto[0]	57	1			T16	1		T18	1		T5	1
auto[536870912:671088639]	auto[1]	55	1			T18	2		T106	1		T128	1
auto[671088640:805306367]	auto[0]	46	1			T18	1		T77	1		T94	1
auto[671088640:805306367]	auto[1]	49	1			T2	1		T81	1		T177	1
auto[805306368:939524095]	auto[0]	45	1			T16	1		T5	1		T175	1
auto[805306368:939524095]	auto[1]	57	1			T18	1		T127	1		T57	2
auto[939524096:1073741823]	auto[0]	44	1			T50	1		T172	1		T54	1
auto[939524096:1073741823]	auto[1]	61	1			T128	1		T54	1		T225	1
auto[1073741824:1207959551]	auto[0]	61	1			T77	1		T93	1		T54	3
auto[1073741824:1207959551]	auto[1]	63	1			T77	1		T86	1		T224	2
auto[1207959552:1342177279]	auto[0]	54	1			T18	2		T5	1		T54	2
auto[1207959552:1342177279]	auto[1]	61	1			T181	1		T22	1		T57	1
auto[1342177280:1476395007]	auto[0]	48	1			T16	1		T18	1		T54	3
auto[1342177280:1476395007]	auto[1]	48	1			T18	1		T54	1		T82	1
auto[1476395008:1610612735]	auto[0]	48	1			T5	1		T50	1		T54	2
auto[1476395008:1610612735]	auto[1]	52	1			T18	2		T81	1		T128	1
auto[1610612736:1744830463]	auto[0]	31	1			T18	2		T38	1		T22	1
auto[1610612736:1744830463]	auto[1]	42	1			T58	1		T177	1		T192	1
auto[1744830464:1879048191]	auto[0]	53	1			T177	1		T38	1		T179	1
auto[1744830464:1879048191]	auto[1]	50	1			T2	1		T19	1		T38	1
auto[1879048192:2013265919]	auto[0]	61	1			T18	2		T5	1		T50	1
auto[1879048192:2013265919]	auto[1]	34	1			T175	1		T177	1		T54	2
auto[2013265920:2147483647]	auto[0]	43	1			T16	1		T175	1		T115	1
auto[2013265920:2147483647]	auto[1]	63	1			T115	1		T93	1		T183	1
auto[2147483648:2281701375]	auto[0]	39	1			T16	1		T18	2		T5	1
auto[2147483648:2281701375]	auto[1]	41	1			T5	1		T54	2		T57	3
auto[2281701376:2415919103]	auto[0]	49	1			T39	1		T91	1		T57	1
auto[2281701376:2415919103]	auto[1]	62	1			T18	1		T39	1		T54	2
auto[2415919104:2550136831]	auto[0]	40	1			T13	1		T18	1		T38	1
auto[2415919104:2550136831]	auto[1]	49	1			T57	1		T179	1		T245	1
auto[2550136832:2684354559]	auto[0]	47	1			T18	2		T127	1		T115	1
auto[2550136832:2684354559]	auto[1]	44	1			T77	1		T5	1		T172	1
auto[2684354560:2818572287]	auto[0]	33	1			T3	1		T18	2		T50	1
auto[2684354560:2818572287]	auto[1]	57	1			T2	1		T13	1		T106	1
auto[2818572288:2952790015]	auto[0]	49	1			T127	1		T115	1		T128	1
auto[2818572288:2952790015]	auto[1]	44	1			T93	2		T57	1		T192	1
auto[2952790016:3087007743]	auto[0]	41	1			T4	1		T175	1		T91	2
auto[2952790016:3087007743]	auto[1]	61	1			T18	2		T181	1		T225	1
auto[3087007744:3221225471]	auto[0]	53	1			T4	1		T18	2		T5	1
auto[3087007744:3221225471]	auto[1]	43	1			T2	1		T4	1		T18	1
auto[3221225472:3355443199]	auto[0]	45	1			T16	1		T18	1		T34	1
auto[3221225472:3355443199]	auto[1]	62	1			T18	2		T54	3		T57	5
auto[3355443200:3489660927]	auto[0]	49	1			T18	1		T39	1		T54	1
auto[3355443200:3489660927]	auto[1]	54	1			T16	1		T128	1		T88	1
auto[3489660928:3623878655]	auto[0]	44	1			T34	1		T54	2		T57	1
auto[3489660928:3623878655]	auto[1]	60	1			T3	1		T34	1		T50	1
auto[3623878656:3758096383]	auto[0]	39	1			T3	1		T4	2		T54	1
auto[3623878656:3758096383]	auto[1]	48	1			T18	1		T46	1		T54	1
auto[3758096384:3892314111]	auto[0]	57	1			T34	1		T5	2		T50	1
auto[3758096384:3892314111]	auto[1]	62	1			T18	1		T5	1		T46	1
auto[3892314112:4026531839]	auto[0]	52	1			T18	1		T77	2		T54	2
auto[3892314112:4026531839]	auto[1]	62	1			T86	1		T91	1		T54	1
auto[4026531840:4160749567]	auto[0]	42	1			T18	1		T5	1		T50	1
auto[4026531840:4160749567]	auto[1]	51	1			T54	1		T57	3		T7	1
auto[4160749568:4294967295]	auto[0]	49	1			T4	1		T5	1		T115	1
auto[4160749568:4294967295]	auto[1]	50	1			T395	1		T62	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1529

1

T3

1

T4

6

T13

1

auto[1]

1696

1

T2

5

T3

2

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T2	1		T4	1		T13	1
auto[134217728:268435455]	116	1			T3	1		T16	1		T18	4
auto[268435456:402653183]	92	1			T18	1		T5	1		T94	1
auto[402653184:536870911]	97	1			T175	1		T58	1		T39	1
auto[536870912:671088639]	100	1			T77	1		T177	1		T39	1
auto[671088640:805306367]	107	1			T3	1		T18	1		T5	1
auto[805306368:939524095]	109	1			T18	4		T5	1		T106	2
auto[939524096:1073741823]	113	1			T13	1		T18	3		T43	1
auto[1073741824:1207959551]	113	1			T2	1		T18	1		T34	1
auto[1207959552:1342177279]	97	1			T77	1		T50	1		T127	1
auto[1342177280:1476395007]	89	1			T46	1		T81	1		T128	1
auto[1476395008:1610612735]	91	1			T5	2		T59	1		T91	1
auto[1610612736:1744830463]	109	1			T34	2		T5	1		T184	1
auto[1744830464:1879048191]	106	1			T18	1		T46	1		T128	1
auto[1879048192:2013265919]	88	1			T175	1		T58	1		T54	3
auto[2013265920:2147483647]	115	1			T4	1		T18	1		T5	1
auto[2147483648:2281701375]	102	1			T3	1		T4	1		T16	1
auto[2281701376:2415919103]	120	1			T18	1		T175	1		T81	1
auto[2415919104:2550136831]	81	1			T16	1		T18	1		T34	1
auto[2550136832:2684354559]	103	1			T18	2		T77	1		T5	1
auto[2684354560:2818572287]	111	1			T77	1		T115	2		T38	1
auto[2818572288:2952790015]	81	1			T2	1		T18	3		T88	1
auto[2952790016:3087007743]	99	1			T2	1		T4	1		T18	1
auto[3087007744:3221225471]	103	1			T16	1		T77	1		T5	2
auto[3221225472:3355443199]	94	1			T2	1		T4	1		T16	1
auto[3355443200:3489660927]	114	1			T4	2		T16	1		T18	2
auto[3489660928:3623878655]	114	1			T16	1		T18	1		T5	1
auto[3623878656:3758096383]	85	1			T18	1		T128	1		T93	1
auto[3758096384:3892314111]	93	1			T18	2		T127	1		T184	1
auto[3892314112:4026531839]	92	1			T16	1		T18	3		T106	1
auto[4026531840:4160749567]	107	1			T18	1		T172	2		T22	1
auto[4160749568:4294967295]	77	1			T18	1		T172	1		T22	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T4	1		T18	1		T50	1
auto[0:134217727]	auto[1]	58	1			T2	1		T13	1		T18	2
auto[134217728:268435455]	auto[0]	54	1			T16	1		T18	2		T5	1
auto[134217728:268435455]	auto[1]	62	1			T3	1		T18	2		T5	1
auto[268435456:402653183]	auto[0]	36	1			T18	1		T94	1		T54	2
auto[268435456:402653183]	auto[1]	56	1			T5	1		T96	1		T225	1
auto[402653184:536870911]	auto[0]	46	1			T175	1		T57	1		T179	1
auto[402653184:536870911]	auto[1]	51	1			T58	1		T39	1		T57	3
auto[536870912:671088639]	auto[0]	58	1			T177	1		T39	1		T54	3
auto[536870912:671088639]	auto[1]	42	1			T77	1		T57	1		T224	1
auto[671088640:805306367]	auto[0]	53	1			T18	1		T5	1		T182	1
auto[671088640:805306367]	auto[1]	54	1			T3	1		T39	1		T54	1
auto[805306368:939524095]	auto[0]	50	1			T18	1		T7	1		T242	1
auto[805306368:939524095]	auto[1]	59	1			T18	3		T5	1		T106	2
auto[939524096:1073741823]	auto[0]	54	1			T13	1		T18	1		T5	1
auto[939524096:1073741823]	auto[1]	59	1			T18	2		T43	1		T77	1
auto[1073741824:1207959551]	auto[0]	59	1			T18	1		T34	1		T175	1
auto[1073741824:1207959551]	auto[1]	54	1			T2	1		T177	1		T59	1
auto[1207959552:1342177279]	auto[0]	56	1			T50	1		T127	1		T115	1
auto[1207959552:1342177279]	auto[1]	41	1			T77	1		T396	1		T237	1
auto[1342177280:1476395007]	auto[0]	35	1			T128	1		T54	1		T224	1
auto[1342177280:1476395007]	auto[1]	54	1			T46	1		T81	1		T178	1
auto[1476395008:1610612735]	auto[0]	48	1			T5	1		T91	1		T57	2
auto[1476395008:1610612735]	auto[1]	43	1			T5	1		T59	1		T57	1
auto[1610612736:1744830463]	auto[0]	56	1			T34	2		T5	1		T128	1
auto[1610612736:1744830463]	auto[1]	53	1			T184	1		T57	2		T192	1
auto[1744830464:1879048191]	auto[0]	45	1			T242	1		T47	1		T271	1
auto[1744830464:1879048191]	auto[1]	61	1			T18	1		T46	1		T128	1
auto[1879048192:2013265919]	auto[0]	46	1			T175	1		T54	2		T82	1
auto[1879048192:2013265919]	auto[1]	42	1			T58	1		T54	1		T57	1
auto[2013265920:2147483647]	auto[0]	56	1			T4	1		T5	1		T50	1
auto[2013265920:2147483647]	auto[1]	59	1			T18	1		T128	1		T54	1
auto[2147483648:2281701375]	auto[0]	53	1			T3	1		T4	1		T16	1
auto[2147483648:2281701375]	auto[1]	49	1			T54	2		T307	1		T7	2
auto[2281701376:2415919103]	auto[0]	49	1			T18	1		T175	1		T54	1
auto[2281701376:2415919103]	auto[1]	71	1			T81	1		T177	1		T86	1
auto[2415919104:2550136831]	auto[0]	35	1			T16	1		T18	1		T34	1
auto[2415919104:2550136831]	auto[1]	46	1			T175	1		T54	1		T57	5
auto[2550136832:2684354559]	auto[0]	52	1			T77	1		T5	1		T50	1
auto[2550136832:2684354559]	auto[1]	51	1			T18	2		T57	2		T179	1
auto[2684354560:2818572287]	auto[0]	40	1			T115	1		T39	1		T54	1
auto[2684354560:2818572287]	auto[1]	71	1			T77	1		T115	1		T38	1
auto[2818572288:2952790015]	auto[0]	34	1			T18	3		T54	2		T82	1
auto[2818572288:2952790015]	auto[1]	47	1			T2	1		T88	1		T181	2
auto[2952790016:3087007743]	auto[0]	54	1			T4	1		T18	1		T34	1
auto[2952790016:3087007743]	auto[1]	45	1			T2	1		T181	1		T91	1
auto[3087007744:3221225471]	auto[0]	55	1			T16	1		T5	2		T57	3
auto[3087007744:3221225471]	auto[1]	48	1			T77	1		T177	1		T91	1
auto[3221225472:3355443199]	auto[0]	46	1			T16	1		T77	1		T38	1
auto[3221225472:3355443199]	auto[1]	48	1			T2	1		T4	1		T18	1
auto[3355443200:3489660927]	auto[0]	54	1			T4	2		T16	1		T18	2
auto[3355443200:3489660927]	auto[1]	60	1			T128	1		T62	1		T261	1
auto[3489660928:3623878655]	auto[0]	55	1			T16	1		T18	1		T54	1
auto[3489660928:3623878655]	auto[1]	59	1			T5	1		T175	1		T106	1
auto[3623878656:3758096383]	auto[0]	42	1			T57	1		T78	1		T174	1
auto[3623878656:3758096383]	auto[1]	43	1			T18	1		T128	1		T93	1
auto[3758096384:3892314111]	auto[0]	34	1			T18	1		T127	1		T128	1
auto[3758096384:3892314111]	auto[1]	59	1			T18	1		T184	1		T59	1
auto[3892314112:4026531839]	auto[0]	42	1			T16	1		T18	3		T106	1
auto[3892314112:4026531839]	auto[1]	50	1			T81	1		T177	1		T93	1
auto[4026531840:4160749567]	auto[0]	54	1			T22	1		T57	1		T173	1
auto[4026531840:4160749567]	auto[1]	53	1			T18	1		T172	2		T173	1
auto[4160749568:4294967295]	auto[0]	29	1			T172	1		T22	1		T94	1
auto[4160749568:4294967295]	auto[1]	48	1			T18	1		T57	1		T7	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1541

1

T3

2

T4

7

T13

1

auto[1]

1682

1

T2

5

T3

1

T13

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T18	2		T175	1		T88	1
auto[134217728:268435455]	93	1			T18	3		T77	1		T46	1
auto[268435456:402653183]	91	1			T4	1		T13	1		T16	1
auto[402653184:536870911]	108	1			T5	1		T184	1		T19	1
auto[536870912:671088639]	95	1			T16	1		T18	3		T115	1
auto[671088640:805306367]	89	1			T2	1		T181	1		T54	4
auto[805306368:939524095]	92	1			T4	1		T77	2		T128	1
auto[939524096:1073741823]	100	1			T18	1		T5	2		T175	1
auto[1073741824:1207959551]	115	1			T13	1		T18	2		T34	1
auto[1207959552:1342177279]	105	1			T16	1		T18	1		T106	1
auto[1342177280:1476395007]	102	1			T77	1		T5	2		T106	1
auto[1476395008:1610612735]	104	1			T18	1		T34	1		T50	1
auto[1610612736:1744830463]	111	1			T18	2		T77	1		T128	3
auto[1744830464:1879048191]	104	1			T18	1		T34	1		T50	1
auto[1879048192:2013265919]	93	1			T18	1		T50	1		T178	1
auto[2013265920:2147483647]	97	1			T54	1		T182	1		T57	2
auto[2147483648:2281701375]	93	1			T18	1		T5	1		T54	2
auto[2281701376:2415919103]	114	1			T2	1		T3	1		T18	1
auto[2415919104:2550136831]	109	1			T2	1		T4	2		T18	1
auto[2550136832:2684354559]	98	1			T3	1		T177	1		T181	1
auto[2684354560:2818572287]	101	1			T16	1		T18	1		T5	2
auto[2818572288:2952790015]	113	1			T18	2		T34	1		T5	3
auto[2952790016:3087007743]	114	1			T18	2		T34	1		T43	1
auto[3087007744:3221225471]	97	1			T16	1		T18	2		T77	1
auto[3221225472:3355443199]	100	1			T18	1		T175	1		T127	1
auto[3355443200:3489660927]	93	1			T4	1		T16	1		T18	3
auto[3489660928:3623878655]	85	1			T2	1		T16	1		T18	2
auto[3623878656:3758096383]	106	1			T18	1		T175	1		T106	1
auto[3758096384:3892314111]	93	1			T2	1		T4	2		T77	1
auto[3892314112:4026531839]	97	1			T18	3		T127	1		T172	1
auto[4026531840:4160749567]	112	1			T16	1		T18	1		T50	1
auto[4160749568:4294967295]	92	1			T3	1		T18	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T18	1		T38	2		T383	1
auto[0:134217727]	auto[1]	64	1			T18	1		T175	1		T88	1
auto[134217728:268435455]	auto[0]	44	1			T18	1		T77	1		T38	1
auto[134217728:268435455]	auto[1]	49	1			T18	2		T46	1		T39	1
auto[268435456:402653183]	auto[0]	37	1			T4	1		T16	1		T18	1
auto[268435456:402653183]	auto[1]	54	1			T13	1		T81	1		T128	1
auto[402653184:536870911]	auto[0]	55	1			T5	1		T38	1		T22	2
auto[402653184:536870911]	auto[1]	53	1			T184	1		T19	1		T57	1
auto[536870912:671088639]	auto[0]	48	1			T18	2		T115	1		T81	1
auto[536870912:671088639]	auto[1]	47	1			T16	1		T18	1		T58	1
auto[671088640:805306367]	auto[0]	43	1			T54	3		T57	1		T23	1
auto[671088640:805306367]	auto[1]	46	1			T2	1		T181	1		T54	1
auto[805306368:939524095]	auto[0]	43	1			T4	1		T77	1		T88	1
auto[805306368:939524095]	auto[1]	49	1			T77	1		T128	1		T58	1
auto[939524096:1073741823]	auto[0]	53	1			T5	1		T175	1		T57	1
auto[939524096:1073741823]	auto[1]	47	1			T18	1		T5	1		T307	1
auto[1073741824:1207959551]	auto[0]	57	1			T13	1		T18	2		T38	1
auto[1073741824:1207959551]	auto[1]	58	1			T34	1		T115	1		T86	1
auto[1207959552:1342177279]	auto[0]	49	1			T16	1		T106	1		T57	1
auto[1207959552:1342177279]	auto[1]	56	1			T18	1		T57	1		T242	1
auto[1342177280:1476395007]	auto[0]	47	1			T5	2		T115	1		T57	3
auto[1342177280:1476395007]	auto[1]	55	1			T77	1		T106	1		T81	1
auto[1476395008:1610612735]	auto[0]	54	1			T34	1		T50	1		T81	1
auto[1476395008:1610612735]	auto[1]	50	1			T18	1		T59	1		T225	1
auto[1610612736:1744830463]	auto[0]	49	1			T18	1		T128	2		T54	2
auto[1610612736:1744830463]	auto[1]	62	1			T18	1		T77	1		T128	1
auto[1744830464:1879048191]	auto[0]	58	1			T18	1		T34	1		T50	1
auto[1744830464:1879048191]	auto[1]	46	1			T177	1		T86	1		T57	2
auto[1879048192:2013265919]	auto[0]	40	1			T50	1		T38	1		T192	1
auto[1879048192:2013265919]	auto[1]	53	1			T18	1		T178	1		T177	1
auto[2013265920:2147483647]	auto[0]	50	1			T182	1		T179	1		T129	1
auto[2013265920:2147483647]	auto[1]	47	1			T54	1		T57	2		T179	1
auto[2147483648:2281701375]	auto[0]	48	1			T18	1		T5	1		T54	1
auto[2147483648:2281701375]	auto[1]	45	1			T54	1		T57	2		T7	1
auto[2281701376:2415919103]	auto[0]	61	1			T3	1		T18	1		T50	1
auto[2281701376:2415919103]	auto[1]	53	1			T2	1		T57	2		T307	1
auto[2415919104:2550136831]	auto[0]	48	1			T4	2		T18	1		T5	1
auto[2415919104:2550136831]	auto[1]	61	1			T2	1		T54	1		T57	2
auto[2550136832:2684354559]	auto[0]	47	1			T57	1		T224	1		T179	1
auto[2550136832:2684354559]	auto[1]	51	1			T3	1		T177	1		T181	1
auto[2684354560:2818572287]	auto[0]	57	1			T16	1		T18	1		T5	2
auto[2684354560:2818572287]	auto[1]	44	1			T54	2		T245	1		T395	1
auto[2818572288:2952790015]	auto[0]	60	1			T34	1		T5	2		T46	1
auto[2818572288:2952790015]	auto[1]	53	1			T18	2		T5	1		T177	1
auto[2952790016:3087007743]	auto[0]	46	1			T18	1		T34	1		T5	1
auto[2952790016:3087007743]	auto[1]	68	1			T18	1		T43	1		T184	1
auto[3087007744:3221225471]	auto[0]	40	1			T16	1		T18	2		T57	1
auto[3087007744:3221225471]	auto[1]	57	1			T77	1		T128	1		T54	1
auto[3221225472:3355443199]	auto[0]	50	1			T18	1		T127	1		T81	1
auto[3221225472:3355443199]	auto[1]	50	1			T175	1		T177	1		T172	1
auto[3355443200:3489660927]	auto[0]	39	1			T4	1		T16	1		T18	1
auto[3355443200:3489660927]	auto[1]	54	1			T18	2		T127	1		T81	1
auto[3489660928:3623878655]	auto[0]	42	1			T16	1		T5	1		T50	1
auto[3489660928:3623878655]	auto[1]	43	1			T2	1		T18	2		T77	1
auto[3623878656:3758096383]	auto[0]	47	1			T18	1		T106	1		T54	3
auto[3623878656:3758096383]	auto[1]	59	1			T175	1		T182	1		T7	1
auto[3758096384:3892314111]	auto[0]	47	1			T4	2		T5	1		T39	1
auto[3758096384:3892314111]	auto[1]	46	1			T2	1		T77	1		T38	1
auto[3892314112:4026531839]	auto[0]	46	1			T18	2		T127	1		T225	1
auto[3892314112:4026531839]	auto[1]	51	1			T18	1		T172	1		T181	1
auto[4026531840:4160749567]	auto[0]	53	1			T16	1		T50	1		T54	1
auto[4026531840:4160749567]	auto[1]	59	1			T18	1		T54	1		T57	2
auto[4160749568:4294967295]	auto[0]	40	1			T3	1		T5	1		T172	1
auto[4160749568:4294967295]	auto[1]	52	1			T18	1		T128	1		T54	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T3

2

T4

6

T13

2

auto[1]

1690

1

T2

5

T3

1

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T18	3		T81	1		T128	1
auto[134217728:268435455]	104	1			T3	1		T16	1		T18	2
auto[268435456:402653183]	88	1			T4	1		T16	1		T18	2
auto[402653184:536870911]	108	1			T34	1		T50	1		T177	1
auto[536870912:671088639]	88	1			T18	1		T34	1		T77	1
auto[671088640:805306367]	113	1			T4	1		T18	1		T178	1
auto[805306368:939524095]	101	1			T18	3		T81	1		T86	1
auto[939524096:1073741823]	100	1			T4	1		T13	1		T16	1
auto[1073741824:1207959551]	106	1			T18	1		T5	1		T106	1
auto[1207959552:1342177279]	112	1			T18	2		T5	1		T46	1
auto[1342177280:1476395007]	95	1			T3	1		T77	1		T5	1
auto[1476395008:1610612735]	113	1			T18	1		T77	1		T175	2
auto[1610612736:1744830463]	103	1			T2	2		T16	1		T77	2
auto[1744830464:1879048191]	105	1			T18	1		T115	1		T38	1
auto[1879048192:2013265919]	102	1			T2	1		T3	1		T16	1
auto[2013265920:2147483647]	100	1			T4	1		T34	1		T50	1
auto[2147483648:2281701375]	99	1			T18	1		T5	1		T50	1
auto[2281701376:2415919103]	127	1			T2	1		T172	1		T38	1
auto[2415919104:2550136831]	89	1			T18	1		T5	1		T115	1
auto[2550136832:2684354559]	106	1			T16	1		T18	1		T115	1
auto[2684354560:2818572287]	111	1			T2	1		T18	1		T5	2
auto[2818572288:2952790015]	98	1			T18	1		T127	1		T106	1
auto[2952790016:3087007743]	77	1			T18	1		T34	1		T54	2
auto[3087007744:3221225471]	90	1			T18	4		T5	2		T50	1
auto[3221225472:3355443199]	118	1			T4	1		T18	1		T77	1
auto[3355443200:3489660927]	93	1			T18	1		T128	1		T172	1
auto[3489660928:3623878655]	82	1			T127	1		T181	1		T93	1
auto[3623878656:3758096383]	102	1			T4	1		T18	2		T5	1
auto[3758096384:3892314111]	85	1			T16	1		T18	1		T34	1
auto[3892314112:4026531839]	92	1			T4	1		T18	3		T5	1
auto[4026531840:4160749567]	95	1			T18	1		T77	1		T5	1
auto[4160749568:4294967295]	118	1			T13	1		T16	1		T59	1