Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4280

1

T2

8

T3

6

T4

14

auto[1]

2174

1

T2

2

T13

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	178	1			T2	2		T4	4		T13	2
auto[134217728:268435455]	218	1			T16	2		T18	4		T54	6
auto[268435456:402653183]	200	1			T18	6		T5	2		T175	2
auto[402653184:536870911]	204	1			T18	2		T50	2		T106	2
auto[536870912:671088639]	192	1			T18	4		T77	4		T46	2
auto[671088640:805306367]	204	1			T18	6		T43	2		T175	2
auto[805306368:939524095]	218	1			T77	2		T5	6		T54	8
auto[939524096:1073741823]	176	1			T16	2		T5	2		T177	2
auto[1073741824:1207959551]	232	1			T18	2		T50	2		T127	2
auto[1207959552:1342177279]	190	1			T18	2		T50	2		T177	2
auto[1342177280:1476395007]	204	1			T2	2		T3	2		T18	6
auto[1476395008:1610612735]	200	1			T13	2		T5	2		T178	2
auto[1610612736:1744830463]	186	1			T16	2		T50	2		T175	2
auto[1744830464:1879048191]	196	1			T18	4		T34	2		T77	2
auto[1879048192:2013265919]	198	1			T2	2		T18	4		T77	2
auto[2013265920:2147483647]	200	1			T2	2		T3	2		T18	2
auto[2147483648:2281701375]	154	1			T4	2		T18	2		T5	2
auto[2281701376:2415919103]	226	1			T4	2		T16	2		T18	2
auto[2415919104:2550136831]	194	1			T81	2		T39	2		T94	2
auto[2550136832:2684354559]	190	1			T177	4		T181	2		T57	8
auto[2684354560:2818572287]	192	1			T16	2		T18	4		T50	2
auto[2818572288:2952790015]	228	1			T3	2		T18	4		T77	2
auto[2952790016:3087007743]	190	1			T4	2		T34	2		T115	2
auto[3087007744:3221225471]	242	1			T2	2		T4	2		T16	2
auto[3221225472:3355443199]	236	1			T127	4		T106	4		T81	2
auto[3355443200:3489660927]	200	1			T18	4		T128	2		T54	6
auto[3489660928:3623878655]	188	1			T18	2		T77	2		T50	2
auto[3623878656:3758096383]	210	1			T16	2		T18	2		T175	2
auto[3758096384:3892314111]	200	1			T18	2		T106	2		T115	2
auto[3892314112:4026531839]	202	1			T5	2		T22	2		T93	2
auto[4026531840:4160749567]	202	1			T18	6		T5	4		T128	2
auto[4160749568:4294967295]	204	1			T4	2		T16	2		T18	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	120	1			T2	2		T4	4		T77	2
auto[0:134217727]	auto[1]	58	1			T13	2		T47	2		T382	2
auto[134217728:268435455]	auto[0]	138	1			T16	2		T18	4		T7	4
auto[134217728:268435455]	auto[1]	80	1			T54	6		T182	2		T174	2
auto[268435456:402653183]	auto[0]	138	1			T18	4		T5	2		T38	2
auto[268435456:402653183]	auto[1]	62	1			T18	2		T175	2		T38	2
auto[402653184:536870911]	auto[0]	140	1			T50	2		T106	2		T57	6
auto[402653184:536870911]	auto[1]	64	1			T18	2		T54	2		T57	2
auto[536870912:671088639]	auto[0]	134	1			T18	4		T77	4		T46	2
auto[536870912:671088639]	auto[1]	58	1			T185	2		T7	4		T190	2
auto[671088640:805306367]	auto[0]	142	1			T18	4		T175	2		T57	4
auto[671088640:805306367]	auto[1]	62	1			T18	2		T43	2		T184	2
auto[805306368:939524095]	auto[0]	140	1			T77	2		T5	4		T54	6
auto[805306368:939524095]	auto[1]	78	1			T5	2		T54	2		T307	2
auto[939524096:1073741823]	auto[0]	116	1			T16	2		T5	2		T177	2
auto[939524096:1073741823]	auto[1]	60	1			T54	4		T185	2		T7	2
auto[1073741824:1207959551]	auto[0]	152	1			T18	2		T127	2		T128	2
auto[1073741824:1207959551]	auto[1]	80	1			T50	2		T96	2		T57	2
auto[1207959552:1342177279]	auto[0]	142	1			T50	2		T177	2		T54	2
auto[1207959552:1342177279]	auto[1]	48	1			T18	2		T191	2		T129	2
auto[1342177280:1476395007]	auto[0]	148	1			T2	2		T3	2		T18	6
auto[1342177280:1476395007]	auto[1]	56	1			T86	2		T96	2		T57	4
auto[1476395008:1610612735]	auto[0]	124	1			T13	2		T5	2		T177	2
auto[1476395008:1610612735]	auto[1]	76	1			T178	2		T96	4		T82	2
auto[1610612736:1744830463]	auto[0]	124	1			T50	2		T175	2		T115	2
auto[1610612736:1744830463]	auto[1]	62	1			T16	2		T128	2		T88	2
auto[1744830464:1879048191]	auto[0]	122	1			T18	4		T34	2		T77	2
auto[1744830464:1879048191]	auto[1]	74	1			T54	2		T57	2		T395	2
auto[1879048192:2013265919]	auto[0]	146	1			T2	2		T18	2		T77	2
auto[1879048192:2013265919]	auto[1]	52	1			T18	2		T65	2		T397	2
auto[2013265920:2147483647]	auto[0]	136	1			T2	2		T3	2		T5	2
auto[2013265920:2147483647]	auto[1]	64	1			T18	2		T34	2		T23	2
auto[2147483648:2281701375]	auto[0]	88	1			T4	2		T5	2		T172	2
auto[2147483648:2281701375]	auto[1]	66	1			T18	2		T54	4		T57	2
auto[2281701376:2415919103]	auto[0]	150	1			T4	2		T16	2		T128	2
auto[2281701376:2415919103]	auto[1]	76	1			T18	2		T19	2		T57	2
auto[2415919104:2550136831]	auto[0]	120	1			T94	2		T54	4		T224	2
auto[2415919104:2550136831]	auto[1]	74	1			T81	2		T39	2		T54	2
auto[2550136832:2684354559]	auto[0]	126	1			T177	4		T181	2		T57	4
auto[2550136832:2684354559]	auto[1]	64	1			T57	4		T179	2		T185	2
auto[2684354560:2818572287]	auto[0]	122	1			T16	2		T18	4		T50	2
auto[2684354560:2818572287]	auto[1]	70	1			T81	2		T38	2		T307	2
auto[2818572288:2952790015]	auto[0]	162	1			T3	2		T18	2		T50	2
auto[2818572288:2952790015]	auto[1]	66	1			T18	2		T77	2		T7	2
auto[2952790016:3087007743]	auto[0]	122	1			T4	2		T34	2		T115	2
auto[2952790016:3087007743]	auto[1]	68	1			T128	2		T40	2		T190	2
auto[3087007744:3221225471]	auto[0]	160	1			T4	2		T16	2		T18	4
auto[3087007744:3221225471]	auto[1]	82	1			T2	2		T18	4		T175	2
auto[3221225472:3355443199]	auto[0]	156	1			T127	2		T106	2		T86	2
auto[3221225472:3355443199]	auto[1]	80	1			T127	2		T106	2		T81	2
auto[3355443200:3489660927]	auto[0]	124	1			T18	4		T54	6		T225	2
auto[3355443200:3489660927]	auto[1]	76	1			T128	2		T57	2		T63	2
auto[3489660928:3623878655]	auto[0]	136	1			T18	2		T77	2		T50	2
auto[3489660928:3623878655]	auto[1]	52	1			T81	2		T54	2		T242	2
auto[3623878656:3758096383]	auto[0]	132	1			T16	2		T18	2		T175	2
auto[3623878656:3758096383]	auto[1]	78	1			T184	2		T54	2		T191	2
auto[3758096384:3892314111]	auto[0]	124	1			T18	2		T106	2		T115	2
auto[3758096384:3892314111]	auto[1]	76	1			T81	2		T22	2		T54	4
auto[3892314112:4026531839]	auto[0]	122	1			T5	2		T22	2		T93	2
auto[3892314112:4026531839]	auto[1]	80	1			T80	2		T261	2		T193	2
auto[4026531840:4160749567]	auto[0]	122	1			T18	4		T5	4		T128	2
auto[4026531840:4160749567]	auto[1]	80	1			T18	2		T39	2		T22	2
auto[4160749568:4294967295]	auto[0]	152	1			T4	2		T16	2		T18	2
auto[4160749568:4294967295]	auto[1]	52	1			T57	2		T83	2		T271	2