Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2849

1

T2

5

T3

2

T4

7

auto[1]

272

1

T77

11

T106

2

T115

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T4	1		T34	1		T50	1
auto[134217728:268435455]	73	1			T18	1		T86	1		T54	1
auto[268435456:402653183]	91	1			T18	2		T77	2		T46	1
auto[402653184:536870911]	88	1			T3	1		T13	1		T77	2
auto[536870912:671088639]	114	1			T106	1		T177	1		T86	1
auto[671088640:805306367]	100	1			T2	1		T77	1		T181	1
auto[805306368:939524095]	75	1			T5	1		T39	1		T54	2
auto[939524096:1073741823]	105	1			T4	1		T16	1		T18	1
auto[1073741824:1207959551]	89	1			T77	1		T5	1		T175	1
auto[1207959552:1342177279]	106	1			T4	1		T18	1		T46	1
auto[1342177280:1476395007]	88	1			T2	1		T18	2		T77	1
auto[1476395008:1610612735]	91	1			T18	3		T77	2		T50	1
auto[1610612736:1744830463]	77	1			T128	1		T38	1		T22	1
auto[1744830464:1879048191]	92	1			T18	2		T77	1		T175	1
auto[1879048192:2013265919]	101	1			T18	2		T115	1		T19	1
auto[2013265920:2147483647]	115	1			T2	1		T3	1		T18	1
auto[2147483648:2281701375]	98	1			T18	2		T184	1		T57	2
auto[2281701376:2415919103]	107	1			T18	1		T175	1		T177	1
auto[2415919104:2550136831]	104	1			T18	2		T5	1		T106	1
auto[2550136832:2684354559]	109	1			T2	2		T4	1		T175	1
auto[2684354560:2818572287]	101	1			T18	2		T43	1		T77	2
auto[2818572288:2952790015]	107	1			T34	1		T178	1		T38	1
auto[2952790016:3087007743]	95	1			T4	1		T5	1		T181	1
auto[3087007744:3221225471]	105	1			T4	1		T18	2		T77	1
auto[3221225472:3355443199]	82	1			T13	1		T5	1		T115	1
auto[3355443200:3489660927]	133	1			T18	2		T77	1		T5	1
auto[3489660928:3623878655]	100	1			T18	3		T175	1		T115	1
auto[3623878656:3758096383]	97	1			T77	1		T39	1		T54	1
auto[3758096384:3892314111]	99	1			T77	2		T38	1		T93	1
auto[3892314112:4026531839]	90	1			T4	1		T18	2		T77	1
auto[4026531840:4160749567]	90	1			T18	3		T184	1		T115	1
auto[4160749568:4294967295]	95	1			T18	1		T77	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T4	1		T34	1		T50	1
auto[0:134217727]	auto[1]	9	1			T174	2		T280	1		T349	1
auto[134217728:268435455]	auto[0]	66	1			T18	1		T86	1		T54	1
auto[134217728:268435455]	auto[1]	7	1			T281	1		T359	1		T320	2
auto[268435456:402653183]	auto[0]	83	1			T18	2		T46	1		T106	1
auto[268435456:402653183]	auto[1]	8	1			T77	2		T174	1		T280	1
auto[402653184:536870911]	auto[0]	76	1			T3	1		T13	1		T175	1
auto[402653184:536870911]	auto[1]	12	1			T77	2		T115	2		T174	2
auto[536870912:671088639]	auto[0]	107	1			T106	1		T177	1		T86	1
auto[536870912:671088639]	auto[1]	7	1			T391	1		T359	1		T320	1
auto[671088640:805306367]	auto[0]	88	1			T2	1		T77	1		T181	1
auto[671088640:805306367]	auto[1]	12	1			T224	1		T252	1		T272	1
auto[805306368:939524095]	auto[0]	67	1			T5	1		T39	1		T54	2
auto[805306368:939524095]	auto[1]	8	1			T183	1		T252	1		T282	1
auto[939524096:1073741823]	auto[0]	96	1			T4	1		T16	1		T18	1
auto[939524096:1073741823]	auto[1]	9	1			T393	1		T349	1		T282	1
auto[1073741824:1207959551]	auto[0]	84	1			T77	1		T5	1		T175	1
auto[1073741824:1207959551]	auto[1]	5	1			T183	1		T174	1		T282	1
auto[1207959552:1342177279]	auto[0]	100	1			T4	1		T18	1		T46	1
auto[1207959552:1342177279]	auto[1]	6	1			T174	1		T252	1		T223	1
auto[1342177280:1476395007]	auto[0]	84	1			T2	1		T18	2		T88	1
auto[1342177280:1476395007]	auto[1]	4	1			T77	1		T224	1		T183	1
auto[1476395008:1610612735]	auto[0]	82	1			T18	3		T77	1		T50	1
auto[1476395008:1610612735]	auto[1]	9	1			T77	1		T252	2		T320	1
auto[1610612736:1744830463]	auto[0]	69	1			T128	1		T38	1		T22	1
auto[1610612736:1744830463]	auto[1]	8	1			T224	1		T349	1		T359	1
auto[1744830464:1879048191]	auto[0]	82	1			T18	2		T175	1		T86	1
auto[1744830464:1879048191]	auto[1]	10	1			T77	1		T106	1		T389	1
auto[1879048192:2013265919]	auto[0]	94	1			T18	2		T115	1		T19	1
auto[1879048192:2013265919]	auto[1]	7	1			T252	1		T272	1		T349	1
auto[2013265920:2147483647]	auto[0]	104	1			T2	1		T3	1		T18	1
auto[2013265920:2147483647]	auto[1]	11	1			T224	1		T174	1		T280	1
auto[2147483648:2281701375]	auto[0]	90	1			T18	2		T184	1		T57	2
auto[2147483648:2281701375]	auto[1]	8	1			T183	1		T272	1		T282	1
auto[2281701376:2415919103]	auto[0]	98	1			T18	1		T175	1		T177	1
auto[2281701376:2415919103]	auto[1]	9	1			T252	1		T281	1		T272	1
auto[2415919104:2550136831]	auto[0]	100	1			T18	2		T5	1		T106	1
auto[2415919104:2550136831]	auto[1]	4	1			T115	2		T402	1		T403	1
auto[2550136832:2684354559]	auto[0]	100	1			T2	2		T4	1		T175	1
auto[2550136832:2684354559]	auto[1]	9	1			T224	1		T174	1		T281	1
auto[2684354560:2818572287]	auto[0]	93	1			T18	2		T43	1		T128	1
auto[2684354560:2818572287]	auto[1]	8	1			T77	2		T91	1		T224	1
auto[2818572288:2952790015]	auto[0]	94	1			T34	1		T178	1		T38	1
auto[2818572288:2952790015]	auto[1]	13	1			T282	1		T320	1		T323	1
auto[2952790016:3087007743]	auto[0]	90	1			T4	1		T5	1		T181	1
auto[2952790016:3087007743]	auto[1]	5	1			T224	1		T280	1		T282	1
auto[3087007744:3221225471]	auto[0]	96	1			T4	1		T18	2		T77	1
auto[3087007744:3221225471]	auto[1]	9	1			T106	1		T174	1		T272	1
auto[3221225472:3355443199]	auto[0]	75	1			T13	1		T5	1		T58	1
auto[3221225472:3355443199]	auto[1]	7	1			T115	1		T224	2		T280	1
auto[3355443200:3489660927]	auto[0]	121	1			T18	2		T77	1		T5	1
auto[3355443200:3489660927]	auto[1]	12	1			T349	1		T359	2		T320	2
auto[3489660928:3623878655]	auto[0]	92	1			T18	3		T175	1		T91	1
auto[3489660928:3623878655]	auto[1]	8	1			T115	1		T323	1		T390	1
auto[3623878656:3758096383]	auto[0]	88	1			T77	1		T39	1		T54	1
auto[3623878656:3758096383]	auto[1]	9	1			T224	1		T282	1		T323	1
auto[3758096384:3892314111]	auto[0]	87	1			T77	1		T38	1		T93	1
auto[3758096384:3892314111]	auto[1]	12	1			T77	1		T174	2		T359	1
auto[3892314112:4026531839]	auto[0]	83	1			T4	1		T18	2		T81	2
auto[3892314112:4026531839]	auto[1]	7	1			T77	1		T252	1		T393	1
auto[4026531840:4160749567]	auto[0]	82	1			T18	3		T184	1		T57	3
auto[4026531840:4160749567]	auto[1]	8	1			T115	1		T282	1		T404	2
auto[4160749568:4294967295]	auto[0]	83	1			T18	1		T77	1		T5	1
auto[4160749568:4294967295]	auto[1]	12	1			T91	1		T224	1		T183	1