Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.10 97.95 98.58 100.00 99.11 98.41 91.63


Total test records in report: 1071
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T1006 /workspace/coverage/default/46.keymgr_sync_async_fault_cross.293921452 Feb 26 03:18:16 PM PST 24 Feb 26 03:18:18 PM PST 24 68653482 ps
T1007 /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1356783473 Feb 26 03:16:19 PM PST 24 Feb 26 03:16:28 PM PST 24 566765708 ps
T1008 /workspace/coverage/default/46.keymgr_sideload_kmac.2453261599 Feb 26 03:18:13 PM PST 24 Feb 26 03:18:55 PM PST 24 8817385972 ps
T1009 /workspace/coverage/default/14.keymgr_sideload_protect.959637907 Feb 26 03:15:31 PM PST 24 Feb 26 03:15:35 PM PST 24 128079233 ps
T1010 /workspace/coverage/default/20.keymgr_sideload_kmac.3657779783 Feb 26 03:16:13 PM PST 24 Feb 26 03:16:16 PM PST 24 92530627 ps
T1011 /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2509115481 Feb 26 03:16:53 PM PST 24 Feb 26 03:16:55 PM PST 24 80037056 ps
T1012 /workspace/coverage/default/41.keymgr_sideload_otbn.4069318664 Feb 26 03:17:41 PM PST 24 Feb 26 03:17:45 PM PST 24 52660443 ps
T408 /workspace/coverage/default/19.keymgr_cfg_regwen.1266169071 Feb 26 03:15:59 PM PST 24 Feb 26 03:16:41 PM PST 24 843815452 ps
T1013 /workspace/coverage/default/6.keymgr_lc_disable.262583224 Feb 26 03:14:46 PM PST 24 Feb 26 03:14:50 PM PST 24 74213496 ps
T1014 /workspace/coverage/default/15.keymgr_sideload_kmac.1481212880 Feb 26 03:15:38 PM PST 24 Feb 26 03:17:00 PM PST 24 4583902313 ps
T1015 /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1382894907 Feb 26 03:17:15 PM PST 24 Feb 26 03:17:17 PM PST 24 466006094 ps
T154 /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3039036616 Feb 26 03:15:58 PM PST 24 Feb 26 03:16:01 PM PST 24 104796343 ps
T1016 /workspace/coverage/default/19.keymgr_direct_to_disabled.2337029266 Feb 26 03:16:04 PM PST 24 Feb 26 03:16:07 PM PST 24 46858530 ps
T1017 /workspace/coverage/default/30.keymgr_sideload_otbn.2141229482 Feb 26 03:16:54 PM PST 24 Feb 26 03:16:56 PM PST 24 66839468 ps
T1018 /workspace/coverage/default/0.keymgr_custom_cm.785814961 Feb 26 03:13:49 PM PST 24 Feb 26 03:13:52 PM PST 24 69862262 ps
T1019 /workspace/coverage/default/22.keymgr_smoke.1843602556 Feb 26 03:16:14 PM PST 24 Feb 26 03:16:19 PM PST 24 504390956 ps
T1020 /workspace/coverage/default/41.keymgr_sw_invalid_input.4032284449 Feb 26 03:17:43 PM PST 24 Feb 26 03:17:47 PM PST 24 48714569 ps
T1021 /workspace/coverage/default/37.keymgr_sideload_protect.694490578 Feb 26 03:17:43 PM PST 24 Feb 26 03:17:46 PM PST 24 475714047 ps
T1022 /workspace/coverage/default/49.keymgr_custom_cm.2772570336 Feb 26 03:18:26 PM PST 24 Feb 26 03:18:28 PM PST 24 44504817 ps
T1023 /workspace/coverage/default/12.keymgr_sideload_protect.1041276577 Feb 26 03:15:24 PM PST 24 Feb 26 03:15:40 PM PST 24 494232609 ps
T1024 /workspace/coverage/default/42.keymgr_sideload_kmac.1257781074 Feb 26 03:17:47 PM PST 24 Feb 26 03:17:52 PM PST 24 138026313 ps
T1025 /workspace/coverage/default/25.keymgr_alert_test.672105469 Feb 26 03:16:25 PM PST 24 Feb 26 03:16:26 PM PST 24 110496007 ps
T1026 /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.721582348 Feb 26 03:15:29 PM PST 24 Feb 26 03:15:34 PM PST 24 297720984 ps
T1027 /workspace/coverage/default/33.keymgr_sideload_aes.1323629624 Feb 26 03:17:06 PM PST 24 Feb 26 03:17:11 PM PST 24 215489511 ps
T1028 /workspace/coverage/default/49.keymgr_alert_test.3978025281 Feb 26 03:18:26 PM PST 24 Feb 26 03:18:27 PM PST 24 13776269 ps
T1029 /workspace/coverage/default/44.keymgr_sideload.4251498377 Feb 26 03:17:53 PM PST 24 Feb 26 03:17:57 PM PST 24 1020770092 ps
T1030 /workspace/coverage/default/2.keymgr_alert_test.1481566024 Feb 26 03:14:13 PM PST 24 Feb 26 03:14:15 PM PST 24 186108226 ps
T1031 /workspace/coverage/default/30.keymgr_sideload_aes.3442489695 Feb 26 03:16:56 PM PST 24 Feb 26 03:16:59 PM PST 24 46035888 ps
T1032 /workspace/coverage/default/27.keymgr_lc_disable.3013326551 Feb 26 03:16:47 PM PST 24 Feb 26 03:17:04 PM PST 24 568587869 ps
T1033 /workspace/coverage/default/40.keymgr_sideload_aes.4037237645 Feb 26 03:17:46 PM PST 24 Feb 26 03:17:52 PM PST 24 562526686 ps
T1034 /workspace/coverage/default/48.keymgr_direct_to_disabled.356644265 Feb 26 03:18:26 PM PST 24 Feb 26 03:18:29 PM PST 24 61372331 ps
T1035 /workspace/coverage/default/11.keymgr_alert_test.556070901 Feb 26 03:15:18 PM PST 24 Feb 26 03:15:19 PM PST 24 12970552 ps
T1036 /workspace/coverage/default/21.keymgr_lc_disable.543700018 Feb 26 03:16:14 PM PST 24 Feb 26 03:16:17 PM PST 24 170779514 ps
T1037 /workspace/coverage/default/49.keymgr_random.3340110112 Feb 26 03:18:25 PM PST 24 Feb 26 03:19:32 PM PST 24 2021816788 ps
T1038 /workspace/coverage/default/21.keymgr_sideload_aes.993023145 Feb 26 03:16:19 PM PST 24 Feb 26 03:16:51 PM PST 24 3206466883 ps
T1039 /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2401574850 Feb 26 03:18:03 PM PST 24 Feb 26 03:18:06 PM PST 24 96667247 ps
T1040 /workspace/coverage/default/8.keymgr_sideload_aes.98008846 Feb 26 03:15:07 PM PST 24 Feb 26 03:15:11 PM PST 24 89067583 ps
T1041 /workspace/coverage/default/45.keymgr_sideload_aes.3418736172 Feb 26 03:18:00 PM PST 24 Feb 26 03:18:58 PM PST 24 5170530499 ps
T1042 /workspace/coverage/default/7.keymgr_sideload_otbn.2170309911 Feb 26 03:14:48 PM PST 24 Feb 26 03:14:53 PM PST 24 131204270 ps
T1043 /workspace/coverage/default/24.keymgr_sideload_protect.1760780746 Feb 26 03:16:21 PM PST 24 Feb 26 03:16:25 PM PST 24 149742707 ps
T1044 /workspace/coverage/default/39.keymgr_sideload_kmac.3014010610 Feb 26 03:17:39 PM PST 24 Feb 26 03:17:43 PM PST 24 56650635 ps
T1045 /workspace/coverage/default/22.keymgr_sideload_kmac.280379926 Feb 26 03:16:29 PM PST 24 Feb 26 03:16:32 PM PST 24 58046450 ps
T1046 /workspace/coverage/default/3.keymgr_smoke.3383217387 Feb 26 03:14:10 PM PST 24 Feb 26 03:14:33 PM PST 24 1277418511 ps
T1047 /workspace/coverage/default/14.keymgr_custom_cm.3218499742 Feb 26 03:15:31 PM PST 24 Feb 26 03:15:37 PM PST 24 217341121 ps
T409 /workspace/coverage/default/42.keymgr_cfg_regwen.17272314 Feb 26 03:17:44 PM PST 24 Feb 26 03:17:49 PM PST 24 109456046 ps
T1048 /workspace/coverage/default/4.keymgr_alert_test.1607371336 Feb 26 03:14:28 PM PST 24 Feb 26 03:14:29 PM PST 24 12747134 ps
T1049 /workspace/coverage/default/43.keymgr_stress_all.1494658271 Feb 26 03:17:56 PM PST 24 Feb 26 03:18:26 PM PST 24 849165789 ps
T1050 /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3577926457 Feb 26 03:18:25 PM PST 24 Feb 26 03:18:27 PM PST 24 44063502 ps
T1051 /workspace/coverage/default/13.keymgr_sideload_protect.845649425 Feb 26 03:15:27 PM PST 24 Feb 26 03:15:31 PM PST 24 155393849 ps
T1052 /workspace/coverage/default/41.keymgr_smoke.2357790878 Feb 26 03:17:42 PM PST 24 Feb 26 03:17:46 PM PST 24 56800952 ps
T1053 /workspace/coverage/default/22.keymgr_sideload_otbn.1140297013 Feb 26 03:16:28 PM PST 24 Feb 26 03:16:36 PM PST 24 241449221 ps
T1054 /workspace/coverage/default/3.keymgr_sideload_kmac.718344025 Feb 26 03:14:14 PM PST 24 Feb 26 03:14:18 PM PST 24 290072013 ps
T1055 /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1390694233 Feb 26 03:17:28 PM PST 24 Feb 26 03:17:31 PM PST 24 159652469 ps
T1056 /workspace/coverage/default/26.keymgr_kmac_rsp_err.1313395990 Feb 26 03:16:32 PM PST 24 Feb 26 03:16:36 PM PST 24 99050000 ps
T1057 /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1337124526 Feb 26 03:14:40 PM PST 24 Feb 26 03:15:23 PM PST 24 20005196099 ps
T1058 /workspace/coverage/default/38.keymgr_sideload_otbn.2516088027 Feb 26 03:17:37 PM PST 24 Feb 26 03:17:49 PM PST 24 897704474 ps
T1059 /workspace/coverage/default/41.keymgr_direct_to_disabled.3517304449 Feb 26 03:17:42 PM PST 24 Feb 26 03:17:45 PM PST 24 67129195 ps
T274 /workspace/coverage/default/24.keymgr_kmac_rsp_err.3528437149 Feb 26 03:16:43 PM PST 24 Feb 26 03:16:46 PM PST 24 56195430 ps
T1060 /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1346951767 Feb 26 03:16:57 PM PST 24 Feb 26 03:17:00 PM PST 24 91642883 ps
T1061 /workspace/coverage/default/44.keymgr_sideload_aes.206513405 Feb 26 03:17:55 PM PST 24 Feb 26 03:18:01 PM PST 24 1264142034 ps
T1062 /workspace/coverage/default/22.keymgr_random.3328752497 Feb 26 03:16:29 PM PST 24 Feb 26 03:16:34 PM PST 24 84356961 ps
T1063 /workspace/coverage/default/49.keymgr_stress_all.2897293707 Feb 26 03:18:31 PM PST 24 Feb 26 03:18:39 PM PST 24 490296475 ps
T49 /workspace/coverage/default/28.keymgr_lc_disable.237143021 Feb 26 03:16:52 PM PST 24 Feb 26 03:16:57 PM PST 24 106537933 ps
T1064 /workspace/coverage/default/16.keymgr_sideload_otbn.3377055859 Feb 26 03:15:47 PM PST 24 Feb 26 03:15:51 PM PST 24 327040156 ps
T1065 /workspace/coverage/default/16.keymgr_direct_to_disabled.76602934 Feb 26 03:15:40 PM PST 24 Feb 26 03:15:43 PM PST 24 60263668 ps
T1066 /workspace/coverage/default/48.keymgr_alert_test.3495837589 Feb 26 03:18:21 PM PST 24 Feb 26 03:18:22 PM PST 24 339704561 ps
T1067 /workspace/coverage/default/21.keymgr_sw_invalid_input.295575081 Feb 26 03:16:15 PM PST 24 Feb 26 03:16:19 PM PST 24 88595318 ps
T1068 /workspace/coverage/default/26.keymgr_random.531194203 Feb 26 03:16:34 PM PST 24 Feb 26 03:16:45 PM PST 24 533122660 ps
T1069 /workspace/coverage/default/42.keymgr_sideload_aes.2292903900 Feb 26 03:17:45 PM PST 24 Feb 26 03:17:52 PM PST 24 504156075 ps
T1070 /workspace/coverage/default/44.keymgr_sw_invalid_input.603254236 Feb 26 03:17:57 PM PST 24 Feb 26 03:18:04 PM PST 24 685657742 ps
T1071 /workspace/coverage/default/36.keymgr_custom_cm.3331885717 Feb 26 03:17:36 PM PST 24 Feb 26 03:17:44 PM PST 24 194725234 ps

Test location /workspace/coverage/default/40.keymgr_stress_all.2808316966
Short name T18
Test name
Test status
Simulation time 382244649 ps
CPU time 19.44 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:18:04 PM PST 24
Peak memory 216456 kb
Host smart-d3d1099b-30c4-40fa-b518-bb56c6da41be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808316966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2808316966
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2169630832
Short name T57
Test name
Test status
Simulation time 1646904248 ps
CPU time 43.16 seconds
Started Feb 26 03:17:25 PM PST 24
Finished Feb 26 03:18:09 PM PST 24
Peak memory 222352 kb
Host smart-918c8497-97ed-4bdc-8018-6935060a8076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169630832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2169630832
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3165888061
Short name T6
Test name
Test status
Simulation time 2232733760 ps
CPU time 11.63 seconds
Started Feb 26 03:14:09 PM PST 24
Finished Feb 26 03:14:21 PM PST 24
Peak memory 234580 kb
Host smart-8d8c1101-fff4-40de-ae83-259b04969334
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165888061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3165888061
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2155933613
Short name T13
Test name
Test status
Simulation time 191800506 ps
CPU time 6.26 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 222504 kb
Host smart-98cc567b-fc74-480b-8567-1d44027b5aa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155933613 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2155933613
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2274474477
Short name T54
Test name
Test status
Simulation time 5952893846 ps
CPU time 49.05 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:18:00 PM PST 24
Peak memory 222528 kb
Host smart-1aa3b0fb-e67c-49f2-96c7-266836388378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274474477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2274474477
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2062344589
Short name T105
Test name
Test status
Simulation time 626422647 ps
CPU time 6.86 seconds
Started Feb 26 12:52:54 PM PST 24
Finished Feb 26 12:53:02 PM PST 24
Peak memory 213808 kb
Host smart-90226f8d-2a53-4e4b-a070-e2cb697f06ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062344589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2062344589
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4212222899
Short name T77
Test name
Test status
Simulation time 735243624 ps
CPU time 20.86 seconds
Started Feb 26 03:17:32 PM PST 24
Finished Feb 26 03:17:53 PM PST 24
Peak memory 215500 kb
Host smart-aa097e36-fcf6-40e6-b29e-c7213fc3dd5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212222899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4212222899
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2926531529
Short name T47
Test name
Test status
Simulation time 2042719687 ps
CPU time 55.02 seconds
Started Feb 26 03:16:10 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 222356 kb
Host smart-d2c3cd86-cc4b-4fc6-a354-dee0a49f822e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926531529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2926531529
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4230830026
Short name T244
Test name
Test status
Simulation time 1465117726 ps
CPU time 56.46 seconds
Started Feb 26 03:18:02 PM PST 24
Finished Feb 26 03:18:59 PM PST 24
Peak memory 222448 kb
Host smart-76254a1d-f269-4e56-b219-ce64a65febea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230830026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4230830026
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3226810037
Short name T8
Test name
Test status
Simulation time 278612384 ps
CPU time 5.61 seconds
Started Feb 26 03:18:02 PM PST 24
Finished Feb 26 03:18:08 PM PST 24
Peak memory 222744 kb
Host smart-c17d4107-769f-48f1-82b5-12ef9e0ba098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226810037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3226810037
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3552340851
Short name T320
Test name
Test status
Simulation time 1642331850 ps
CPU time 85.27 seconds
Started Feb 26 03:17:21 PM PST 24
Finished Feb 26 03:18:47 PM PST 24
Peak memory 214316 kb
Host smart-d5c559ea-3058-481b-86b2-0caeae8d2168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552340851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3552340851
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1493419678
Short name T100
Test name
Test status
Simulation time 185440621 ps
CPU time 7.82 seconds
Started Feb 26 12:52:51 PM PST 24
Finished Feb 26 12:53:00 PM PST 24
Peak memory 219888 kb
Host smart-fa96db99-432d-4c23-a843-b8741009458a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493419678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1493419678
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3057887063
Short name T80
Test name
Test status
Simulation time 495979509 ps
CPU time 3.36 seconds
Started Feb 26 03:17:32 PM PST 24
Finished Feb 26 03:17:36 PM PST 24
Peak memory 209248 kb
Host smart-a64de348-4c72-4e01-bfb1-8507c92e9eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057887063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3057887063
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4028936069
Short name T86
Test name
Test status
Simulation time 797130152 ps
CPU time 6.74 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:44 PM PST 24
Peak memory 214228 kb
Host smart-d43ee2da-1d52-4abc-bd7d-0de9a9745043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028936069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4028936069
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1256469971
Short name T115
Test name
Test status
Simulation time 148537721 ps
CPU time 8.26 seconds
Started Feb 26 03:16:55 PM PST 24
Finished Feb 26 03:17:03 PM PST 24
Peak memory 215344 kb
Host smart-ac527068-cf8b-4af1-b832-5d86eb4a52e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256469971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1256469971
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2516039116
Short name T392
Test name
Test status
Simulation time 7690760075 ps
CPU time 105.11 seconds
Started Feb 26 03:17:02 PM PST 24
Finished Feb 26 03:18:47 PM PST 24
Peak memory 222304 kb
Host smart-05ee8acb-ca14-4678-8e3f-f2ec7a641059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516039116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2516039116
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2387067329
Short name T174
Test name
Test status
Simulation time 343457104 ps
CPU time 10.47 seconds
Started Feb 26 03:16:16 PM PST 24
Finished Feb 26 03:16:27 PM PST 24
Peak memory 215184 kb
Host smart-8c9dd649-2b44-4f58-9586-0ebc6c172629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387067329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2387067329
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.916430636
Short name T19
Test name
Test status
Simulation time 260487641 ps
CPU time 4.16 seconds
Started Feb 26 03:14:23 PM PST 24
Finished Feb 26 03:14:29 PM PST 24
Peak memory 214308 kb
Host smart-8b2a0684-66e3-49e4-aaac-1e7fde83a3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916430636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.916430636
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.307764580
Short name T142
Test name
Test status
Simulation time 343792244 ps
CPU time 8.72 seconds
Started Feb 26 12:52:55 PM PST 24
Finished Feb 26 12:53:04 PM PST 24
Peak memory 213424 kb
Host smart-1e9a5319-5212-4c88-aad4-8b155734853b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307764580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
307764580
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2325459057
Short name T224
Test name
Test status
Simulation time 377099755 ps
CPU time 10.53 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:14:10 PM PST 24
Peak memory 214268 kb
Host smart-4ced9df0-6c55-4e63-8e52-010307df4bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325459057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2325459057
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2938568862
Short name T662
Test name
Test status
Simulation time 211979512 ps
CPU time 5.12 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:33 PM PST 24
Peak memory 207976 kb
Host smart-42ac7f8d-fd9b-460a-8344-25bb1c21b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938568862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2938568862
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.217312506
Short name T27
Test name
Test status
Simulation time 528661598 ps
CPU time 4.93 seconds
Started Feb 26 03:14:50 PM PST 24
Finished Feb 26 03:14:56 PM PST 24
Peak memory 214332 kb
Host smart-25195288-f023-472b-9f94-c1c49f7158a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217312506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.217312506
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1541124662
Short name T140
Test name
Test status
Simulation time 131732806 ps
CPU time 3.01 seconds
Started Feb 26 12:53:16 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 213552 kb
Host smart-d44a23b8-0f04-4a38-8552-8b31ea08daef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541124662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1541124662
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1944516513
Short name T63
Test name
Test status
Simulation time 5721521265 ps
CPU time 74.98 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 216064 kb
Host smart-c2723dd6-d48b-46df-be30-2cddb1c78187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944516513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1944516513
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3694092353
Short name T134
Test name
Test status
Simulation time 610554322 ps
CPU time 4.84 seconds
Started Feb 26 03:15:27 PM PST 24
Finished Feb 26 03:15:32 PM PST 24
Peak memory 222572 kb
Host smart-394c4ba9-ba90-4fac-973a-2629c79398d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694092353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3694092353
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.318356768
Short name T232
Test name
Test status
Simulation time 988602035 ps
CPU time 36.98 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 214188 kb
Host smart-dfd731bf-603d-474d-b0f0-5722b44cbd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318356768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.318356768
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.779884373
Short name T15
Test name
Test status
Simulation time 20972563 ps
CPU time 0.73 seconds
Started Feb 26 03:14:38 PM PST 24
Finished Feb 26 03:14:38 PM PST 24
Peak memory 205892 kb
Host smart-add1ccba-0740-4943-a7ed-bfd5c946f597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779884373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.779884373
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.4140519372
Short name T149
Test name
Test status
Simulation time 109441319 ps
CPU time 6.12 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:20 PM PST 24
Peak memory 208776 kb
Host smart-e3220a7b-487f-4528-8770-718c9c07cafa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140519372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.4140519372
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4019078155
Short name T68
Test name
Test status
Simulation time 977982740 ps
CPU time 27 seconds
Started Feb 26 03:15:42 PM PST 24
Finished Feb 26 03:16:10 PM PST 24
Peak memory 216096 kb
Host smart-ea0ca4dd-6575-4b8c-b30e-39ecd5c88c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019078155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4019078155
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.767248081
Short name T317
Test name
Test status
Simulation time 8394481357 ps
CPU time 76.23 seconds
Started Feb 26 03:14:06 PM PST 24
Finished Feb 26 03:15:22 PM PST 24
Peak memory 214384 kb
Host smart-666cdcdc-5085-46d3-acb6-ef9f7b1e0db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767248081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.767248081
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2937026116
Short name T242
Test name
Test status
Simulation time 2364103335 ps
CPU time 24.74 seconds
Started Feb 26 03:16:27 PM PST 24
Finished Feb 26 03:16:52 PM PST 24
Peak memory 215188 kb
Host smart-2916b147-c49f-477c-ae6b-2a4c539db076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937026116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2937026116
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2790259695
Short name T359
Test name
Test status
Simulation time 92632572 ps
CPU time 4.79 seconds
Started Feb 26 03:17:58 PM PST 24
Finished Feb 26 03:18:03 PM PST 24
Peak memory 214376 kb
Host smart-8fd50d49-c915-4b13-90ca-386e5f74247b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790259695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2790259695
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1731582414
Short name T32
Test name
Test status
Simulation time 114911438 ps
CPU time 3.26 seconds
Started Feb 26 03:16:45 PM PST 24
Finished Feb 26 03:16:49 PM PST 24
Peak memory 214648 kb
Host smart-47dc1071-ddc5-45d6-aabc-c2d4a8391911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731582414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1731582414
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2499897215
Short name T39
Test name
Test status
Simulation time 446730544 ps
CPU time 10.45 seconds
Started Feb 26 03:15:29 PM PST 24
Finished Feb 26 03:15:39 PM PST 24
Peak memory 222488 kb
Host smart-a01588ac-2ea5-4baf-9905-c1ff900db2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499897215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2499897215
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3053933546
Short name T217
Test name
Test status
Simulation time 2182910396 ps
CPU time 30.76 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:30 PM PST 24
Peak memory 216480 kb
Host smart-a05a7bcd-2872-4273-9223-1ca53e345e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053933546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3053933546
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3404623355
Short name T282
Test name
Test status
Simulation time 260011422 ps
CPU time 14.02 seconds
Started Feb 26 03:16:10 PM PST 24
Finished Feb 26 03:16:24 PM PST 24
Peak memory 215428 kb
Host smart-1744fc21-be2b-4db2-8681-e5eb0773512b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404623355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3404623355
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1315356530
Short name T66
Test name
Test status
Simulation time 161926987 ps
CPU time 2.34 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 215604 kb
Host smart-a6994582-11d6-4a22-8bb6-3ff31756857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315356530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1315356530
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3486172448
Short name T390
Test name
Test status
Simulation time 400710173 ps
CPU time 16.8 seconds
Started Feb 26 03:15:35 PM PST 24
Finished Feb 26 03:15:52 PM PST 24
Peak memory 215248 kb
Host smart-97f7d67a-451b-49b8-b7f1-71ad270a171e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486172448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3486172448
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2018110425
Short name T5
Test name
Test status
Simulation time 832878813 ps
CPU time 16.23 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:58 PM PST 24
Peak memory 222440 kb
Host smart-f2f135d1-042c-4ed4-ae52-720d60d9c05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018110425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2018110425
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3403854673
Short name T136
Test name
Test status
Simulation time 310631993 ps
CPU time 3.98 seconds
Started Feb 26 03:16:03 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 217696 kb
Host smart-155adad0-e7d4-42a0-964c-daaaf016ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403854673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3403854673
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.416473853
Short name T289
Test name
Test status
Simulation time 235083644 ps
CPU time 8.22 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:16:56 PM PST 24
Peak memory 214212 kb
Host smart-df568789-e93d-4753-b560-26027efdd6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416473853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.416473853
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3480918999
Short name T272
Test name
Test status
Simulation time 73342876 ps
CPU time 4.81 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:49 PM PST 24
Peak memory 214356 kb
Host smart-c590eb97-fe16-40c7-8ef5-4f01d3f0894f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480918999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3480918999
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3107873729
Short name T133
Test name
Test status
Simulation time 390100193 ps
CPU time 4.3 seconds
Started Feb 26 03:14:13 PM PST 24
Finished Feb 26 03:14:17 PM PST 24
Peak memory 217052 kb
Host smart-6c7259b1-0da1-49c5-8112-fd5686b3a6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107873729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3107873729
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3013151398
Short name T129
Test name
Test status
Simulation time 1005596416 ps
CPU time 13.55 seconds
Started Feb 26 03:16:54 PM PST 24
Finished Feb 26 03:17:08 PM PST 24
Peak memory 218096 kb
Host smart-c4e346c4-8c86-4485-a253-041d8ffc52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013151398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3013151398
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.459769647
Short name T311
Test name
Test status
Simulation time 152276744 ps
CPU time 6.93 seconds
Started Feb 26 03:13:58 PM PST 24
Finished Feb 26 03:14:05 PM PST 24
Peak memory 222388 kb
Host smart-9d1d73fe-e07c-42f6-92aa-f472928db6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459769647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.459769647
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1167117453
Short name T72
Test name
Test status
Simulation time 1339377629 ps
CPU time 46.17 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 222516 kb
Host smart-f10881ed-44e8-43ba-805b-45975d7e1401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167117453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1167117453
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.75297675
Short name T240
Test name
Test status
Simulation time 312014097 ps
CPU time 12.37 seconds
Started Feb 26 03:14:50 PM PST 24
Finished Feb 26 03:15:04 PM PST 24
Peak memory 214204 kb
Host smart-96b353da-ba8f-4a4f-8384-23fb703cbd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75297675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.75297675
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2016778055
Short name T108
Test name
Test status
Simulation time 216310829 ps
CPU time 6.35 seconds
Started Feb 26 12:53:03 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 213724 kb
Host smart-7f38c9e3-9058-4efb-9fce-98e9c1822ee4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016778055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2016778055
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.481717941
Short name T141
Test name
Test status
Simulation time 196477108 ps
CPU time 7.27 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:23 PM PST 24
Peak memory 213512 kb
Host smart-9752314f-9d1a-4df1-a4aa-fbb8147f5723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481717941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.481717941
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3987631904
Short name T152
Test name
Test status
Simulation time 747521695 ps
CPU time 5.16 seconds
Started Feb 26 12:53:08 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 208968 kb
Host smart-df9d5fdd-b9a2-412e-aa13-45de85f649fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987631904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3987631904
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1190082649
Short name T22
Test name
Test status
Simulation time 1161863985 ps
CPU time 9.81 seconds
Started Feb 26 03:15:10 PM PST 24
Finished Feb 26 03:15:20 PM PST 24
Peak memory 214256 kb
Host smart-f9287c2c-bc08-4da0-9183-5ad637806ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190082649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1190082649
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.979330437
Short name T371
Test name
Test status
Simulation time 128019404 ps
CPU time 3.33 seconds
Started Feb 26 03:16:31 PM PST 24
Finished Feb 26 03:16:35 PM PST 24
Peak memory 219136 kb
Host smart-535ba852-0e50-41dd-9ec4-261140922f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979330437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.979330437
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3885955163
Short name T252
Test name
Test status
Simulation time 225599057 ps
CPU time 12.37 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:55 PM PST 24
Peak memory 215560 kb
Host smart-d58527c6-9cc7-40b6-88b8-d4e2f4cf1b5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885955163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3885955163
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.570188982
Short name T236
Test name
Test status
Simulation time 390496506 ps
CPU time 4.75 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:31 PM PST 24
Peak memory 214124 kb
Host smart-5855f196-2365-4097-87b4-a6bb0917fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570188982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.570188982
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1478933801
Short name T214
Test name
Test status
Simulation time 20494050920 ps
CPU time 133.35 seconds
Started Feb 26 03:14:50 PM PST 24
Finished Feb 26 03:17:05 PM PST 24
Peak memory 222440 kb
Host smart-766f0006-55be-4d58-984e-d85d39c261d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478933801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1478933801
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2337442586
Short name T132
Test name
Test status
Simulation time 928778635 ps
CPU time 2.57 seconds
Started Feb 26 03:15:17 PM PST 24
Finished Feb 26 03:15:20 PM PST 24
Peak memory 222812 kb
Host smart-afa6ab99-6c26-45cc-a46a-e3d0d6ab2ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337442586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2337442586
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3920505020
Short name T131
Test name
Test status
Simulation time 404855825 ps
CPU time 3.87 seconds
Started Feb 26 03:15:43 PM PST 24
Finished Feb 26 03:15:47 PM PST 24
Peak memory 217088 kb
Host smart-007a45c6-20c8-4a27-bd9e-a90cc59c3ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920505020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3920505020
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1270349451
Short name T137
Test name
Test status
Simulation time 126196877 ps
CPU time 4.13 seconds
Started Feb 26 03:14:39 PM PST 24
Finished Feb 26 03:14:44 PM PST 24
Peak memory 218248 kb
Host smart-e55e7887-4b93-473d-8499-efd058518188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270349451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1270349451
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3872850546
Short name T215
Test name
Test status
Simulation time 1380049309 ps
CPU time 28.53 seconds
Started Feb 26 03:13:52 PM PST 24
Finished Feb 26 03:14:21 PM PST 24
Peak memory 222480 kb
Host smart-8d7314ef-cacb-42ec-9d32-4b6b98833927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872850546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3872850546
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3815708514
Short name T24
Test name
Test status
Simulation time 370683882 ps
CPU time 8.05 seconds
Started Feb 26 03:14:01 PM PST 24
Finished Feb 26 03:14:09 PM PST 24
Peak memory 221564 kb
Host smart-5b49061a-764e-44ff-a354-7ec636c2cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815708514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3815708514
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_random.3373243517
Short name T338
Test name
Test status
Simulation time 192804849 ps
CPU time 5.99 seconds
Started Feb 26 03:13:55 PM PST 24
Finished Feb 26 03:14:01 PM PST 24
Peak memory 209952 kb
Host smart-e5738825-918d-4656-adf8-aaa0c0e70752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373243517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3373243517
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1404881306
Short name T208
Test name
Test status
Simulation time 3583540156 ps
CPU time 39.07 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:48 PM PST 24
Peak memory 215540 kb
Host smart-f764aa43-b413-45f1-a223-71062306fb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404881306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1404881306
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3898981859
Short name T410
Test name
Test status
Simulation time 34851736 ps
CPU time 2.88 seconds
Started Feb 26 03:15:27 PM PST 24
Finished Feb 26 03:15:30 PM PST 24
Peak memory 214404 kb
Host smart-675fc704-5db5-4647-a5ac-8a1e2609905f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898981859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3898981859
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2894416599
Short name T79
Test name
Test status
Simulation time 64383860 ps
CPU time 3.17 seconds
Started Feb 26 03:15:42 PM PST 24
Finished Feb 26 03:15:45 PM PST 24
Peak memory 208744 kb
Host smart-0386ceba-340b-490f-9624-74e771c89e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894416599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2894416599
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2259825466
Short name T330
Test name
Test status
Simulation time 117346861 ps
CPU time 4.88 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:05 PM PST 24
Peak memory 214256 kb
Host smart-7d7a7b7e-0d96-48f0-80b1-9f5140e5fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259825466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2259825466
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.628734333
Short name T934
Test name
Test status
Simulation time 393240278 ps
CPU time 6.28 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:21 PM PST 24
Peak memory 214320 kb
Host smart-49b5496e-3d77-45b4-aad7-f251b36786ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628734333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.628734333
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.510409215
Short name T298
Test name
Test status
Simulation time 283256275 ps
CPU time 11.28 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 220112 kb
Host smart-2f7a01cf-f4f9-4d0d-8d86-779ce67b9f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510409215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.510409215
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2979754381
Short name T314
Test name
Test status
Simulation time 501701410 ps
CPU time 13.47 seconds
Started Feb 26 03:14:44 PM PST 24
Finished Feb 26 03:14:58 PM PST 24
Peak memory 215100 kb
Host smart-29cfda24-b912-471e-839a-73d76af95fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979754381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2979754381
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.958167720
Short name T147
Test name
Test status
Simulation time 230352802 ps
CPU time 2.01 seconds
Started Feb 26 12:53:03 PM PST 24
Finished Feb 26 12:53:05 PM PST 24
Peak memory 215660 kb
Host smart-e09ecd99-7c4f-432e-ab02-4d18c77ac1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958167720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.958167720
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2300493477
Short name T150
Test name
Test status
Simulation time 225427596 ps
CPU time 3.65 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 213768 kb
Host smart-5ef3dbe6-834b-473f-8d20-b8a8c0a85ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300493477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2300493477
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4251704082
Short name T151
Test name
Test status
Simulation time 638795493 ps
CPU time 7.35 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:30 PM PST 24
Peak memory 208580 kb
Host smart-15ef111b-4f6f-4a0f-8e4d-8bb37c8b7f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251704082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4251704082
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2497118717
Short name T480
Test name
Test status
Simulation time 56726899 ps
CPU time 1.72 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:02 PM PST 24
Peak memory 213632 kb
Host smart-8119baa4-94d7-4b2e-a7e5-79c4695b53f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497118717 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2497118717
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.785814961
Short name T1018
Test name
Test status
Simulation time 69862262 ps
CPU time 3.27 seconds
Started Feb 26 03:13:49 PM PST 24
Finished Feb 26 03:13:52 PM PST 24
Peak memory 209936 kb
Host smart-1081ed34-58b0-4cf9-942c-03beb78619c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785814961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.785814961
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2968624909
Short name T551
Test name
Test status
Simulation time 161283539 ps
CPU time 1.73 seconds
Started Feb 26 03:14:01 PM PST 24
Finished Feb 26 03:14:03 PM PST 24
Peak memory 209912 kb
Host smart-f3e50d37-6732-429e-a9ed-18e9354a5b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968624909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2968624909
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.624673418
Short name T203
Test name
Test status
Simulation time 254399750 ps
CPU time 3.67 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:11 PM PST 24
Peak memory 209400 kb
Host smart-61eeebde-997a-4a79-8935-dfc90861efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624673418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.624673418
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2905404055
Short name T926
Test name
Test status
Simulation time 157803295 ps
CPU time 5.78 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 208660 kb
Host smart-4ebbcb28-5c6e-4547-b340-a564bd50b40f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905404055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2905404055
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.960049234
Short name T177
Test name
Test status
Simulation time 4199871500 ps
CPU time 30.7 seconds
Started Feb 26 03:15:12 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 209572 kb
Host smart-6b6e7e61-d4a9-4a7d-b756-b119732b31eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960049234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.960049234
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2691222240
Short name T627
Test name
Test status
Simulation time 407384141 ps
CPU time 11.09 seconds
Started Feb 26 03:15:24 PM PST 24
Finished Feb 26 03:15:35 PM PST 24
Peak memory 211652 kb
Host smart-445fb1ed-07f5-4f3e-926c-f03bdbb3b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691222240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2691222240
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1885607980
Short name T180
Test name
Test status
Simulation time 718654629 ps
CPU time 10.51 seconds
Started Feb 26 03:15:32 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 214276 kb
Host smart-3a441ae3-023f-4705-9d10-8916464f67c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885607980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1885607980
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4197655620
Short name T199
Test name
Test status
Simulation time 28262273 ps
CPU time 1.95 seconds
Started Feb 26 03:15:53 PM PST 24
Finished Feb 26 03:15:55 PM PST 24
Peak memory 218748 kb
Host smart-306e3bde-6d42-4870-b364-18cac083ca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197655620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4197655620
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2092129107
Short name T241
Test name
Test status
Simulation time 266911909 ps
CPU time 9.17 seconds
Started Feb 26 03:15:58 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 219336 kb
Host smart-b6435ab1-f2ea-4f3b-9528-2c8a5705df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092129107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2092129107
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3321730422
Short name T290
Test name
Test status
Simulation time 403611922 ps
CPU time 7.29 seconds
Started Feb 26 03:15:54 PM PST 24
Finished Feb 26 03:16:01 PM PST 24
Peak memory 210508 kb
Host smart-b896ee40-9001-4668-a5df-5cdad449e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321730422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3321730422
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1266169071
Short name T408
Test name
Test status
Simulation time 843815452 ps
CPU time 42.6 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 215040 kb
Host smart-b3c55228-3ec9-4f27-8300-b0860e08b595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266169071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1266169071
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3566379661
Short name T194
Test name
Test status
Simulation time 255723778 ps
CPU time 7.28 seconds
Started Feb 26 03:16:42 PM PST 24
Finished Feb 26 03:16:50 PM PST 24
Peak memory 220828 kb
Host smart-fed7382d-0a38-49cd-9429-ce3df41d91ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566379661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3566379661
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4051622067
Short name T277
Test name
Test status
Simulation time 65972997 ps
CPU time 2.72 seconds
Started Feb 26 03:16:45 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 210512 kb
Host smart-4eae280e-fac2-46f1-b33b-24e7e4597836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051622067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4051622067
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2781608646
Short name T301
Test name
Test status
Simulation time 44609963 ps
CPU time 3.11 seconds
Started Feb 26 03:17:16 PM PST 24
Finished Feb 26 03:17:19 PM PST 24
Peak memory 219296 kb
Host smart-b34fa78c-12fb-46f7-9d06-d5b1063bfa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781608646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2781608646
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3147256158
Short name T234
Test name
Test status
Simulation time 303419083 ps
CPU time 10.06 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:53 PM PST 24
Peak memory 214168 kb
Host smart-15356832-1d72-4165-9854-95e79a2b1d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147256158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3147256158
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2430937076
Short name T135
Test name
Test status
Simulation time 70784245 ps
CPU time 3.5 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 217696 kb
Host smart-66fd924b-1fbf-45b5-ae36-5b7bd2adcbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430937076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2430937076
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.378988262
Short name T488
Test name
Test status
Simulation time 262440955 ps
CPU time 7.26 seconds
Started Feb 26 12:52:54 PM PST 24
Finished Feb 26 12:53:02 PM PST 24
Peak memory 205216 kb
Host smart-c35db53d-50b2-4d56-a904-c8c9630bd148
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378988262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.378988262
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4245418051
Short name T427
Test name
Test status
Simulation time 566013231 ps
CPU time 7.59 seconds
Started Feb 26 12:52:57 PM PST 24
Finished Feb 26 12:53:04 PM PST 24
Peak memory 205080 kb
Host smart-2c0cb404-32f5-4543-b2a8-94b2e9007a5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245418051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
245418051
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2019493572
Short name T424
Test name
Test status
Simulation time 57604949 ps
CPU time 1.41 seconds
Started Feb 26 12:52:54 PM PST 24
Finished Feb 26 12:52:56 PM PST 24
Peak memory 205176 kb
Host smart-80b54321-12c9-40c8-85de-a16781f89858
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019493572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
019493572
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2337035919
Short name T486
Test name
Test status
Simulation time 25315819 ps
CPU time 1.13 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:07 PM PST 24
Peak memory 205280 kb
Host smart-1473c84f-b1b1-4f15-8215-24548048563b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337035919 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2337035919
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3393879434
Short name T117
Test name
Test status
Simulation time 125713795 ps
CPU time 1.2 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 205024 kb
Host smart-3b91627b-3bc1-43b2-9c0f-c6dceb2c367e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393879434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3393879434
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3742695114
Short name T491
Test name
Test status
Simulation time 46159332 ps
CPU time 0.73 seconds
Started Feb 26 12:52:56 PM PST 24
Finished Feb 26 12:52:56 PM PST 24
Peak memory 205104 kb
Host smart-cdbf5c3e-01b5-4817-94b0-01c8fd0f9611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742695114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3742695114
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.86885338
Short name T505
Test name
Test status
Simulation time 257190172 ps
CPU time 4.39 seconds
Started Feb 26 12:53:02 PM PST 24
Finished Feb 26 12:53:06 PM PST 24
Peak memory 213740 kb
Host smart-f4a0a0c2-524b-4843-8998-f278049fb566
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86885338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_
reg_errors.86885338
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1533017133
Short name T533
Test name
Test status
Simulation time 46606839 ps
CPU time 1.48 seconds
Started Feb 26 12:52:53 PM PST 24
Finished Feb 26 12:52:56 PM PST 24
Peak memory 214424 kb
Host smart-4be0be00-56e3-4e1d-a1bd-2f54bb3447b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533017133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1533017133
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4103044145
Short name T489
Test name
Test status
Simulation time 511825700 ps
CPU time 8.65 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:09 PM PST 24
Peak memory 205180 kb
Host smart-28356c79-c681-461b-bf64-2deeecd63722
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103044145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
103044145
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3559469973
Short name T495
Test name
Test status
Simulation time 64799871 ps
CPU time 0.92 seconds
Started Feb 26 12:52:51 PM PST 24
Finished Feb 26 12:52:53 PM PST 24
Peak memory 205136 kb
Host smart-52d72c45-ab73-4782-a091-2b1234311615
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559469973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
559469973
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2049020418
Short name T162
Test name
Test status
Simulation time 210734740 ps
CPU time 1.15 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:01 PM PST 24
Peak memory 204076 kb
Host smart-999c147f-b8b4-4cde-b736-8e7d3e691371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049020418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2049020418
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.297808537
Short name T123
Test name
Test status
Simulation time 42104982 ps
CPU time 0.71 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205116 kb
Host smart-c7021ce8-6d53-4094-b7eb-66ee213cafe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297808537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.297808537
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.516215366
Short name T487
Test name
Test status
Simulation time 516584411 ps
CPU time 2.1 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:03 PM PST 24
Peak memory 205268 kb
Host smart-6cf0d4ac-6950-4eb4-b6f1-7adfa5d86271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516215366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.516215366
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1138902057
Short name T450
Test name
Test status
Simulation time 1236302138 ps
CPU time 1.75 seconds
Started Feb 26 12:52:57 PM PST 24
Finished Feb 26 12:52:59 PM PST 24
Peak memory 213832 kb
Host smart-753a6514-447c-401a-9655-ff38cfdfdf48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138902057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1138902057
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2029750028
Short name T101
Test name
Test status
Simulation time 694272105 ps
CPU time 10.09 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 213972 kb
Host smart-dee06906-864d-40cc-9ba9-ca405b464330
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029750028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2029750028
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.774246325
Short name T526
Test name
Test status
Simulation time 30046893 ps
CPU time 1.42 seconds
Started Feb 26 12:53:08 PM PST 24
Finished Feb 26 12:53:11 PM PST 24
Peak memory 205336 kb
Host smart-d19ff1c4-7a6d-4a5e-81e3-8cf401725309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774246325 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.774246325
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3997677418
Short name T503
Test name
Test status
Simulation time 10914159 ps
CPU time 0.76 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 205312 kb
Host smart-14ad45c7-2b05-44eb-b9e9-b71d5d5979d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997677418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3997677418
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3039327217
Short name T441
Test name
Test status
Simulation time 1626513971 ps
CPU time 14.74 seconds
Started Feb 26 12:53:11 PM PST 24
Finished Feb 26 12:53:27 PM PST 24
Peak memory 213844 kb
Host smart-0ce65108-55da-4c46-a8d0-479b93ee00b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039327217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3039327217
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1663862516
Short name T511
Test name
Test status
Simulation time 192535823 ps
CPU time 2.41 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:12 PM PST 24
Peak memory 213544 kb
Host smart-ea519a84-5b45-4ea0-8a10-aebaa158a369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663862516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1663862516
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1284701682
Short name T423
Test name
Test status
Simulation time 333102068 ps
CPU time 1.38 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:16 PM PST 24
Peak memory 213620 kb
Host smart-ec8897ef-298f-4ca4-b302-403dc87ccff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284701682 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1284701682
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1675722629
Short name T451
Test name
Test status
Simulation time 10455163 ps
CPU time 0.9 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 205064 kb
Host smart-5f5b3565-03f9-4572-a6dc-48d5c28f5018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675722629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1675722629
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3443731979
Short name T490
Test name
Test status
Simulation time 9397416 ps
CPU time 0.72 seconds
Started Feb 26 12:53:16 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205132 kb
Host smart-b9687fb9-dfbe-4e73-932e-584c609233af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443731979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3443731979
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3316765421
Short name T456
Test name
Test status
Simulation time 369113149 ps
CPU time 3.56 seconds
Started Feb 26 12:53:10 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 213792 kb
Host smart-82ee7b3c-534e-4c52-8d4e-21ca15058646
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316765421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3316765421
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2690674514
Short name T459
Test name
Test status
Simulation time 3785647309 ps
CPU time 5.23 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 213892 kb
Host smart-d91d46af-48f6-4e00-98f8-e52d0b9d60c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690674514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2690674514
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.181962357
Short name T112
Test name
Test status
Simulation time 216805596 ps
CPU time 1.66 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 213580 kb
Host smart-33658078-a655-41b5-b425-76ca82becddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181962357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.181962357
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.875737795
Short name T537
Test name
Test status
Simulation time 117593645 ps
CPU time 2.42 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:12 PM PST 24
Peak memory 213688 kb
Host smart-c62e49b8-1c3f-4c01-b039-4a8814a98fef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875737795 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.875737795
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2734974526
Short name T125
Test name
Test status
Simulation time 28366998 ps
CPU time 1.11 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:16 PM PST 24
Peak memory 205216 kb
Host smart-90b83fdf-cd40-43ba-a0f5-2125e7975137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734974526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2734974526
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2791296603
Short name T448
Test name
Test status
Simulation time 8109977 ps
CPU time 0.81 seconds
Started Feb 26 12:53:10 PM PST 24
Finished Feb 26 12:53:11 PM PST 24
Peak memory 205040 kb
Host smart-ac1aae7b-83a2-4e5f-bbff-a96b909fc214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791296603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2791296603
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1000109846
Short name T521
Test name
Test status
Simulation time 102614014 ps
CPU time 1.64 seconds
Started Feb 26 12:53:17 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 205220 kb
Host smart-9b7b6aee-befb-4751-a822-42501d3f6719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000109846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1000109846
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3181668596
Short name T483
Test name
Test status
Simulation time 737808079 ps
CPU time 3.47 seconds
Started Feb 26 12:53:16 PM PST 24
Finished Feb 26 12:53:20 PM PST 24
Peak memory 213824 kb
Host smart-4af30ac6-26dc-49af-8464-789c4d1ccc8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181668596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3181668596
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2088999466
Short name T460
Test name
Test status
Simulation time 771456242 ps
CPU time 8.39 seconds
Started Feb 26 12:53:17 PM PST 24
Finished Feb 26 12:53:26 PM PST 24
Peak memory 213752 kb
Host smart-330a60ca-ab6f-44da-8d6e-492212e8d597
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088999466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2088999466
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1201585109
Short name T103
Test name
Test status
Simulation time 96613180 ps
CPU time 1.57 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:11 PM PST 24
Peak memory 213492 kb
Host smart-8da943ec-acef-496b-a648-5988405d708b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201585109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1201585109
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.431914786
Short name T494
Test name
Test status
Simulation time 86392748 ps
CPU time 1.09 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:15 PM PST 24
Peak memory 205372 kb
Host smart-eb9a5004-36db-4b85-88a8-4acd2e6315a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431914786 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.431914786
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.482601898
Short name T535
Test name
Test status
Simulation time 39486571 ps
CPU time 0.81 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:15 PM PST 24
Peak memory 205056 kb
Host smart-ae1944e7-1743-4dfd-b479-22055405e9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482601898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.482601898
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3957727599
Short name T501
Test name
Test status
Simulation time 47636622 ps
CPU time 1.47 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:16 PM PST 24
Peak memory 205216 kb
Host smart-a021ad9b-f05d-47ee-b4b3-5994d617a79d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957727599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3957727599
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.724605928
Short name T522
Test name
Test status
Simulation time 196160708 ps
CPU time 4.47 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 213792 kb
Host smart-555f5764-7171-443a-8d3c-3a0d0ab9d0a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724605928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.724605928
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4100949061
Short name T437
Test name
Test status
Simulation time 714295934 ps
CPU time 6.83 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:21 PM PST 24
Peak memory 219924 kb
Host smart-3f3f2268-5d19-4e6c-b1d6-c0ddb1763045
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100949061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4100949061
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.283501492
Short name T425
Test name
Test status
Simulation time 61013542 ps
CPU time 1.23 seconds
Started Feb 26 12:53:18 PM PST 24
Finished Feb 26 12:53:20 PM PST 24
Peak memory 213648 kb
Host smart-04534150-82a1-4388-9ad5-16724cf48a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283501492 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.283501492
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3815558214
Short name T473
Test name
Test status
Simulation time 111961366 ps
CPU time 1.36 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:24 PM PST 24
Peak memory 205288 kb
Host smart-ff175918-79b0-4f0a-92c9-c5042a2217c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815558214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3815558214
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1148471835
Short name T518
Test name
Test status
Simulation time 12030535 ps
CPU time 0.83 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205116 kb
Host smart-9ef161e5-6384-469c-837c-931fa77f6d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148471835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1148471835
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4279135965
Short name T455
Test name
Test status
Simulation time 89369843 ps
CPU time 2.74 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:25 PM PST 24
Peak memory 213440 kb
Host smart-4ad6bf35-8ef5-44e1-a9bd-5f4e2dd869d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279135965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4279135965
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1728184178
Short name T109
Test name
Test status
Simulation time 377259641 ps
CPU time 7.45 seconds
Started Feb 26 12:53:17 PM PST 24
Finished Feb 26 12:53:25 PM PST 24
Peak memory 213652 kb
Host smart-888c8bab-72eb-41b1-ba80-88d5ea87adad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728184178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1728184178
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2683823224
Short name T525
Test name
Test status
Simulation time 812875298 ps
CPU time 5.41 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 213776 kb
Host smart-c18525e0-97d5-4bb7-af9d-697e9fbf6ce4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683823224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2683823224
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2413378513
Short name T139
Test name
Test status
Simulation time 299123654 ps
CPU time 2.35 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:15 PM PST 24
Peak memory 213496 kb
Host smart-f63ba5d4-7326-4109-a56a-d271343c464e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413378513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2413378513
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.609839645
Short name T166
Test name
Test status
Simulation time 71454635 ps
CPU time 1.28 seconds
Started Feb 26 12:53:21 PM PST 24
Finished Feb 26 12:53:22 PM PST 24
Peak memory 205432 kb
Host smart-4a3bdfaf-a532-4abe-bc5c-9007642b4504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609839645 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.609839645
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1875477285
Short name T118
Test name
Test status
Simulation time 39226354 ps
CPU time 0.9 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205168 kb
Host smart-c0ade4e1-c5b7-4dbd-b7fd-12a9ea70fb0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875477285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1875477285
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.286283928
Short name T124
Test name
Test status
Simulation time 10498382 ps
CPU time 0.69 seconds
Started Feb 26 12:53:18 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 205040 kb
Host smart-eb9edbd9-5a19-4d3d-a082-a333989965c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286283928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.286283928
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2603337931
Short name T161
Test name
Test status
Simulation time 251307117 ps
CPU time 7.28 seconds
Started Feb 26 12:53:20 PM PST 24
Finished Feb 26 12:53:27 PM PST 24
Peak memory 213832 kb
Host smart-63393840-1fe8-4969-8d98-d2b61c8116f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603337931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2603337931
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2505425711
Short name T111
Test name
Test status
Simulation time 97320853 ps
CPU time 2.01 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:24 PM PST 24
Peak memory 221676 kb
Host smart-3934a451-7f9e-4e2c-bfe5-3388b2dbd42a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505425711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2505425711
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.430097594
Short name T506
Test name
Test status
Simulation time 125037672 ps
CPU time 1.35 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:23 PM PST 24
Peak memory 213472 kb
Host smart-21976c0f-c648-49aa-adef-808356b4de64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430097594 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.430097594
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1940825417
Short name T121
Test name
Test status
Simulation time 14122776 ps
CPU time 1.21 seconds
Started Feb 26 12:53:24 PM PST 24
Finished Feb 26 12:53:26 PM PST 24
Peak memory 205140 kb
Host smart-f5ab6793-154a-4e32-81e8-d7acc24fc685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940825417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1940825417
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2796390986
Short name T453
Test name
Test status
Simulation time 11386733 ps
CPU time 0.83 seconds
Started Feb 26 12:53:28 PM PST 24
Finished Feb 26 12:53:29 PM PST 24
Peak memory 205128 kb
Host smart-f8bcc697-9b29-470a-9374-80102bb5c2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796390986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2796390986
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3195460647
Short name T534
Test name
Test status
Simulation time 330933237 ps
CPU time 2.71 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 213796 kb
Host smart-70d6e97e-5a60-4312-b69f-d1e94b01ff4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195460647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3195460647
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3691105270
Short name T484
Test name
Test status
Simulation time 27639311 ps
CPU time 1.49 seconds
Started Feb 26 12:53:34 PM PST 24
Finished Feb 26 12:53:35 PM PST 24
Peak memory 213732 kb
Host smart-b095b3a2-0264-4e27-93c6-ec3a175397d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691105270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3691105270
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1409679630
Short name T438
Test name
Test status
Simulation time 61104397 ps
CPU time 1.32 seconds
Started Feb 26 12:53:18 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 213484 kb
Host smart-c02a8723-6515-4202-9286-513c987c5260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409679630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1409679630
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.838851154
Short name T493
Test name
Test status
Simulation time 16040494 ps
CPU time 1.07 seconds
Started Feb 26 12:53:16 PM PST 24
Finished Feb 26 12:53:18 PM PST 24
Peak memory 205160 kb
Host smart-a7a11203-2c96-4f45-8247-5a67a514fe7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838851154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.838851154
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2722667873
Short name T524
Test name
Test status
Simulation time 13220628 ps
CPU time 0.85 seconds
Started Feb 26 12:53:24 PM PST 24
Finished Feb 26 12:53:25 PM PST 24
Peak memory 205164 kb
Host smart-f4b441e8-cd27-4222-a8c6-6f87b4fec0ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722667873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2722667873
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2745223100
Short name T122
Test name
Test status
Simulation time 319667619 ps
CPU time 3.51 seconds
Started Feb 26 12:53:25 PM PST 24
Finished Feb 26 12:53:29 PM PST 24
Peak memory 205308 kb
Host smart-cffa1e28-301f-4407-b068-dd72feb52705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745223100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2745223100
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3875649681
Short name T530
Test name
Test status
Simulation time 325104805 ps
CPU time 5.57 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 213736 kb
Host smart-9f6db1ea-2843-482d-986c-e049fccdd4e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875649681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3875649681
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1602615124
Short name T452
Test name
Test status
Simulation time 353990747 ps
CPU time 7.85 seconds
Started Feb 26 12:53:16 PM PST 24
Finished Feb 26 12:53:24 PM PST 24
Peak memory 219904 kb
Host smart-10fb6970-b9d9-426f-8ff6-335ed727e3a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602615124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1602615124
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.496996695
Short name T481
Test name
Test status
Simulation time 94731683 ps
CPU time 2.92 seconds
Started Feb 26 12:53:18 PM PST 24
Finished Feb 26 12:53:22 PM PST 24
Peak memory 213492 kb
Host smart-f9487f5d-5076-49ba-b9d5-185bc5a70a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496996695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.496996695
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2806925995
Short name T538
Test name
Test status
Simulation time 56856175 ps
CPU time 1.13 seconds
Started Feb 26 12:53:44 PM PST 24
Finished Feb 26 12:53:46 PM PST 24
Peak memory 205256 kb
Host smart-1a98822e-25dc-4319-8627-42a1017439d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806925995 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2806925995
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1026937527
Short name T482
Test name
Test status
Simulation time 52416151 ps
CPU time 1.21 seconds
Started Feb 26 12:53:25 PM PST 24
Finished Feb 26 12:53:27 PM PST 24
Peak memory 205232 kb
Host smart-2b1a99da-3e76-4c58-af76-fc8c9f008779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026937527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1026937527
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3439527871
Short name T429
Test name
Test status
Simulation time 201334115 ps
CPU time 0.81 seconds
Started Feb 26 12:53:20 PM PST 24
Finished Feb 26 12:53:21 PM PST 24
Peak memory 205156 kb
Host smart-5c197eef-0fbb-4c73-920a-ad8af50b5a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439527871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3439527871
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2059234581
Short name T462
Test name
Test status
Simulation time 285853574 ps
CPU time 2.56 seconds
Started Feb 26 12:53:28 PM PST 24
Finished Feb 26 12:53:31 PM PST 24
Peak memory 205312 kb
Host smart-94eb5074-66c3-423c-8a2d-f828bd210b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059234581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2059234581
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.977535759
Short name T499
Test name
Test status
Simulation time 1029276767 ps
CPU time 6.01 seconds
Started Feb 26 12:53:19 PM PST 24
Finished Feb 26 12:53:26 PM PST 24
Peak memory 218852 kb
Host smart-3bc8bb1a-3610-4062-bd4b-0535364bfbab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977535759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.977535759
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4117967843
Short name T434
Test name
Test status
Simulation time 208223225 ps
CPU time 10.14 seconds
Started Feb 26 12:53:17 PM PST 24
Finished Feb 26 12:53:28 PM PST 24
Peak memory 213744 kb
Host smart-2353bd24-d9f9-4efa-a702-71bce70ec999
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117967843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4117967843
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3181285412
Short name T513
Test name
Test status
Simulation time 61910607 ps
CPU time 2.14 seconds
Started Feb 26 12:53:22 PM PST 24
Finished Feb 26 12:53:25 PM PST 24
Peak memory 221740 kb
Host smart-5e644ad7-04aa-4e81-88cc-a91c8bcac137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181285412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3181285412
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1515458760
Short name T160
Test name
Test status
Simulation time 126258306 ps
CPU time 3.47 seconds
Started Feb 26 12:53:23 PM PST 24
Finished Feb 26 12:53:27 PM PST 24
Peak memory 213648 kb
Host smart-c608fcae-5eab-4535-9614-ee0f027ffea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515458760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1515458760
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.156124945
Short name T113
Test name
Test status
Simulation time 42570463 ps
CPU time 1.76 seconds
Started Feb 26 12:53:24 PM PST 24
Finished Feb 26 12:53:26 PM PST 24
Peak memory 213528 kb
Host smart-fede7b87-484b-406f-ace8-02f36a361767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156124945 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.156124945
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3564075336
Short name T479
Test name
Test status
Simulation time 21135385 ps
CPU time 0.72 seconds
Started Feb 26 12:53:37 PM PST 24
Finished Feb 26 12:53:38 PM PST 24
Peak memory 205124 kb
Host smart-f60f7140-a870-4f35-a3f8-dbe41426330e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564075336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3564075336
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3931768332
Short name T520
Test name
Test status
Simulation time 251805778 ps
CPU time 2.12 seconds
Started Feb 26 12:53:28 PM PST 24
Finished Feb 26 12:53:30 PM PST 24
Peak memory 205316 kb
Host smart-84eb2ee8-4457-45ad-b97c-287f17ba9214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931768332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3931768332
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1667811661
Short name T167
Test name
Test status
Simulation time 236360889 ps
CPU time 4.17 seconds
Started Feb 26 12:53:30 PM PST 24
Finished Feb 26 12:53:34 PM PST 24
Peak memory 213880 kb
Host smart-0535b3de-062e-44c0-b560-27904b07c7fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667811661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1667811661
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.739613978
Short name T442
Test name
Test status
Simulation time 441163879 ps
CPU time 5.63 seconds
Started Feb 26 12:53:31 PM PST 24
Finished Feb 26 12:53:37 PM PST 24
Peak memory 213680 kb
Host smart-2fc0696f-2768-43a6-95cc-93062fd595c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739613978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.739613978
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2669943030
Short name T148
Test name
Test status
Simulation time 152225912 ps
CPU time 2.99 seconds
Started Feb 26 12:53:26 PM PST 24
Finished Feb 26 12:53:29 PM PST 24
Peak memory 213560 kb
Host smart-722f2955-aadf-4455-b5cc-3588592eced5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669943030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2669943030
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2663414652
Short name T509
Test name
Test status
Simulation time 162222408 ps
CPU time 4.14 seconds
Started Feb 26 12:53:34 PM PST 24
Finished Feb 26 12:53:38 PM PST 24
Peak memory 213620 kb
Host smart-2a24ccd5-3188-4d73-893d-d8c485408eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663414652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2663414652
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2759361609
Short name T430
Test name
Test status
Simulation time 136855674 ps
CPU time 7.47 seconds
Started Feb 26 12:53:05 PM PST 24
Finished Feb 26 12:53:12 PM PST 24
Peak memory 205240 kb
Host smart-fcd636b7-510b-4657-84f3-8a646bb57195
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759361609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
759361609
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1793790927
Short name T475
Test name
Test status
Simulation time 999715979 ps
CPU time 14.85 seconds
Started Feb 26 12:52:55 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 205116 kb
Host smart-277d1ce8-fc79-4985-83e0-ba3f97075e50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793790927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
793790927
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4195637779
Short name T119
Test name
Test status
Simulation time 34507030 ps
CPU time 1.29 seconds
Started Feb 26 12:52:50 PM PST 24
Finished Feb 26 12:52:52 PM PST 24
Peak memory 205184 kb
Host smart-36729a32-ed1c-42c1-8a7a-dc5b223a898a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195637779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
195637779
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1430754153
Short name T536
Test name
Test status
Simulation time 42825444 ps
CPU time 1.35 seconds
Started Feb 26 12:52:58 PM PST 24
Finished Feb 26 12:52:59 PM PST 24
Peak memory 213448 kb
Host smart-7e039185-6fc7-4e1b-b5f8-efc2a24032bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430754153 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1430754153
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2978582660
Short name T515
Test name
Test status
Simulation time 26205671 ps
CPU time 1.11 seconds
Started Feb 26 12:53:07 PM PST 24
Finished Feb 26 12:53:09 PM PST 24
Peak memory 205288 kb
Host smart-27f135aa-65ae-4ff3-8b18-92767c5139e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978582660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2978582660
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.236033792
Short name T170
Test name
Test status
Simulation time 117861253 ps
CPU time 0.75 seconds
Started Feb 26 12:52:53 PM PST 24
Finished Feb 26 12:52:55 PM PST 24
Peak memory 205036 kb
Host smart-fa575c08-1715-48b6-bfe0-f03cca5c14f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236033792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.236033792
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2198017636
Short name T467
Test name
Test status
Simulation time 689515496 ps
CPU time 3.78 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:04 PM PST 24
Peak memory 205192 kb
Host smart-69c0a500-e344-4c86-a06f-a787e0f0326c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198017636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2198017636
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3971290205
Short name T163
Test name
Test status
Simulation time 971346143 ps
CPU time 6.15 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:07 PM PST 24
Peak memory 218544 kb
Host smart-503100c5-417a-455c-9166-58e8ae43d190
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971290205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3971290205
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3816484921
Short name T517
Test name
Test status
Simulation time 606302865 ps
CPU time 5.86 seconds
Started Feb 26 12:52:52 PM PST 24
Finished Feb 26 12:52:59 PM PST 24
Peak memory 213664 kb
Host smart-c8553fe4-da84-4cff-a325-ee474f11bc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816484921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3816484921
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1587920721
Short name T145
Test name
Test status
Simulation time 1264721880 ps
CPU time 11.14 seconds
Started Feb 26 12:52:55 PM PST 24
Finished Feb 26 12:53:07 PM PST 24
Peak memory 213500 kb
Host smart-5073bbde-ffb4-4517-a7ec-7bf2cb59b41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587920721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1587920721
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1025767697
Short name T472
Test name
Test status
Simulation time 18632211 ps
CPU time 0.81 seconds
Started Feb 26 12:53:45 PM PST 24
Finished Feb 26 12:53:46 PM PST 24
Peak memory 205176 kb
Host smart-7148b908-c8d1-435b-88ff-ff93a658b5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025767697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1025767697
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3319344489
Short name T440
Test name
Test status
Simulation time 45447272 ps
CPU time 0.75 seconds
Started Feb 26 12:53:26 PM PST 24
Finished Feb 26 12:53:27 PM PST 24
Peak memory 205036 kb
Host smart-01fe2d23-5de0-4d0e-a814-9a0f80c93aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319344489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3319344489
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2607530804
Short name T432
Test name
Test status
Simulation time 15937758 ps
CPU time 0.74 seconds
Started Feb 26 12:53:39 PM PST 24
Finished Feb 26 12:53:40 PM PST 24
Peak memory 205140 kb
Host smart-1334f0e6-f0e4-48c9-8c82-b96dfeae7a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607530804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2607530804
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1944131154
Short name T461
Test name
Test status
Simulation time 19855519 ps
CPU time 0.87 seconds
Started Feb 26 12:53:29 PM PST 24
Finished Feb 26 12:53:30 PM PST 24
Peak memory 205084 kb
Host smart-811c909b-5aa6-42d9-b4d1-eb22d122b2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944131154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1944131154
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3379694985
Short name T420
Test name
Test status
Simulation time 77541730 ps
CPU time 0.8 seconds
Started Feb 26 12:53:46 PM PST 24
Finished Feb 26 12:53:52 PM PST 24
Peak memory 205112 kb
Host smart-200850c0-fa3d-4d1d-945e-cb75ca6e4921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379694985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3379694985
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1270422070
Short name T169
Test name
Test status
Simulation time 109175169 ps
CPU time 0.67 seconds
Started Feb 26 12:53:37 PM PST 24
Finished Feb 26 12:53:38 PM PST 24
Peak memory 204924 kb
Host smart-4bb5d411-7e16-4be6-badb-3bba5af62fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270422070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1270422070
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2687151860
Short name T445
Test name
Test status
Simulation time 29840684 ps
CPU time 0.7 seconds
Started Feb 26 12:53:28 PM PST 24
Finished Feb 26 12:53:29 PM PST 24
Peak memory 205104 kb
Host smart-8624b897-fff1-4475-b62f-47ff0ffe2653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687151860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2687151860
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.489979988
Short name T466
Test name
Test status
Simulation time 37425678 ps
CPU time 0.74 seconds
Started Feb 26 12:53:39 PM PST 24
Finished Feb 26 12:53:40 PM PST 24
Peak memory 205148 kb
Host smart-4952ea85-6a69-4afd-b479-57c60cb952d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489979988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.489979988
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.957623886
Short name T449
Test name
Test status
Simulation time 12868319 ps
CPU time 0.72 seconds
Started Feb 26 12:53:43 PM PST 24
Finished Feb 26 12:53:44 PM PST 24
Peak memory 205068 kb
Host smart-b645f897-ef2e-490d-adf2-f3e0eb7e7ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957623886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.957623886
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1941235709
Short name T431
Test name
Test status
Simulation time 12907410 ps
CPU time 0.83 seconds
Started Feb 26 12:53:30 PM PST 24
Finished Feb 26 12:53:31 PM PST 24
Peak memory 205040 kb
Host smart-d41af7da-67cc-407a-bbe6-1079719f65af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941235709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1941235709
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3588893019
Short name T144
Test name
Test status
Simulation time 491503854 ps
CPU time 5.03 seconds
Started Feb 26 12:53:11 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205228 kb
Host smart-cce2e163-5fee-478a-ae26-fb3fb66331d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588893019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
588893019
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3080786108
Short name T502
Test name
Test status
Simulation time 2794405066 ps
CPU time 13.03 seconds
Started Feb 26 12:52:57 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 205280 kb
Host smart-5c340d1c-e1c9-40ab-aea0-f5ade1f3d1b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080786108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
080786108
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3891100468
Short name T516
Test name
Test status
Simulation time 26310973 ps
CPU time 1.03 seconds
Started Feb 26 12:52:57 PM PST 24
Finished Feb 26 12:52:58 PM PST 24
Peak memory 205120 kb
Host smart-d5c52faa-1415-43b5-a361-90720b7b6cfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891100468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
891100468
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3328416958
Short name T110
Test name
Test status
Simulation time 23427457 ps
CPU time 1.81 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:08 PM PST 24
Peak memory 213460 kb
Host smart-76d583ea-e92a-4555-851e-4da60d903862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328416958 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3328416958
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1927696509
Short name T436
Test name
Test status
Simulation time 266674559 ps
CPU time 1.57 seconds
Started Feb 26 12:53:07 PM PST 24
Finished Feb 26 12:53:09 PM PST 24
Peak memory 205364 kb
Host smart-f4ae6c03-442f-4a73-9fea-09e44f110bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927696509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1927696509
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3754849935
Short name T529
Test name
Test status
Simulation time 14336388 ps
CPU time 0.85 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:01 PM PST 24
Peak memory 205144 kb
Host smart-5681da12-10b2-4c91-930b-9fb53a4b4dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754849935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3754849935
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4016201995
Short name T478
Test name
Test status
Simulation time 869040512 ps
CPU time 15.46 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:22 PM PST 24
Peak memory 215356 kb
Host smart-c3cbcf85-eb4b-4afa-af08-69e2ae6bca0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016201995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4016201995
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3271384094
Short name T99
Test name
Test status
Simulation time 214664763 ps
CPU time 8.32 seconds
Started Feb 26 12:52:59 PM PST 24
Finished Feb 26 12:53:07 PM PST 24
Peak memory 221864 kb
Host smart-f46900aa-0d4a-4598-9e52-09fdd017e751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271384094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3271384094
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1817570035
Short name T496
Test name
Test status
Simulation time 163733902 ps
CPU time 2.29 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:02 PM PST 24
Peak memory 213456 kb
Host smart-f297eb83-79d2-4534-bcd3-5ebc324946eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817570035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1817570035
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3628292270
Short name T155
Test name
Test status
Simulation time 761718100 ps
CPU time 10.17 seconds
Started Feb 26 12:53:00 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 208020 kb
Host smart-9a2ad60c-a294-4a2b-94a1-81c29b266a52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628292270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3628292270
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1372503906
Short name T439
Test name
Test status
Simulation time 38960605 ps
CPU time 0.76 seconds
Started Feb 26 12:53:40 PM PST 24
Finished Feb 26 12:53:41 PM PST 24
Peak memory 205040 kb
Host smart-ccd7ee3c-076c-4eaa-ab75-7c0e12d9db48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372503906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1372503906
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3046161023
Short name T444
Test name
Test status
Simulation time 42402281 ps
CPU time 0.86 seconds
Started Feb 26 12:53:35 PM PST 24
Finished Feb 26 12:53:36 PM PST 24
Peak memory 205156 kb
Host smart-147c3e5b-00c6-4987-9dcd-48708dda7ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046161023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3046161023
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2332190448
Short name T374
Test name
Test status
Simulation time 28902605 ps
CPU time 0.79 seconds
Started Feb 26 12:53:25 PM PST 24
Finished Feb 26 12:53:26 PM PST 24
Peak memory 205160 kb
Host smart-e08f0244-1021-447f-aefb-6a60ea1e4a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332190448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2332190448
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1808674130
Short name T531
Test name
Test status
Simulation time 16518606 ps
CPU time 0.72 seconds
Started Feb 26 12:53:32 PM PST 24
Finished Feb 26 12:53:33 PM PST 24
Peak memory 205176 kb
Host smart-688cac8c-6f6b-423a-ac4c-1b5a256aafdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808674130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1808674130
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1959112011
Short name T446
Test name
Test status
Simulation time 75407535 ps
CPU time 0.81 seconds
Started Feb 26 12:53:40 PM PST 24
Finished Feb 26 12:53:42 PM PST 24
Peak memory 205092 kb
Host smart-0c045f86-a65b-4197-8042-02252f1ec20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959112011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1959112011
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2834087276
Short name T470
Test name
Test status
Simulation time 13215287 ps
CPU time 0.71 seconds
Started Feb 26 12:53:29 PM PST 24
Finished Feb 26 12:53:30 PM PST 24
Peak memory 205188 kb
Host smart-95411a8e-493e-4928-a521-f73f848342a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834087276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2834087276
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.642615453
Short name T519
Test name
Test status
Simulation time 53056979 ps
CPU time 0.81 seconds
Started Feb 26 12:53:30 PM PST 24
Finished Feb 26 12:53:31 PM PST 24
Peak memory 205176 kb
Host smart-3084a722-8eab-4652-8ac9-369a8ec6663c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642615453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.642615453
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2583288917
Short name T507
Test name
Test status
Simulation time 10534900 ps
CPU time 0.81 seconds
Started Feb 26 12:53:35 PM PST 24
Finished Feb 26 12:53:36 PM PST 24
Peak memory 205176 kb
Host smart-089d7066-a875-42c7-ab64-a222e7480b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583288917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2583288917
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4084460699
Short name T474
Test name
Test status
Simulation time 51094679 ps
CPU time 0.69 seconds
Started Feb 26 12:53:50 PM PST 24
Finished Feb 26 12:53:51 PM PST 24
Peak memory 205064 kb
Host smart-0ab1402f-e650-4243-974a-bbe14fc4f952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084460699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4084460699
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.748747601
Short name T373
Test name
Test status
Simulation time 12612297 ps
CPU time 0.85 seconds
Started Feb 26 12:53:38 PM PST 24
Finished Feb 26 12:53:40 PM PST 24
Peak memory 205100 kb
Host smart-5cbb092e-dcd9-4414-88c0-e70d810a9016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748747601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.748747601
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2070190061
Short name T443
Test name
Test status
Simulation time 1038037236 ps
CPU time 12.62 seconds
Started Feb 26 12:52:56 PM PST 24
Finished Feb 26 12:53:09 PM PST 24
Peak memory 205116 kb
Host smart-3da8c4c4-36dc-49b1-b58e-d3621bdfb7e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070190061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
070190061
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2095574947
Short name T433
Test name
Test status
Simulation time 11833534 ps
CPU time 0.86 seconds
Started Feb 26 12:52:59 PM PST 24
Finished Feb 26 12:53:00 PM PST 24
Peak memory 204964 kb
Host smart-34f225a0-43e2-4d03-805f-067820f97da3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095574947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
095574947
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.104304638
Short name T468
Test name
Test status
Simulation time 57742520 ps
CPU time 1.14 seconds
Started Feb 26 12:52:55 PM PST 24
Finished Feb 26 12:52:57 PM PST 24
Peak memory 205368 kb
Host smart-1cd1cca3-3877-4b6c-8b08-3263057c7a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104304638 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.104304638
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.630695599
Short name T500
Test name
Test status
Simulation time 36328172 ps
CPU time 1.01 seconds
Started Feb 26 12:52:56 PM PST 24
Finished Feb 26 12:52:57 PM PST 24
Peak memory 205076 kb
Host smart-4c4aeca8-d8ab-4363-84a6-68ec1eae0308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630695599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.630695599
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1136676406
Short name T171
Test name
Test status
Simulation time 18663367 ps
CPU time 0.72 seconds
Started Feb 26 12:53:07 PM PST 24
Finished Feb 26 12:53:08 PM PST 24
Peak memory 205128 kb
Host smart-2d52e2c6-422b-41be-a015-d92ddb515dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136676406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1136676406
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.76751599
Short name T498
Test name
Test status
Simulation time 448008665 ps
CPU time 3.52 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:15 PM PST 24
Peak memory 205332 kb
Host smart-90eb1ec0-7ee5-4344-8c8f-cd6a0effe8f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76751599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same
_csr_outstanding.76751599
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4009017865
Short name T469
Test name
Test status
Simulation time 819523024 ps
CPU time 11.29 seconds
Started Feb 26 12:52:59 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 213644 kb
Host smart-ea4f9189-1178-4590-97d8-d345de058c7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009017865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4009017865
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1208732162
Short name T532
Test name
Test status
Simulation time 28875615 ps
CPU time 1.96 seconds
Started Feb 26 12:53:03 PM PST 24
Finished Feb 26 12:53:05 PM PST 24
Peak memory 213536 kb
Host smart-0d678b3a-052d-4c14-9246-2adbb70de574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208732162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1208732162
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2914212406
Short name T510
Test name
Test status
Simulation time 40890587 ps
CPU time 0.78 seconds
Started Feb 26 12:53:36 PM PST 24
Finished Feb 26 12:53:37 PM PST 24
Peak memory 205084 kb
Host smart-02fcc8cd-f3cd-4f3e-9df7-c92f6d8c155f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914212406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2914212406
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.394124309
Short name T464
Test name
Test status
Simulation time 23653910 ps
CPU time 0.77 seconds
Started Feb 26 12:53:41 PM PST 24
Finished Feb 26 12:53:42 PM PST 24
Peak memory 205124 kb
Host smart-b3763065-a15c-4209-a3e9-0508c86b21f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394124309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.394124309
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3193793368
Short name T426
Test name
Test status
Simulation time 18190266 ps
CPU time 0.8 seconds
Started Feb 26 12:53:33 PM PST 24
Finished Feb 26 12:53:34 PM PST 24
Peak memory 205092 kb
Host smart-335161e2-0017-46b1-b763-32ef4ef54bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193793368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3193793368
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1432228856
Short name T428
Test name
Test status
Simulation time 24781693 ps
CPU time 0.82 seconds
Started Feb 26 12:53:42 PM PST 24
Finished Feb 26 12:53:43 PM PST 24
Peak memory 205112 kb
Host smart-3f076429-1e6e-4a72-ba61-c06685239391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432228856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1432228856
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2431849539
Short name T372
Test name
Test status
Simulation time 35654648 ps
CPU time 0.73 seconds
Started Feb 26 12:53:33 PM PST 24
Finished Feb 26 12:53:34 PM PST 24
Peak memory 205040 kb
Host smart-67902456-1986-4081-8f2c-24aa2e16b5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431849539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2431849539
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2541777921
Short name T528
Test name
Test status
Simulation time 38371187 ps
CPU time 0.72 seconds
Started Feb 26 12:53:32 PM PST 24
Finished Feb 26 12:53:33 PM PST 24
Peak memory 205160 kb
Host smart-b9c0dd7c-e831-468c-82ca-eb6550f3be55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541777921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2541777921
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.516472626
Short name T523
Test name
Test status
Simulation time 44781814 ps
CPU time 0.87 seconds
Started Feb 26 12:53:36 PM PST 24
Finished Feb 26 12:53:37 PM PST 24
Peak memory 205388 kb
Host smart-e219a069-e593-495a-9931-7c108366d38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516472626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.516472626
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1210610065
Short name T168
Test name
Test status
Simulation time 44465604 ps
CPU time 0.85 seconds
Started Feb 26 12:53:51 PM PST 24
Finished Feb 26 12:53:52 PM PST 24
Peak memory 205176 kb
Host smart-da2bcd33-a3c0-432d-9841-8186f5692b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210610065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1210610065
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.352139900
Short name T508
Test name
Test status
Simulation time 30591448 ps
CPU time 0.71 seconds
Started Feb 26 12:53:46 PM PST 24
Finished Feb 26 12:53:47 PM PST 24
Peak memory 205084 kb
Host smart-32f61455-a62d-4d2a-a06c-11c8dd290dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352139900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.352139900
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1542649966
Short name T165
Test name
Test status
Simulation time 7498162 ps
CPU time 0.69 seconds
Started Feb 26 12:53:34 PM PST 24
Finished Feb 26 12:53:35 PM PST 24
Peak memory 205088 kb
Host smart-46a66e32-4eaf-4f74-b15d-e6138a8ab5ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542649966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1542649966
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1500316923
Short name T164
Test name
Test status
Simulation time 60458066 ps
CPU time 1.58 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:08 PM PST 24
Peak memory 213432 kb
Host smart-f05a237a-4f6a-4432-a046-f7ac3fad6dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500316923 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1500316923
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2740397971
Short name T422
Test name
Test status
Simulation time 8937372 ps
CPU time 0.72 seconds
Started Feb 26 12:53:04 PM PST 24
Finished Feb 26 12:53:05 PM PST 24
Peak memory 205176 kb
Host smart-3a7c8ce5-eff9-4967-8164-fae0582d4d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740397971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2740397971
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3403877151
Short name T159
Test name
Test status
Simulation time 128810308 ps
CPU time 4.52 seconds
Started Feb 26 12:52:58 PM PST 24
Finished Feb 26 12:53:02 PM PST 24
Peak memory 213780 kb
Host smart-73f6e8d7-97af-4478-a650-4e591a1ccf33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403877151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3403877151
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.376638364
Short name T514
Test name
Test status
Simulation time 42829400 ps
CPU time 3.08 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 213632 kb
Host smart-3d24cc22-1b37-4581-a1d9-757182931bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376638364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.376638364
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3487824771
Short name T504
Test name
Test status
Simulation time 18107105 ps
CPU time 1.56 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 213636 kb
Host smart-7b695daf-c2e3-453a-b8e7-6d9b15955a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487824771 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3487824771
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.267266575
Short name T116
Test name
Test status
Simulation time 39630882 ps
CPU time 0.88 seconds
Started Feb 26 12:52:57 PM PST 24
Finished Feb 26 12:52:58 PM PST 24
Peak memory 205068 kb
Host smart-8afdb909-f3ce-46fd-b37e-08ab48aca698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267266575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.267266575
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3093989236
Short name T435
Test name
Test status
Simulation time 107575241 ps
CPU time 0.77 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:13 PM PST 24
Peak memory 205140 kb
Host smart-23736343-1cfc-4250-ae38-2689dddfaa53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093989236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3093989236
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.826585719
Short name T527
Test name
Test status
Simulation time 756160884 ps
CPU time 13.8 seconds
Started Feb 26 12:53:03 PM PST 24
Finished Feb 26 12:53:18 PM PST 24
Peak memory 221948 kb
Host smart-7ce394ce-2711-44a0-84bb-b290ba49ebb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826585719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.826585719
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1550677242
Short name T485
Test name
Test status
Simulation time 558581994 ps
CPU time 4.28 seconds
Started Feb 26 12:53:07 PM PST 24
Finished Feb 26 12:53:11 PM PST 24
Peak memory 213524 kb
Host smart-efd9bcdb-24a8-441f-8725-81850393ad02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550677242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1550677242
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3755385065
Short name T421
Test name
Test status
Simulation time 28846096 ps
CPU time 1.25 seconds
Started Feb 26 12:53:11 PM PST 24
Finished Feb 26 12:53:13 PM PST 24
Peak memory 213624 kb
Host smart-aa38f288-194e-43d3-93c7-d6da17be473f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755385065 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3755385065
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2831882180
Short name T497
Test name
Test status
Simulation time 53072183 ps
CPU time 1.1 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 205068 kb
Host smart-b8c2cdb7-c1d0-483d-bb26-3499a7f0a22d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831882180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2831882180
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1988980650
Short name T492
Test name
Test status
Simulation time 14431600 ps
CPU time 0.83 seconds
Started Feb 26 12:53:08 PM PST 24
Finished Feb 26 12:53:09 PM PST 24
Peak memory 205040 kb
Host smart-991a0a44-39bb-4cbd-a10f-40ea61f9f6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988980650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1988980650
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.691854515
Short name T512
Test name
Test status
Simulation time 97060576 ps
CPU time 1.55 seconds
Started Feb 26 12:53:03 PM PST 24
Finished Feb 26 12:53:05 PM PST 24
Peak memory 205164 kb
Host smart-7b633bf1-9180-4bfe-8d6d-8d893f355896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691854515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.691854515
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.284483773
Short name T104
Test name
Test status
Simulation time 371729460 ps
CPU time 4.54 seconds
Started Feb 26 12:52:56 PM PST 24
Finished Feb 26 12:53:01 PM PST 24
Peak memory 213708 kb
Host smart-22042549-677c-4b2b-ae2a-3783541b8f35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284483773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.284483773
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2993360973
Short name T143
Test name
Test status
Simulation time 133346186 ps
CPU time 2.39 seconds
Started Feb 26 12:53:04 PM PST 24
Finished Feb 26 12:53:06 PM PST 24
Peak memory 213472 kb
Host smart-5f09e636-7afc-41fa-a515-e35758155681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993360973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2993360973
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1808877661
Short name T454
Test name
Test status
Simulation time 538610130 ps
CPU time 7.38 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:21 PM PST 24
Peak memory 209112 kb
Host smart-1fbb6722-e574-43d8-bacc-f9c3f66fc197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808877661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1808877661
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.975817193
Short name T120
Test name
Test status
Simulation time 17682197 ps
CPU time 0.81 seconds
Started Feb 26 12:53:09 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 205096 kb
Host smart-75093db6-f6c0-4c62-802e-b08bc4335e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975817193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.975817193
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2392459155
Short name T457
Test name
Test status
Simulation time 16396777 ps
CPU time 0.71 seconds
Started Feb 26 12:53:07 PM PST 24
Finished Feb 26 12:53:08 PM PST 24
Peak memory 205172 kb
Host smart-8fac6985-4c3b-483c-b255-99d3fe463ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392459155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2392459155
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1557208454
Short name T477
Test name
Test status
Simulation time 106594872 ps
CPU time 1.48 seconds
Started Feb 26 12:53:15 PM PST 24
Finished Feb 26 12:53:17 PM PST 24
Peak memory 205592 kb
Host smart-e702a327-e8fe-4f69-b76c-7128054ccf0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557208454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1557208454
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1386583604
Short name T107
Test name
Test status
Simulation time 1092496808 ps
CPU time 5.59 seconds
Started Feb 26 12:53:04 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 213796 kb
Host smart-84604602-6f2a-4a7c-814d-135f32a58195
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386583604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1386583604
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1570887433
Short name T476
Test name
Test status
Simulation time 112577195 ps
CPU time 5.98 seconds
Started Feb 26 12:53:12 PM PST 24
Finished Feb 26 12:53:18 PM PST 24
Peak memory 219772 kb
Host smart-148d74fb-5c13-4608-b7f3-2d35b0b90b48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570887433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1570887433
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1664566758
Short name T114
Test name
Test status
Simulation time 138818296 ps
CPU time 3.03 seconds
Started Feb 26 12:53:08 PM PST 24
Finished Feb 26 12:53:11 PM PST 24
Peak memory 216660 kb
Host smart-f6852020-cc82-407a-8ec9-39d7c99c5dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664566758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1664566758
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1755229496
Short name T463
Test name
Test status
Simulation time 22681176 ps
CPU time 1.5 seconds
Started Feb 26 12:53:10 PM PST 24
Finished Feb 26 12:53:12 PM PST 24
Peak memory 213588 kb
Host smart-bdd5bb1c-59e6-4d7d-9614-652b1db555af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755229496 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1755229496
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1537079331
Short name T126
Test name
Test status
Simulation time 25179328 ps
CPU time 1.18 seconds
Started Feb 26 12:53:14 PM PST 24
Finished Feb 26 12:53:15 PM PST 24
Peak memory 205312 kb
Host smart-a76ccc2b-29a5-4199-99e7-0135671e4bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537079331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1537079331
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.268864954
Short name T447
Test name
Test status
Simulation time 33499622 ps
CPU time 0.68 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 205068 kb
Host smart-4fd7ce50-5387-4f08-919c-b2478110d275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268864954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.268864954
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1299118538
Short name T471
Test name
Test status
Simulation time 194845738 ps
CPU time 1.8 seconds
Started Feb 26 12:53:11 PM PST 24
Finished Feb 26 12:53:14 PM PST 24
Peak memory 205276 kb
Host smart-9b384e3e-16b7-4939-87ce-eb11ec279628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299118538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1299118538
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1552939537
Short name T465
Test name
Test status
Simulation time 488029764 ps
CPU time 3.74 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 213668 kb
Host smart-c89c0ce7-8c1e-47f7-9bec-bcd1d823594f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552939537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1552939537
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2261893891
Short name T458
Test name
Test status
Simulation time 109373753 ps
CPU time 5.61 seconds
Started Feb 26 12:53:13 PM PST 24
Finished Feb 26 12:53:19 PM PST 24
Peak memory 221860 kb
Host smart-b506d732-8208-4285-9ea2-fd3aa14ac7da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261893891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2261893891
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.817957319
Short name T102
Test name
Test status
Simulation time 41475424 ps
CPU time 2.99 seconds
Started Feb 26 12:53:06 PM PST 24
Finished Feb 26 12:53:10 PM PST 24
Peak memory 216928 kb
Host smart-769e7c10-b4a0-4fc5-978b-6c32f4195322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817957319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.817957319
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3236625001
Short name T587
Test name
Test status
Simulation time 12690329 ps
CPU time 0.78 seconds
Started Feb 26 03:13:54 PM PST 24
Finished Feb 26 03:13:54 PM PST 24
Peak memory 205776 kb
Host smart-01092ce7-cc68-4cc1-a9dd-c3b0982d86cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236625001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3236625001
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3894744040
Short name T106
Test name
Test status
Simulation time 50716963 ps
CPU time 3.39 seconds
Started Feb 26 03:13:45 PM PST 24
Finished Feb 26 03:13:49 PM PST 24
Peak memory 214220 kb
Host smart-b057087d-433a-4f90-bec9-5565143978a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894744040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3894744040
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4228028302
Short name T843
Test name
Test status
Simulation time 1867286468 ps
CPU time 3.5 seconds
Started Feb 26 03:13:50 PM PST 24
Finished Feb 26 03:13:54 PM PST 24
Peak memory 207224 kb
Host smart-f975d160-b7e4-438f-94a5-cab227e637dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228028302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4228028302
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1417392919
Short name T837
Test name
Test status
Simulation time 1894571581 ps
CPU time 62.41 seconds
Started Feb 26 03:13:51 PM PST 24
Finished Feb 26 03:14:54 PM PST 24
Peak memory 209768 kb
Host smart-3882691d-0ec6-4ee9-9fb7-7c036e3a7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417392919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1417392919
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3604299753
Short name T271
Test name
Test status
Simulation time 40178803 ps
CPU time 2.79 seconds
Started Feb 26 03:13:51 PM PST 24
Finished Feb 26 03:13:53 PM PST 24
Peak memory 209708 kb
Host smart-ac9c7111-77c6-4283-a9c0-06f461fda87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604299753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3604299753
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3403292158
Short name T360
Test name
Test status
Simulation time 3135258418 ps
CPU time 43.82 seconds
Started Feb 26 03:13:38 PM PST 24
Finished Feb 26 03:14:22 PM PST 24
Peak memory 214244 kb
Host smart-d6d0e5c7-72f1-4107-939c-d33a71890008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403292158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3403292158
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2026513464
Short name T11
Test name
Test status
Simulation time 764831632 ps
CPU time 24.73 seconds
Started Feb 26 03:13:56 PM PST 24
Finished Feb 26 03:14:21 PM PST 24
Peak memory 240800 kb
Host smart-9f5dfd2b-fd5f-4dfb-b4c7-aa05f175c6f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026513464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2026513464
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2994164303
Short name T387
Test name
Test status
Simulation time 250086755 ps
CPU time 6.76 seconds
Started Feb 26 03:13:37 PM PST 24
Finished Feb 26 03:13:44 PM PST 24
Peak memory 206860 kb
Host smart-0d236528-4350-4167-8357-3acfa17de391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994164303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2994164303
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3783486426
Short name T664
Test name
Test status
Simulation time 4654264495 ps
CPU time 29.3 seconds
Started Feb 26 03:13:36 PM PST 24
Finished Feb 26 03:14:05 PM PST 24
Peak memory 208676 kb
Host smart-94125525-e68f-43e5-9ca4-13f1703104d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783486426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3783486426
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1350704555
Short name T708
Test name
Test status
Simulation time 99342111 ps
CPU time 2.65 seconds
Started Feb 26 03:13:39 PM PST 24
Finished Feb 26 03:13:42 PM PST 24
Peak memory 206940 kb
Host smart-64f0d04c-ca73-4eae-b51e-78d20437dcc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350704555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1350704555
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4162375321
Short name T614
Test name
Test status
Simulation time 793827100 ps
CPU time 20.76 seconds
Started Feb 26 03:13:36 PM PST 24
Finished Feb 26 03:13:57 PM PST 24
Peak memory 208844 kb
Host smart-3df47dff-026d-49d0-bbe1-bebe51814fa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162375321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4162375321
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2349096016
Short name T908
Test name
Test status
Simulation time 18729106 ps
CPU time 1.56 seconds
Started Feb 26 03:13:53 PM PST 24
Finished Feb 26 03:13:55 PM PST 24
Peak memory 207300 kb
Host smart-2d179591-540e-4bec-8221-edb76fcdb76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349096016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2349096016
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.447716516
Short name T622
Test name
Test status
Simulation time 111634367 ps
CPU time 2.3 seconds
Started Feb 26 03:13:39 PM PST 24
Finished Feb 26 03:13:42 PM PST 24
Peak memory 206776 kb
Host smart-0118355a-946c-46b3-87ee-b4b953769548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447716516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.447716516
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1326980269
Short name T992
Test name
Test status
Simulation time 781853158 ps
CPU time 10.02 seconds
Started Feb 26 03:13:56 PM PST 24
Finished Feb 26 03:14:06 PM PST 24
Peak memory 223124 kb
Host smart-cff7a5d7-ecb5-4599-b44c-49d99e5a0ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326980269 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1326980269
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.252416641
Short name T874
Test name
Test status
Simulation time 142616500 ps
CPU time 2.71 seconds
Started Feb 26 03:13:56 PM PST 24
Finished Feb 26 03:13:59 PM PST 24
Peak memory 207988 kb
Host smart-5ef31c12-4dfd-43dd-8be5-df9eb2567270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252416641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.252416641
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3591748758
Short name T712
Test name
Test status
Simulation time 84268740 ps
CPU time 2.57 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:14:03 PM PST 24
Peak memory 214344 kb
Host smart-a8fc11a9-6055-4bfc-abf5-ea1852b2dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591748758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3591748758
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1750218115
Short name T673
Test name
Test status
Simulation time 42182659 ps
CPU time 0.76 seconds
Started Feb 26 03:14:01 PM PST 24
Finished Feb 26 03:14:02 PM PST 24
Peak memory 205888 kb
Host smart-2c8c98ea-fb93-42e4-8a2e-4d51013d4fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750218115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1750218115
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.912495009
Short name T332
Test name
Test status
Simulation time 47827970 ps
CPU time 1.86 seconds
Started Feb 26 03:13:58 PM PST 24
Finished Feb 26 03:14:00 PM PST 24
Peak memory 214324 kb
Host smart-88277c02-5419-46b6-9d1a-19188ded5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912495009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.912495009
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3563847352
Short name T762
Test name
Test status
Simulation time 1628324036 ps
CPU time 39.58 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:14:39 PM PST 24
Peak memory 209360 kb
Host smart-827d8120-c2ee-4c02-a2fb-c9a3db1ed1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563847352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3563847352
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.999505005
Short name T16
Test name
Test status
Simulation time 85887688 ps
CPU time 2.44 seconds
Started Feb 26 03:13:59 PM PST 24
Finished Feb 26 03:14:02 PM PST 24
Peak memory 214348 kb
Host smart-176992fd-09e1-4d65-8ca7-2d90f3267d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999505005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.999505005
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.197208520
Short name T12
Test name
Test status
Simulation time 963103883 ps
CPU time 25.06 seconds
Started Feb 26 03:14:02 PM PST 24
Finished Feb 26 03:14:27 PM PST 24
Peak memory 231668 kb
Host smart-b755d690-9582-452b-881e-9ecba92b9b2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197208520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.197208520
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4242963462
Short name T557
Test name
Test status
Simulation time 95823516 ps
CPU time 4.39 seconds
Started Feb 26 03:13:55 PM PST 24
Finished Feb 26 03:13:59 PM PST 24
Peak memory 208516 kb
Host smart-ac9e587f-d7c9-412e-8562-b636a982fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242963462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4242963462
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1027312935
Short name T887
Test name
Test status
Simulation time 332696533 ps
CPU time 8.99 seconds
Started Feb 26 03:13:58 PM PST 24
Finished Feb 26 03:14:07 PM PST 24
Peak memory 207700 kb
Host smart-b736027e-53a9-4540-8b74-4f3ea8e3adf3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027312935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1027312935
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1939050417
Short name T851
Test name
Test status
Simulation time 642031862 ps
CPU time 20.6 seconds
Started Feb 26 03:14:01 PM PST 24
Finished Feb 26 03:14:22 PM PST 24
Peak memory 208560 kb
Host smart-575b3bd7-0765-4ef9-a3bb-35b9c20f3cbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939050417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1939050417
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2555351059
Short name T811
Test name
Test status
Simulation time 60914425 ps
CPU time 3.01 seconds
Started Feb 26 03:13:59 PM PST 24
Finished Feb 26 03:14:02 PM PST 24
Peak memory 206904 kb
Host smart-54336f27-423c-481c-bb28-36f5c70baf87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555351059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2555351059
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3427299238
Short name T178
Test name
Test status
Simulation time 115238186 ps
CPU time 4.29 seconds
Started Feb 26 03:14:01 PM PST 24
Finished Feb 26 03:14:05 PM PST 24
Peak memory 215948 kb
Host smart-e4fd9e74-73ce-4150-9a6d-7ac78e69a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427299238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3427299238
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.389858118
Short name T882
Test name
Test status
Simulation time 61840431 ps
CPU time 3.26 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:14:03 PM PST 24
Peak memory 206760 kb
Host smart-cde7df8c-fb30-4736-9026-90a661573c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389858118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.389858118
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3852689665
Short name T764
Test name
Test status
Simulation time 385060621 ps
CPU time 6.54 seconds
Started Feb 26 03:14:00 PM PST 24
Finished Feb 26 03:14:07 PM PST 24
Peak memory 222600 kb
Host smart-af57b0d3-0e7f-4765-bee4-fcc929278a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852689665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3852689665
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4262079132
Short name T726
Test name
Test status
Simulation time 192124868 ps
CPU time 6.81 seconds
Started Feb 26 03:13:59 PM PST 24
Finished Feb 26 03:14:06 PM PST 24
Peak memory 208568 kb
Host smart-860eb806-7003-4f4c-9e0f-4e7446930dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262079132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4262079132
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.783622017
Short name T571
Test name
Test status
Simulation time 28376265 ps
CPU time 0.74 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:19 PM PST 24
Peak memory 205888 kb
Host smart-3452fba3-84b0-44e2-92b8-6b87e83529fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783622017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.783622017
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2005527424
Short name T412
Test name
Test status
Simulation time 111563391 ps
CPU time 2.45 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:10 PM PST 24
Peak memory 214268 kb
Host smart-0944c185-4ee0-4488-9761-0d13d4f43277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005527424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2005527424
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1301533633
Short name T333
Test name
Test status
Simulation time 80438565 ps
CPU time 2.83 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:21 PM PST 24
Peak memory 214168 kb
Host smart-8e4079c7-7f95-4063-a54d-0b194bdac474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301533633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1301533633
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.246686440
Short name T923
Test name
Test status
Simulation time 253317512 ps
CPU time 5.2 seconds
Started Feb 26 03:15:22 PM PST 24
Finished Feb 26 03:15:27 PM PST 24
Peak memory 220172 kb
Host smart-57553338-754b-4be5-aeeb-09e00b2730e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246686440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.246686440
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3459602161
Short name T797
Test name
Test status
Simulation time 165416840 ps
CPU time 4.21 seconds
Started Feb 26 03:15:03 PM PST 24
Finished Feb 26 03:15:07 PM PST 24
Peak memory 220124 kb
Host smart-48dea0a6-a6a7-42da-92b7-f41939eaa5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459602161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3459602161
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1634217140
Short name T680
Test name
Test status
Simulation time 368196683 ps
CPU time 9.39 seconds
Started Feb 26 03:15:12 PM PST 24
Finished Feb 26 03:15:22 PM PST 24
Peak memory 208652 kb
Host smart-33f5a169-8b50-408c-81d5-ea072a604532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634217140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1634217140
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1300144742
Short name T544
Test name
Test status
Simulation time 982823799 ps
CPU time 9.68 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:19 PM PST 24
Peak memory 207956 kb
Host smart-71378852-fd86-433d-b1ca-c4e61793d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300144742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1300144742
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3091537416
Short name T186
Test name
Test status
Simulation time 335025762 ps
CPU time 3.98 seconds
Started Feb 26 03:15:10 PM PST 24
Finished Feb 26 03:15:14 PM PST 24
Peak memory 208948 kb
Host smart-6f2764fd-4d77-4ffd-8662-ba9676d51df9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091537416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3091537416
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3986967796
Short name T891
Test name
Test status
Simulation time 1054802848 ps
CPU time 33.87 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 208932 kb
Host smart-73c087e5-b2f3-47c1-bc05-9256f21f46be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986967796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3986967796
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1206360000
Short name T646
Test name
Test status
Simulation time 373473051 ps
CPU time 3.54 seconds
Started Feb 26 03:15:08 PM PST 24
Finished Feb 26 03:15:12 PM PST 24
Peak memory 215680 kb
Host smart-73bae6da-0f74-4625-9b04-4b09497451c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206360000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1206360000
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3477703126
Short name T176
Test name
Test status
Simulation time 83670564 ps
CPU time 1.84 seconds
Started Feb 26 03:15:21 PM PST 24
Finished Feb 26 03:15:23 PM PST 24
Peak memory 207064 kb
Host smart-9605c097-fd16-4ccf-af2c-6a439973f11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477703126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3477703126
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3555786895
Short name T871
Test name
Test status
Simulation time 130508069 ps
CPU time 4.01 seconds
Started Feb 26 03:15:08 PM PST 24
Finished Feb 26 03:15:12 PM PST 24
Peak memory 222576 kb
Host smart-5ca26325-5890-406b-bb80-042f4fdca2ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555786895 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3555786895
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2842662121
Short name T589
Test name
Test status
Simulation time 64682279 ps
CPU time 1.57 seconds
Started Feb 26 03:15:11 PM PST 24
Finished Feb 26 03:15:13 PM PST 24
Peak memory 209636 kb
Host smart-9dbdf0a0-0611-40b3-b618-4036105c82df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842662121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2842662121
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.556070901
Short name T1035
Test name
Test status
Simulation time 12970552 ps
CPU time 0.75 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:19 PM PST 24
Peak memory 205812 kb
Host smart-56bdcdaa-06f7-4ace-bcc8-e0aa09aad2f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556070901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.556070901
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2790193066
Short name T959
Test name
Test status
Simulation time 189580496 ps
CPU time 3.76 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:22 PM PST 24
Peak memory 214332 kb
Host smart-077608bd-9343-487b-8cc1-ee964dcb7391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790193066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2790193066
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.12071393
Short name T601
Test name
Test status
Simulation time 78653182 ps
CPU time 2.59 seconds
Started Feb 26 03:15:21 PM PST 24
Finished Feb 26 03:15:24 PM PST 24
Peak memory 207368 kb
Host smart-7110dced-4138-449f-837b-5c291493be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12071393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.12071393
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.330573307
Short name T864
Test name
Test status
Simulation time 380190602 ps
CPU time 6.46 seconds
Started Feb 26 03:15:19 PM PST 24
Finished Feb 26 03:15:25 PM PST 24
Peak memory 220160 kb
Host smart-09328dca-137a-4e31-9e76-c1c42984d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330573307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.330573307
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2218138962
Short name T190
Test name
Test status
Simulation time 1468595289 ps
CPU time 57.39 seconds
Started Feb 26 03:15:15 PM PST 24
Finished Feb 26 03:16:13 PM PST 24
Peak memory 222928 kb
Host smart-f1a4af06-9c47-436b-bbeb-fa597147e91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218138962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2218138962
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.661065753
Short name T759
Test name
Test status
Simulation time 59974182 ps
CPU time 3.45 seconds
Started Feb 26 03:15:11 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 209716 kb
Host smart-7647eae3-a4f2-4036-b027-f0dcfdf073ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661065753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.661065753
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1093304836
Short name T245
Test name
Test status
Simulation time 78489571 ps
CPU time 4.22 seconds
Started Feb 26 03:15:10 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 214404 kb
Host smart-ab54cb88-0403-4ff8-8a1d-04b1db3eaf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093304836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1093304836
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.337068047
Short name T583
Test name
Test status
Simulation time 435471634 ps
CPU time 10.81 seconds
Started Feb 26 03:15:12 PM PST 24
Finished Feb 26 03:15:23 PM PST 24
Peak memory 208536 kb
Host smart-5e3183a4-a391-4d8c-a8d8-affd202aabfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337068047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.337068047
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4013608622
Short name T595
Test name
Test status
Simulation time 908984980 ps
CPU time 21.54 seconds
Started Feb 26 03:15:12 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 208836 kb
Host smart-bd70d644-0e7a-4957-aecf-87c4b9bf75d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013608622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4013608622
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.635905305
Short name T986
Test name
Test status
Simulation time 4283209108 ps
CPU time 29.37 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:38 PM PST 24
Peak memory 208756 kb
Host smart-2e37fbbf-ca84-4885-a7f5-55ad87d28f1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635905305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.635905305
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3231380385
Short name T720
Test name
Test status
Simulation time 45437205 ps
CPU time 1.85 seconds
Started Feb 26 03:15:19 PM PST 24
Finished Feb 26 03:15:21 PM PST 24
Peak memory 206920 kb
Host smart-3ddf0dfb-87bf-4135-b984-be6e90efff68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231380385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3231380385
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.169905586
Short name T592
Test name
Test status
Simulation time 1927593836 ps
CPU time 23.16 seconds
Started Feb 26 03:15:26 PM PST 24
Finished Feb 26 03:15:49 PM PST 24
Peak memory 209476 kb
Host smart-387c744d-e4f0-45c5-a8a5-992105aaedd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169905586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.169905586
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2873332761
Short name T588
Test name
Test status
Simulation time 575351764 ps
CPU time 5.69 seconds
Started Feb 26 03:15:09 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 208324 kb
Host smart-7e8b5f2d-9b0c-4e7e-9d88-2c51c5355054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873332761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2873332761
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3547927703
Short name T976
Test name
Test status
Simulation time 433408723 ps
CPU time 12.11 seconds
Started Feb 26 03:15:28 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 217196 kb
Host smart-440c3449-b833-4062-8747-ab4e29e28fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547927703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3547927703
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3151164814
Short name T937
Test name
Test status
Simulation time 298228998 ps
CPU time 5.48 seconds
Started Feb 26 03:15:27 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 222560 kb
Host smart-20f0acfe-5b7c-4022-92a9-bdf3197060c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151164814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3151164814
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2986072497
Short name T829
Test name
Test status
Simulation time 54301280 ps
CPU time 3.63 seconds
Started Feb 26 03:15:20 PM PST 24
Finished Feb 26 03:15:23 PM PST 24
Peak memory 218140 kb
Host smart-c405dc20-22da-495f-b5a9-68b801a7f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986072497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2986072497
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1152400645
Short name T734
Test name
Test status
Simulation time 19539073 ps
CPU time 0.83 seconds
Started Feb 26 03:15:26 PM PST 24
Finished Feb 26 03:15:27 PM PST 24
Peak memory 205900 kb
Host smart-98dfc018-54bb-4259-b643-3d622c69248f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152400645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1152400645
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3566338468
Short name T335
Test name
Test status
Simulation time 436958835 ps
CPU time 9.79 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:41 PM PST 24
Peak memory 215432 kb
Host smart-542abacc-c531-421d-a1c3-19a5c05875e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566338468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3566338468
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1127488801
Short name T30
Test name
Test status
Simulation time 679486744 ps
CPU time 8.48 seconds
Started Feb 26 03:15:25 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 208984 kb
Host smart-76eae89e-bb7d-453f-a547-d9d3ea9ae981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127488801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1127488801
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1370801276
Short name T683
Test name
Test status
Simulation time 104406312 ps
CPU time 3.92 seconds
Started Feb 26 03:15:24 PM PST 24
Finished Feb 26 03:15:28 PM PST 24
Peak memory 210004 kb
Host smart-141890ef-33ad-4b89-b13c-a6dba23c4aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370801276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1370801276
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.99451800
Short name T775
Test name
Test status
Simulation time 1919580904 ps
CPU time 24.18 seconds
Started Feb 26 03:15:16 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 209580 kb
Host smart-8427e17b-d208-41c2-8e00-f83e15a29fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99451800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.99451800
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2260299441
Short name T3
Test name
Test status
Simulation time 410450704 ps
CPU time 4.13 seconds
Started Feb 26 03:15:25 PM PST 24
Finished Feb 26 03:15:29 PM PST 24
Peak memory 209560 kb
Host smart-9266ac40-7071-49cf-a272-90a3805f6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260299441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2260299441
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1298032922
Short name T181
Test name
Test status
Simulation time 54874823 ps
CPU time 2.99 seconds
Started Feb 26 03:15:25 PM PST 24
Finished Feb 26 03:15:28 PM PST 24
Peak memory 214276 kb
Host smart-95999a39-7afd-4625-b5a4-57cbd74784c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298032922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1298032922
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2811898617
Short name T713
Test name
Test status
Simulation time 41771998 ps
CPU time 1.81 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:20 PM PST 24
Peak memory 206804 kb
Host smart-c94be8c3-4ac8-49da-83ab-0f6ef5b883e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811898617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2811898617
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1984510032
Short name T952
Test name
Test status
Simulation time 874713272 ps
CPU time 7.1 seconds
Started Feb 26 03:15:18 PM PST 24
Finished Feb 26 03:15:25 PM PST 24
Peak memory 208544 kb
Host smart-61495237-9466-4597-a02f-fd15ce6dab99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984510032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1984510032
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.107918095
Short name T950
Test name
Test status
Simulation time 65685934 ps
CPU time 2.53 seconds
Started Feb 26 03:15:25 PM PST 24
Finished Feb 26 03:15:27 PM PST 24
Peak memory 206716 kb
Host smart-fff4a4e0-0475-4e92-ba6b-c91af71eef4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107918095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.107918095
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.622822257
Short name T189
Test name
Test status
Simulation time 101603296 ps
CPU time 2.15 seconds
Started Feb 26 03:15:23 PM PST 24
Finished Feb 26 03:15:25 PM PST 24
Peak memory 208624 kb
Host smart-f87c7936-94c8-4331-a406-8a8ee7be5609
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622822257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.622822257
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1041276577
Short name T1023
Test name
Test status
Simulation time 494232609 ps
CPU time 15.91 seconds
Started Feb 26 03:15:24 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 209740 kb
Host smart-bf1da81e-a763-4e0e-999e-3735a5b03efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041276577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1041276577
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2417886794
Short name T983
Test name
Test status
Simulation time 181276771 ps
CPU time 2.4 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:34 PM PST 24
Peak memory 206696 kb
Host smart-180f7cb7-2b2d-4015-a7fb-dcbb870ef9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417886794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2417886794
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.174170654
Short name T348
Test name
Test status
Simulation time 669901543 ps
CPU time 9.3 seconds
Started Feb 26 03:15:27 PM PST 24
Finished Feb 26 03:15:37 PM PST 24
Peak memory 221520 kb
Host smart-bd1b0621-f4fc-4a9a-a032-14cec27759ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174170654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.174170654
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3482942780
Short name T677
Test name
Test status
Simulation time 526415445 ps
CPU time 8.83 seconds
Started Feb 26 03:15:24 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 222720 kb
Host smart-3cb2300d-13c1-4a33-ae95-be95c91796b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482942780 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3482942780
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3863266809
Short name T752
Test name
Test status
Simulation time 770463352 ps
CPU time 9.08 seconds
Started Feb 26 03:15:24 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 214316 kb
Host smart-2d85cd8e-1cc9-40f1-bb4f-1111eef05f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863266809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3863266809
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.88203948
Short name T599
Test name
Test status
Simulation time 214246318 ps
CPU time 1.55 seconds
Started Feb 26 03:15:23 PM PST 24
Finished Feb 26 03:15:24 PM PST 24
Peak memory 208600 kb
Host smart-e2e08c85-39d3-4412-ac58-cf9948a1d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88203948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.88203948
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3029879830
Short name T645
Test name
Test status
Simulation time 33887866 ps
CPU time 0.75 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:31 PM PST 24
Peak memory 205840 kb
Host smart-c6ce249c-3ad7-411c-b63b-000b2c35555c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029879830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3029879830
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3121255658
Short name T554
Test name
Test status
Simulation time 357752121 ps
CPU time 2.68 seconds
Started Feb 26 03:15:26 PM PST 24
Finished Feb 26 03:15:29 PM PST 24
Peak memory 208904 kb
Host smart-8b2dd46f-9596-4a55-b4f7-566992ef8c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121255658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3121255658
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2271713382
Short name T23
Test name
Test status
Simulation time 164261346 ps
CPU time 5.72 seconds
Started Feb 26 03:15:26 PM PST 24
Finished Feb 26 03:15:32 PM PST 24
Peak memory 208748 kb
Host smart-a4938115-52d7-476f-b943-fa006ebe385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271713382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2271713382
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1187771910
Short name T45
Test name
Test status
Simulation time 79976402 ps
CPU time 2.7 seconds
Started Feb 26 03:15:29 PM PST 24
Finished Feb 26 03:15:32 PM PST 24
Peak memory 216740 kb
Host smart-ae126db0-fcfb-414b-9a7f-0905661f8c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187771910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1187771910
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3608153428
Short name T883
Test name
Test status
Simulation time 49533753 ps
CPU time 3.53 seconds
Started Feb 26 03:15:23 PM PST 24
Finished Feb 26 03:15:26 PM PST 24
Peak memory 218524 kb
Host smart-5e3c8da2-e92f-4e6e-8b34-8b97f8146a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608153428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3608153428
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3429115542
Short name T776
Test name
Test status
Simulation time 57873972 ps
CPU time 3.07 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:35 PM PST 24
Peak memory 208012 kb
Host smart-02259cc2-9203-4ab0-b158-fd330b1e109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429115542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3429115542
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3067824650
Short name T97
Test name
Test status
Simulation time 156366139 ps
CPU time 5 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:37 PM PST 24
Peak memory 208364 kb
Host smart-295de42e-347a-4ed5-a39f-f6b0ba065ad4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067824650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3067824650
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2859677849
Short name T725
Test name
Test status
Simulation time 487425524 ps
CPU time 7.61 seconds
Started Feb 26 03:15:22 PM PST 24
Finished Feb 26 03:15:30 PM PST 24
Peak memory 207976 kb
Host smart-209cc703-623a-499d-bf8d-fe1181fd15ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859677849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2859677849
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1724959151
Short name T714
Test name
Test status
Simulation time 107082472 ps
CPU time 2.3 seconds
Started Feb 26 03:15:23 PM PST 24
Finished Feb 26 03:15:25 PM PST 24
Peak memory 208736 kb
Host smart-3dafd9fc-dcdc-4cb3-8ec4-b67a79cc4b8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724959151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1724959151
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.845649425
Short name T1051
Test name
Test status
Simulation time 155393849 ps
CPU time 3.72 seconds
Started Feb 26 03:15:27 PM PST 24
Finished Feb 26 03:15:31 PM PST 24
Peak memory 209652 kb
Host smart-f59853fe-5dc7-4104-9bcc-1c9042a6c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845649425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.845649425
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.653531642
Short name T543
Test name
Test status
Simulation time 1831996603 ps
CPU time 4.95 seconds
Started Feb 26 03:15:28 PM PST 24
Finished Feb 26 03:15:33 PM PST 24
Peak memory 206800 kb
Host smart-2503675d-444d-4f00-b6db-d96ce2e323e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653531642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.653531642
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.63301804
Short name T220
Test name
Test status
Simulation time 2177914691 ps
CPU time 32.29 seconds
Started Feb 26 03:15:26 PM PST 24
Finished Feb 26 03:15:59 PM PST 24
Peak memory 222540 kb
Host smart-ee434996-fd8c-4007-82b7-709cbf65fe1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63301804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.63301804
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.721582348
Short name T1026
Test name
Test status
Simulation time 297720984 ps
CPU time 5.03 seconds
Started Feb 26 03:15:29 PM PST 24
Finished Feb 26 03:15:34 PM PST 24
Peak memory 219424 kb
Host smart-f5d9cd4b-a525-4167-a87f-8d2c8e2e934e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721582348 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.721582348
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2450167310
Short name T880
Test name
Test status
Simulation time 271305581 ps
CPU time 9.73 seconds
Started Feb 26 03:15:30 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 218304 kb
Host smart-8b2a0f69-1dd8-4a94-89a0-6930744aa06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450167310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2450167310
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3476522883
Short name T854
Test name
Test status
Simulation time 62251831 ps
CPU time 2.82 seconds
Started Feb 26 03:15:25 PM PST 24
Finished Feb 26 03:15:28 PM PST 24
Peak memory 209820 kb
Host smart-05265045-a15e-4d90-8c24-02026595f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476522883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3476522883
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1772073133
Short name T600
Test name
Test status
Simulation time 35457233 ps
CPU time 0.85 seconds
Started Feb 26 03:15:33 PM PST 24
Finished Feb 26 03:15:34 PM PST 24
Peak memory 205876 kb
Host smart-1538eec7-12e0-4a9e-800b-21f45d42bc3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772073133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1772073133
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3218499742
Short name T1047
Test name
Test status
Simulation time 217341121 ps
CPU time 6.07 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:37 PM PST 24
Peak memory 209476 kb
Host smart-f1b74aa4-7b4b-402e-81e5-b92442f9efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218499742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3218499742
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.450552916
Short name T709
Test name
Test status
Simulation time 3221900978 ps
CPU time 30.52 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 208916 kb
Host smart-fecf414a-1f32-4e52-98fb-b0a9e7ebba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450552916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.450552916
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.126744605
Short name T262
Test name
Test status
Simulation time 229919192 ps
CPU time 6.53 seconds
Started Feb 26 03:15:32 PM PST 24
Finished Feb 26 03:15:39 PM PST 24
Peak memory 214272 kb
Host smart-a3765e35-2062-4f1e-ad82-cd22a85f5833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126744605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.126744605
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1862121574
Short name T52
Test name
Test status
Simulation time 306805125 ps
CPU time 4.17 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 209652 kb
Host smart-dd15062e-2d88-4153-9bd2-39b99ff36183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862121574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1862121574
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.856340900
Short name T641
Test name
Test status
Simulation time 393112534 ps
CPU time 6.67 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 214284 kb
Host smart-4cca753b-1afc-4261-b6c2-35004014d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856340900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.856340900
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2377977938
Short name T785
Test name
Test status
Simulation time 175898228 ps
CPU time 3.57 seconds
Started Feb 26 03:15:32 PM PST 24
Finished Feb 26 03:15:36 PM PST 24
Peak memory 208904 kb
Host smart-eda57a8a-df93-485f-b572-236c64ee973c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377977938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2377977938
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1228980060
Short name T264
Test name
Test status
Simulation time 250099831 ps
CPU time 7.58 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:44 PM PST 24
Peak memory 208360 kb
Host smart-29122b75-e971-4533-8b19-e8fc60d3bc2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228980060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1228980060
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2294179063
Short name T999
Test name
Test status
Simulation time 75547206 ps
CPU time 1.96 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:34 PM PST 24
Peak memory 206888 kb
Host smart-0e86442b-6b8a-445c-9987-612dbdab12b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294179063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2294179063
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3892570163
Short name T895
Test name
Test status
Simulation time 22799187 ps
CPU time 1.87 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:38 PM PST 24
Peak memory 206876 kb
Host smart-a7d24def-c8ce-4bc5-813b-0ceea394fef4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892570163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3892570163
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.959637907
Short name T1009
Test name
Test status
Simulation time 128079233 ps
CPU time 3.22 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:35 PM PST 24
Peak memory 209812 kb
Host smart-33b52da7-8b3e-42d1-913a-869ee7f02523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959637907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.959637907
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1343287584
Short name T384
Test name
Test status
Simulation time 593072200 ps
CPU time 2.93 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 206720 kb
Host smart-ab720971-b25e-4479-bb55-3cb8829f0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343287584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1343287584
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1324032561
Short name T204
Test name
Test status
Simulation time 1394226020 ps
CPU time 26.46 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 214892 kb
Host smart-ac5cbb1b-e9fc-4881-899a-e001b3f28511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324032561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1324032561
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.886288486
Short name T376
Test name
Test status
Simulation time 704748711 ps
CPU time 4.67 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:42 PM PST 24
Peak memory 222576 kb
Host smart-24a424f1-7717-4ad5-a81c-e684c45346aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886288486 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.886288486
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3355569382
Short name T191
Test name
Test status
Simulation time 1310902589 ps
CPU time 19.73 seconds
Started Feb 26 03:15:32 PM PST 24
Finished Feb 26 03:15:52 PM PST 24
Peak memory 207648 kb
Host smart-4971e0c6-def8-4a22-8979-da3e8d8d9dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355569382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3355569382
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1671675922
Short name T570
Test name
Test status
Simulation time 205477892 ps
CPU time 2.74 seconds
Started Feb 26 03:15:31 PM PST 24
Finished Feb 26 03:15:35 PM PST 24
Peak memory 209964 kb
Host smart-a378f636-e5d7-4acb-939b-4e905c1dd89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671675922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1671675922
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4219358168
Short name T748
Test name
Test status
Simulation time 10101541 ps
CPU time 0.84 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:39 PM PST 24
Peak memory 205756 kb
Host smart-0c4fe0dd-15ce-4f21-afee-789e04c03822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219358168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4219358168
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.68064174
Short name T349
Test name
Test status
Simulation time 3015430220 ps
CPU time 17.59 seconds
Started Feb 26 03:15:41 PM PST 24
Finished Feb 26 03:15:59 PM PST 24
Peak memory 214308 kb
Host smart-9320a72c-c7f5-4fd9-a3aa-cb18d31a9671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68064174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.68064174
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.731462317
Short name T31
Test name
Test status
Simulation time 2097333717 ps
CPU time 18.3 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:56 PM PST 24
Peak memory 222812 kb
Host smart-f92e180e-6217-4c50-829f-aa3bace22789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731462317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.731462317
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3727239026
Short name T628
Test name
Test status
Simulation time 196604043 ps
CPU time 2.59 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:39 PM PST 24
Peak memory 207068 kb
Host smart-95e09785-a9da-4543-9f7a-204be7a75589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727239026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3727239026
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3058660711
Short name T370
Test name
Test status
Simulation time 280157737 ps
CPU time 4.2 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 220272 kb
Host smart-90f7ff90-1926-484e-8af3-5464ae1aa1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058660711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3058660711
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.51929406
Short name T96
Test name
Test status
Simulation time 114684824 ps
CPU time 3.43 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 209144 kb
Host smart-96f05130-cd17-4950-9739-468228a8b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51929406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.51929406
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3944568221
Short name T929
Test name
Test status
Simulation time 1810359371 ps
CPU time 17.86 seconds
Started Feb 26 03:15:36 PM PST 24
Finished Feb 26 03:15:54 PM PST 24
Peak memory 208716 kb
Host smart-8c720fc1-e509-489f-b640-db8cbc9449d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944568221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3944568221
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3956488604
Short name T246
Test name
Test status
Simulation time 58402840 ps
CPU time 3.03 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:40 PM PST 24
Peak memory 208832 kb
Host smart-f9b5f18f-b707-42e9-a065-db88a01c7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956488604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3956488604
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2375322266
Short name T640
Test name
Test status
Simulation time 135783983 ps
CPU time 2.69 seconds
Started Feb 26 03:15:42 PM PST 24
Finished Feb 26 03:15:46 PM PST 24
Peak memory 208300 kb
Host smart-2bd745ab-18c3-449d-b027-a5d588d56d6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375322266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2375322266
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1481212880
Short name T1014
Test name
Test status
Simulation time 4583902313 ps
CPU time 81.84 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:17:00 PM PST 24
Peak memory 207964 kb
Host smart-a8dabae4-8837-4c6e-aa16-0acec001c86f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481212880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1481212880
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2074677218
Short name T629
Test name
Test status
Simulation time 474283708 ps
CPU time 15.38 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:54 PM PST 24
Peak memory 208288 kb
Host smart-9a406187-3126-4423-a015-e8782404d59d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074677218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2074677218
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1323472620
Short name T184
Test name
Test status
Simulation time 525529400 ps
CPU time 3.96 seconds
Started Feb 26 03:15:33 PM PST 24
Finished Feb 26 03:15:37 PM PST 24
Peak memory 214280 kb
Host smart-0b34c624-73fd-4187-8355-65ea1550c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323472620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1323472620
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2953205623
Short name T852
Test name
Test status
Simulation time 137814617 ps
CPU time 4.95 seconds
Started Feb 26 03:15:37 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 206736 kb
Host smart-9ae4c661-6543-4f34-b0f7-53a9e12bd752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953205623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2953205623
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2443623497
Short name T67
Test name
Test status
Simulation time 3008546101 ps
CPU time 55.97 seconds
Started Feb 26 03:15:35 PM PST 24
Finished Feb 26 03:16:31 PM PST 24
Peak memory 222560 kb
Host smart-6c4acbae-c9f8-44b0-8986-b0a0c31ac7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443623497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2443623497
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1776070486
Short name T210
Test name
Test status
Simulation time 301452708 ps
CPU time 6.22 seconds
Started Feb 26 03:15:35 PM PST 24
Finished Feb 26 03:15:41 PM PST 24
Peak memory 220712 kb
Host smart-da47db11-bace-4eac-b8eb-ba09a0531d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776070486 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1776070486
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1913420841
Short name T2
Test name
Test status
Simulation time 255725459 ps
CPU time 7.4 seconds
Started Feb 26 03:15:35 PM PST 24
Finished Feb 26 03:15:42 PM PST 24
Peak memory 218192 kb
Host smart-ce96cf33-014d-4c95-b4ba-f593212150a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913420841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1913420841
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2768941752
Short name T156
Test name
Test status
Simulation time 43496266 ps
CPU time 1.8 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:39 PM PST 24
Peak memory 209904 kb
Host smart-9852208f-e2ce-4209-a3a8-d95ab39c6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768941752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2768941752
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3023998765
Short name T765
Test name
Test status
Simulation time 21292788 ps
CPU time 0.85 seconds
Started Feb 26 03:15:44 PM PST 24
Finished Feb 26 03:15:45 PM PST 24
Peak memory 205880 kb
Host smart-6219da61-3b7b-4976-95a8-2f1e5894c7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023998765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3023998765
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3988259937
Short name T329
Test name
Test status
Simulation time 208168491 ps
CPU time 2.72 seconds
Started Feb 26 03:15:39 PM PST 24
Finished Feb 26 03:15:42 PM PST 24
Peak memory 214376 kb
Host smart-b0782edd-59ec-4e37-bc7b-ba7d1e8d2856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988259937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3988259937
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.76602934
Short name T1065
Test name
Test status
Simulation time 60263668 ps
CPU time 2.17 seconds
Started Feb 26 03:15:40 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 207604 kb
Host smart-48920e59-ebed-4ccc-b859-bae88fdd07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76602934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.76602934
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1603079487
Short name T38
Test name
Test status
Simulation time 346458593 ps
CPU time 4.99 seconds
Started Feb 26 03:15:41 PM PST 24
Finished Feb 26 03:15:47 PM PST 24
Peak memory 222436 kb
Host smart-dfafcaad-ecfb-4cf2-bda0-80618c25dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603079487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1603079487
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1418275234
Short name T788
Test name
Test status
Simulation time 679603532 ps
CPU time 4.71 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 222364 kb
Host smart-d7c5f2f7-a37f-4cf0-9adc-16c1e9972dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418275234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1418275234
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3056159576
Short name T842
Test name
Test status
Simulation time 2038722636 ps
CPU time 66.72 seconds
Started Feb 26 03:15:42 PM PST 24
Finished Feb 26 03:16:49 PM PST 24
Peak memory 214264 kb
Host smart-7f650ab3-2ba3-419e-b44f-8b5c761c3e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056159576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3056159576
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1411437526
Short name T786
Test name
Test status
Simulation time 127405454 ps
CPU time 2.59 seconds
Started Feb 26 03:15:40 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 208628 kb
Host smart-2d8c95e2-0630-4463-acdb-62dab1e6aab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411437526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1411437526
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2687495150
Short name T644
Test name
Test status
Simulation time 1022530516 ps
CPU time 9.04 seconds
Started Feb 26 03:15:41 PM PST 24
Finished Feb 26 03:15:51 PM PST 24
Peak memory 207976 kb
Host smart-ae7d4134-f2ac-4f4d-ba13-da5900dd9e1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687495150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2687495150
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3505369587
Short name T848
Test name
Test status
Simulation time 807548703 ps
CPU time 7.33 seconds
Started Feb 26 03:15:39 PM PST 24
Finished Feb 26 03:15:46 PM PST 24
Peak memory 208720 kb
Host smart-f4431944-d628-41cb-95cf-380ab58a8678
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505369587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3505369587
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3377055859
Short name T1064
Test name
Test status
Simulation time 327040156 ps
CPU time 4.1 seconds
Started Feb 26 03:15:47 PM PST 24
Finished Feb 26 03:15:51 PM PST 24
Peak memory 208528 kb
Host smart-1e8ece3d-2cea-46d7-b8d5-93840b2e074a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377055859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3377055859
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1889083674
Short name T611
Test name
Test status
Simulation time 187949833 ps
CPU time 4.51 seconds
Started Feb 26 03:15:44 PM PST 24
Finished Feb 26 03:15:48 PM PST 24
Peak memory 218300 kb
Host smart-7f77cc27-4b62-4b8e-99f6-81c16c7190ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889083674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1889083674
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1334247487
Short name T879
Test name
Test status
Simulation time 185143366 ps
CPU time 4.13 seconds
Started Feb 26 03:15:38 PM PST 24
Finished Feb 26 03:15:43 PM PST 24
Peak memory 207764 kb
Host smart-1b4c897d-e6af-454f-97d3-5f028571f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334247487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1334247487
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4224060170
Short name T198
Test name
Test status
Simulation time 180462909 ps
CPU time 4.42 seconds
Started Feb 26 03:15:43 PM PST 24
Finished Feb 26 03:15:47 PM PST 24
Peak memory 219592 kb
Host smart-998094b1-6d2c-4a0c-a077-e03893b03c37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224060170 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4224060170
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1849930021
Short name T875
Test name
Test status
Simulation time 1574190321 ps
CPU time 31.08 seconds
Started Feb 26 03:15:45 PM PST 24
Finished Feb 26 03:16:16 PM PST 24
Peak memory 209516 kb
Host smart-467533a8-a625-4e81-86e1-378dcc181942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849930021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1849930021
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2053617134
Short name T763
Test name
Test status
Simulation time 29948250 ps
CPU time 1.71 seconds
Started Feb 26 03:15:44 PM PST 24
Finished Feb 26 03:15:46 PM PST 24
Peak memory 209800 kb
Host smart-e130c073-452e-49f3-b140-60bb2fb61659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053617134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2053617134
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.245001537
Short name T771
Test name
Test status
Simulation time 46902552 ps
CPU time 0.81 seconds
Started Feb 26 03:15:55 PM PST 24
Finished Feb 26 03:15:56 PM PST 24
Peak memory 205844 kb
Host smart-997bf32e-cdfd-4ca1-8881-4d423e3c0502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245001537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.245001537
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2232456158
Short name T393
Test name
Test status
Simulation time 32610446 ps
CPU time 2.57 seconds
Started Feb 26 03:15:41 PM PST 24
Finished Feb 26 03:15:45 PM PST 24
Peak memory 214324 kb
Host smart-5e9a2946-5de2-4716-a305-2376fa37c81c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232456158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2232456158
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.673725487
Short name T711
Test name
Test status
Simulation time 2645787381 ps
CPU time 13.65 seconds
Started Feb 26 03:15:44 PM PST 24
Finished Feb 26 03:15:58 PM PST 24
Peak memory 209488 kb
Host smart-2b0df672-9c11-4b78-b22f-2a03b9e202e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673725487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.673725487
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.907265855
Short name T197
Test name
Test status
Simulation time 72748774 ps
CPU time 2.91 seconds
Started Feb 26 03:15:51 PM PST 24
Finished Feb 26 03:15:55 PM PST 24
Peak memory 220144 kb
Host smart-8861161b-0359-4c50-8f5c-6c2f4f3e5e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907265855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.907265855
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1251180742
Short name T792
Test name
Test status
Simulation time 764493460 ps
CPU time 5.11 seconds
Started Feb 26 03:15:47 PM PST 24
Finished Feb 26 03:15:52 PM PST 24
Peak memory 207328 kb
Host smart-3d8afeb0-2501-44b4-98f2-e177878a00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251180742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1251180742
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3251168691
Short name T44
Test name
Test status
Simulation time 1822955897 ps
CPU time 52.3 seconds
Started Feb 26 03:15:44 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 207908 kb
Host smart-80798fed-bbf7-44bd-905d-325cb5f2fcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251168691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3251168691
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3793856139
Short name T798
Test name
Test status
Simulation time 205911586 ps
CPU time 3.17 seconds
Started Feb 26 03:15:46 PM PST 24
Finished Feb 26 03:15:49 PM PST 24
Peak memory 206840 kb
Host smart-00263394-37ee-4641-84b5-c7347c182d28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793856139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3793856139
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.393300583
Short name T806
Test name
Test status
Simulation time 52283535 ps
CPU time 2.85 seconds
Started Feb 26 03:15:43 PM PST 24
Finished Feb 26 03:15:46 PM PST 24
Peak memory 206984 kb
Host smart-636a072d-30f7-4ab2-98b1-29ceb3e9fb51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393300583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.393300583
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2411027506
Short name T693
Test name
Test status
Simulation time 971645860 ps
CPU time 6.62 seconds
Started Feb 26 03:15:47 PM PST 24
Finished Feb 26 03:15:53 PM PST 24
Peak memory 207744 kb
Host smart-449e3a74-5895-461a-87ff-4a6bc70d1657
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411027506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2411027506
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1189623581
Short name T358
Test name
Test status
Simulation time 421267189 ps
CPU time 4.72 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:04 PM PST 24
Peak memory 218344 kb
Host smart-c0318b6b-fb0d-4d24-b70f-8add818814c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189623581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1189623581
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2591385423
Short name T552
Test name
Test status
Simulation time 45647309 ps
CPU time 1.88 seconds
Started Feb 26 03:15:42 PM PST 24
Finished Feb 26 03:15:45 PM PST 24
Peak memory 208268 kb
Host smart-9dc8d725-9a87-4c53-bc7a-30e4d5dd11f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591385423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2591385423
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.4020339254
Short name T195
Test name
Test status
Simulation time 90003421 ps
CPU time 6.33 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:05 PM PST 24
Peak memory 219676 kb
Host smart-ebfb0c4a-20a2-465b-9f0b-7203a520c0ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020339254 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.4020339254
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.573023370
Short name T647
Test name
Test status
Simulation time 199980210 ps
CPU time 4.22 seconds
Started Feb 26 03:15:53 PM PST 24
Finished Feb 26 03:15:57 PM PST 24
Peak memory 218216 kb
Host smart-c69d0ad6-cac9-4907-84c3-1d683c133daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573023370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.573023370
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3039036616
Short name T154
Test name
Test status
Simulation time 104796343 ps
CPU time 2.9 seconds
Started Feb 26 03:15:58 PM PST 24
Finished Feb 26 03:16:01 PM PST 24
Peak memory 210104 kb
Host smart-d841072d-3ea5-4a63-b580-856c93c09599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039036616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3039036616
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1263606117
Short name T795
Test name
Test status
Simulation time 21344661 ps
CPU time 0.85 seconds
Started Feb 26 03:16:05 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 205836 kb
Host smart-4cc7bc8e-c1a2-4692-b9a2-68de0af87d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263606117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1263606117
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1397496918
Short name T400
Test name
Test status
Simulation time 555590775 ps
CPU time 8.05 seconds
Started Feb 26 03:16:01 PM PST 24
Finished Feb 26 03:16:09 PM PST 24
Peak memory 214612 kb
Host smart-faa020cf-79f7-45b6-b199-a08d0363db57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397496918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1397496918
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4225460560
Short name T991
Test name
Test status
Simulation time 38547524 ps
CPU time 2.38 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:02 PM PST 24
Peak memory 219324 kb
Host smart-c949f59b-787e-4437-a6ce-8445366e2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225460560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4225460560
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3497265092
Short name T43
Test name
Test status
Simulation time 407551385 ps
CPU time 3.95 seconds
Started Feb 26 03:15:54 PM PST 24
Finished Feb 26 03:15:58 PM PST 24
Peak memory 208160 kb
Host smart-d2c1c860-6d47-4f64-9569-db6f31236eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497265092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3497265092
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1580226852
Short name T278
Test name
Test status
Simulation time 450045993 ps
CPU time 6.31 seconds
Started Feb 26 03:15:58 PM PST 24
Finished Feb 26 03:16:04 PM PST 24
Peak memory 208404 kb
Host smart-c36326b7-3ee8-443a-90ce-af64763f4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580226852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1580226852
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1294977897
Short name T1004
Test name
Test status
Simulation time 5363500430 ps
CPU time 11.17 seconds
Started Feb 26 03:15:53 PM PST 24
Finished Feb 26 03:16:05 PM PST 24
Peak memory 214296 kb
Host smart-d1ac6e10-cd80-415a-836d-f96bff33f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294977897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1294977897
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.416931158
Short name T227
Test name
Test status
Simulation time 1985986260 ps
CPU time 66.04 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:17:05 PM PST 24
Peak memory 222440 kb
Host smart-42002e0c-5ad8-4fd1-a233-6418665d59f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416931158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.416931158
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.552696550
Short name T911
Test name
Test status
Simulation time 180733568 ps
CPU time 5.5 seconds
Started Feb 26 03:15:54 PM PST 24
Finished Feb 26 03:16:00 PM PST 24
Peak memory 208240 kb
Host smart-1db40908-a715-4362-9945-7ad2c2b91709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552696550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.552696550
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3996459633
Short name T342
Test name
Test status
Simulation time 20786248209 ps
CPU time 56.84 seconds
Started Feb 26 03:15:54 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 208172 kb
Host smart-9e8a51ee-39b9-46e0-9936-9f627828b4a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996459633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3996459633
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3364542713
Short name T558
Test name
Test status
Simulation time 1097633479 ps
CPU time 8.67 seconds
Started Feb 26 03:15:53 PM PST 24
Finished Feb 26 03:16:01 PM PST 24
Peak memory 208808 kb
Host smart-6b6ed1ad-94ba-44a2-8b66-3b1094a75643
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364542713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3364542713
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2239676197
Short name T303
Test name
Test status
Simulation time 87023221 ps
CPU time 3.5 seconds
Started Feb 26 03:15:57 PM PST 24
Finished Feb 26 03:16:01 PM PST 24
Peak memory 206836 kb
Host smart-2b722027-f9fd-4a66-8111-54259e98c6f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239676197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2239676197
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4096363077
Short name T17
Test name
Test status
Simulation time 2352529851 ps
CPU time 6.22 seconds
Started Feb 26 03:16:06 PM PST 24
Finished Feb 26 03:16:13 PM PST 24
Peak memory 209156 kb
Host smart-15352397-07fe-4717-8907-d7cf29287877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096363077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4096363077
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1577142184
Short name T561
Test name
Test status
Simulation time 178568308 ps
CPU time 2.83 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 206676 kb
Host smart-42d64a7b-83de-4037-a83f-bdffcb1c6662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577142184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1577142184
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2969528803
Short name T881
Test name
Test status
Simulation time 124827044 ps
CPU time 9.14 seconds
Started Feb 26 03:15:56 PM PST 24
Finished Feb 26 03:16:05 PM PST 24
Peak memory 222640 kb
Host smart-d565bc5e-3166-4d0b-ac29-9710ab1d836a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969528803 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2969528803
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4145559456
Short name T960
Test name
Test status
Simulation time 447927959 ps
CPU time 3.98 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 209020 kb
Host smart-a6ea433b-383e-468e-91cc-94af790440a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145559456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4145559456
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1101498840
Short name T973
Test name
Test status
Simulation time 197668673 ps
CPU time 2.37 seconds
Started Feb 26 03:16:02 PM PST 24
Finished Feb 26 03:16:05 PM PST 24
Peak memory 209612 kb
Host smart-6b25dacd-37d6-4848-a208-f34f31df7754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101498840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1101498840
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2127876928
Short name T95
Test name
Test status
Simulation time 42121240 ps
CPU time 0.84 seconds
Started Feb 26 03:16:05 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 205840 kb
Host smart-4991c6b0-61fe-4d19-bd13-0648dcc4e4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127876928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2127876928
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2337029266
Short name T1016
Test name
Test status
Simulation time 46858530 ps
CPU time 2.51 seconds
Started Feb 26 03:16:04 PM PST 24
Finished Feb 26 03:16:07 PM PST 24
Peak memory 207596 kb
Host smart-fce0ffc1-82cb-400e-af37-f9b983c0ee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337029266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2337029266
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3482862503
Short name T724
Test name
Test status
Simulation time 164463038 ps
CPU time 5.5 seconds
Started Feb 26 03:16:04 PM PST 24
Finished Feb 26 03:16:10 PM PST 24
Peak memory 214260 kb
Host smart-05b0d41a-42b0-4ec5-a2a9-ee3964129447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482862503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3482862503
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.282015662
Short name T576
Test name
Test status
Simulation time 284381006 ps
CPU time 2.86 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 206136 kb
Host smart-b5ec5b1e-18e5-40ca-bc56-3b2cadcecadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282015662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.282015662
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.797819571
Short name T953
Test name
Test status
Simulation time 541507510 ps
CPU time 6.67 seconds
Started Feb 26 03:16:03 PM PST 24
Finished Feb 26 03:16:11 PM PST 24
Peak memory 208848 kb
Host smart-20aaf444-98c2-4f17-9800-6b4dd237ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797819571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.797819571
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1237413005
Short name T618
Test name
Test status
Simulation time 178147015 ps
CPU time 5.29 seconds
Started Feb 26 03:15:57 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 208376 kb
Host smart-86b43527-1c8f-4798-af10-4574f3d0f65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237413005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1237413005
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3646275263
Short name T910
Test name
Test status
Simulation time 26227333 ps
CPU time 2.14 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:02 PM PST 24
Peak memory 208632 kb
Host smart-7c2c44ac-5d2a-43e7-9898-78c066c5c334
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646275263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3646275263
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1143848514
Short name T957
Test name
Test status
Simulation time 75351246 ps
CPU time 3.33 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 208304 kb
Host smart-ed1bf6f1-d4f9-46eb-bba2-d2981a27fc7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143848514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1143848514
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.645658335
Short name T894
Test name
Test status
Simulation time 75693473 ps
CPU time 3.66 seconds
Started Feb 26 03:15:59 PM PST 24
Finished Feb 26 03:16:04 PM PST 24
Peak memory 206940 kb
Host smart-36432b82-0d49-4903-a2f4-370ef6015e63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645658335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.645658335
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4120896460
Short name T634
Test name
Test status
Simulation time 196131009 ps
CPU time 1.81 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:02 PM PST 24
Peak memory 207400 kb
Host smart-88dab743-fc1f-4d00-bb7c-f6ba849c9656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120896460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4120896460
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1589195225
Short name T828
Test name
Test status
Simulation time 587064751 ps
CPU time 6.43 seconds
Started Feb 26 03:15:53 PM PST 24
Finished Feb 26 03:16:00 PM PST 24
Peak memory 208680 kb
Host smart-5168ac6c-9519-4a13-b361-53572f4588c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589195225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1589195225
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2869021919
Short name T7
Test name
Test status
Simulation time 512688567 ps
CPU time 16.78 seconds
Started Feb 26 03:16:01 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 215928 kb
Host smart-261f94fe-69bb-4c86-bd10-7490c16c1e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869021919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2869021919
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1594169398
Short name T267
Test name
Test status
Simulation time 241016632 ps
CPU time 5.65 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:06 PM PST 24
Peak memory 218220 kb
Host smart-f26ceb2c-9b02-47d0-9e19-b1e1ab448048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594169398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1594169398
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4112631347
Short name T716
Test name
Test status
Simulation time 131860375 ps
CPU time 3.01 seconds
Started Feb 26 03:16:00 PM PST 24
Finished Feb 26 03:16:04 PM PST 24
Peak memory 210488 kb
Host smart-439c1268-8898-46fb-ac85-630098cbd85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112631347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4112631347
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1481566024
Short name T1030
Test name
Test status
Simulation time 186108226 ps
CPU time 0.93 seconds
Started Feb 26 03:14:13 PM PST 24
Finished Feb 26 03:14:15 PM PST 24
Peak memory 205768 kb
Host smart-7e57877f-3c08-4e5a-bc8a-6493c0422e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481566024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1481566024
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3971805809
Short name T653
Test name
Test status
Simulation time 205772844 ps
CPU time 2.41 seconds
Started Feb 26 03:14:07 PM PST 24
Finished Feb 26 03:14:09 PM PST 24
Peak memory 210092 kb
Host smart-c1d632c2-6818-4cf1-9ef8-f9540bdd9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971805809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3971805809
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2573384701
Short name T970
Test name
Test status
Simulation time 1963366940 ps
CPU time 9.08 seconds
Started Feb 26 03:14:05 PM PST 24
Finished Feb 26 03:14:15 PM PST 24
Peak memory 207968 kb
Host smart-e795ea30-2eb2-463d-98c6-1e237d119c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573384701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2573384701
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2908745688
Short name T936
Test name
Test status
Simulation time 308185216 ps
CPU time 9.06 seconds
Started Feb 26 03:14:07 PM PST 24
Finished Feb 26 03:14:16 PM PST 24
Peak memory 209940 kb
Host smart-4761eeb0-defa-4cfa-bb5e-1d1b9270dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908745688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2908745688
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3270783142
Short name T219
Test name
Test status
Simulation time 760230818 ps
CPU time 7.36 seconds
Started Feb 26 03:14:06 PM PST 24
Finished Feb 26 03:14:14 PM PST 24
Peak memory 214420 kb
Host smart-cce0cdfb-6350-45f7-bb4a-4b76aedc6510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270783142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3270783142
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3052370080
Short name T305
Test name
Test status
Simulation time 4632353709 ps
CPU time 50.32 seconds
Started Feb 26 03:14:09 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 209556 kb
Host smart-a80bf324-9aff-4758-a9eb-cc8cbbc42b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052370080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3052370080
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1942009149
Short name T827
Test name
Test status
Simulation time 202285811 ps
CPU time 2.94 seconds
Started Feb 26 03:14:07 PM PST 24
Finished Feb 26 03:14:10 PM PST 24
Peak memory 208384 kb
Host smart-179fadcc-86e2-4c39-acfe-a0ee4a2f7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942009149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1942009149
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1746930838
Short name T885
Test name
Test status
Simulation time 39233748 ps
CPU time 1.83 seconds
Started Feb 26 03:14:08 PM PST 24
Finished Feb 26 03:14:10 PM PST 24
Peak memory 207476 kb
Host smart-5275c7de-b876-4a1e-ac90-aa254d3357e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746930838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1746930838
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.987694551
Short name T604
Test name
Test status
Simulation time 3006291407 ps
CPU time 19.44 seconds
Started Feb 26 03:14:06 PM PST 24
Finished Feb 26 03:14:26 PM PST 24
Peak memory 208272 kb
Host smart-4041c9eb-a56c-4753-baa0-d155baacaa0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987694551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.987694551
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2207419760
Short name T998
Test name
Test status
Simulation time 93905305 ps
CPU time 4.55 seconds
Started Feb 26 03:14:05 PM PST 24
Finished Feb 26 03:14:10 PM PST 24
Peak memory 208936 kb
Host smart-ed3b467d-f666-48ad-bb3a-eaa2049ad8d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207419760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2207419760
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3783820856
Short name T385
Test name
Test status
Simulation time 49795694 ps
CPU time 2.75 seconds
Started Feb 26 03:14:10 PM PST 24
Finished Feb 26 03:14:13 PM PST 24
Peak memory 209124 kb
Host smart-bc8efbdb-1a96-47ef-b678-6167a05603d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783820856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3783820856
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2585908271
Short name T695
Test name
Test status
Simulation time 156191665 ps
CPU time 4.53 seconds
Started Feb 26 03:13:59 PM PST 24
Finished Feb 26 03:14:04 PM PST 24
Peak memory 206664 kb
Host smart-0052615e-ae7c-4705-aadc-c26f9117b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585908271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2585908271
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.267805944
Short name T772
Test name
Test status
Simulation time 200190672 ps
CPU time 3.26 seconds
Started Feb 26 03:14:09 PM PST 24
Finished Feb 26 03:14:13 PM PST 24
Peak memory 209516 kb
Host smart-47f66b80-656b-4265-b756-53c8a0b001b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267805944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.267805944
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.738427486
Short name T193
Test name
Test status
Simulation time 1288482485 ps
CPU time 14.34 seconds
Started Feb 26 03:14:09 PM PST 24
Finished Feb 26 03:14:23 PM PST 24
Peak memory 222484 kb
Host smart-a8575d7a-3ebe-4223-b54f-d66ecc20f227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738427486 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.738427486
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2802534161
Short name T308
Test name
Test status
Simulation time 163000095 ps
CPU time 4.11 seconds
Started Feb 26 03:14:05 PM PST 24
Finished Feb 26 03:14:09 PM PST 24
Peak memory 208972 kb
Host smart-d608be30-234e-4f2c-b557-7d6856b2f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802534161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2802534161
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.577791416
Short name T578
Test name
Test status
Simulation time 204125661 ps
CPU time 2.2 seconds
Started Feb 26 03:14:13 PM PST 24
Finished Feb 26 03:14:15 PM PST 24
Peak memory 209908 kb
Host smart-b5ac012e-c7aa-4a94-9e31-0b25a28d4ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577791416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.577791416
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2372451224
Short name T414
Test name
Test status
Simulation time 43709733 ps
CPU time 0.79 seconds
Started Feb 26 03:16:11 PM PST 24
Finished Feb 26 03:16:12 PM PST 24
Peak memory 205844 kb
Host smart-1409fd62-0579-409f-be01-edf523897efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372451224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2372451224
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3957301280
Short name T1003
Test name
Test status
Simulation time 359414503 ps
CPU time 3.08 seconds
Started Feb 26 03:16:11 PM PST 24
Finished Feb 26 03:16:14 PM PST 24
Peak memory 219728 kb
Host smart-98abdf34-703f-4562-8b0a-6a5533a55ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957301280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3957301280
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3523459369
Short name T635
Test name
Test status
Simulation time 1982915377 ps
CPU time 25.06 seconds
Started Feb 26 03:16:17 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 209920 kb
Host smart-619a08b2-d2c0-4e49-97ac-658feb92e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523459369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3523459369
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3707293360
Short name T346
Test name
Test status
Simulation time 222971672 ps
CPU time 3.87 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 221128 kb
Host smart-7221a038-ab10-453a-8382-720ae3123424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707293360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3707293360
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3476357396
Short name T235
Test name
Test status
Simulation time 2384814829 ps
CPU time 5.51 seconds
Started Feb 26 03:16:12 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 211260 kb
Host smart-aa2d695a-a57c-45d5-93e2-80e6f4b90411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476357396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3476357396
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3477674431
Short name T567
Test name
Test status
Simulation time 211460909 ps
CPU time 5.38 seconds
Started Feb 26 03:16:05 PM PST 24
Finished Feb 26 03:16:11 PM PST 24
Peak memory 220080 kb
Host smart-2bfb8cf7-1b61-4a96-a966-8cb25369fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477674431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3477674431
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.405168782
Short name T283
Test name
Test status
Simulation time 533085731 ps
CPU time 6.76 seconds
Started Feb 26 03:16:05 PM PST 24
Finished Feb 26 03:16:13 PM PST 24
Peak memory 208880 kb
Host smart-b1ea4b73-be77-4805-809e-e9fc5f4dc220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405168782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.405168782
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.714239465
Short name T318
Test name
Test status
Simulation time 204841403 ps
CPU time 2.79 seconds
Started Feb 26 03:16:08 PM PST 24
Finished Feb 26 03:16:11 PM PST 24
Peak memory 206732 kb
Host smart-57875bbc-f040-4e17-9470-63317bf1b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714239465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.714239465
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2415018595
Short name T630
Test name
Test status
Simulation time 461296183 ps
CPU time 3.92 seconds
Started Feb 26 03:16:11 PM PST 24
Finished Feb 26 03:16:15 PM PST 24
Peak memory 206936 kb
Host smart-b3668e42-2e4d-40f0-96a4-0033ccb90423
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415018595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2415018595
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3657779783
Short name T1010
Test name
Test status
Simulation time 92530627 ps
CPU time 2.63 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:16 PM PST 24
Peak memory 206824 kb
Host smart-b8486792-9938-4021-99f8-4dafa1187dc1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657779783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3657779783
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1085708312
Short name T573
Test name
Test status
Simulation time 32403216 ps
CPU time 2.31 seconds
Started Feb 26 03:16:06 PM PST 24
Finished Feb 26 03:16:09 PM PST 24
Peak memory 206752 kb
Host smart-29ecaf8d-8fab-44cd-8a78-a8f17d18eed2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085708312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1085708312
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.175005151
Short name T760
Test name
Test status
Simulation time 113383467 ps
CPU time 2.24 seconds
Started Feb 26 03:16:09 PM PST 24
Finished Feb 26 03:16:11 PM PST 24
Peak memory 209064 kb
Host smart-73691f76-b9eb-4fe7-bac1-a71089659ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175005151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.175005151
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3272735635
Short name T574
Test name
Test status
Simulation time 245990571 ps
CPU time 4.11 seconds
Started Feb 26 03:16:17 PM PST 24
Finished Feb 26 03:16:21 PM PST 24
Peak memory 206568 kb
Host smart-f9f430b8-eb29-41c6-97b2-501eb9a36c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272735635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3272735635
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2433279935
Short name T755
Test name
Test status
Simulation time 234386526 ps
CPU time 7.96 seconds
Started Feb 26 03:16:07 PM PST 24
Finished Feb 26 03:16:15 PM PST 24
Peak memory 220272 kb
Host smart-df3b4dfb-9d2f-4028-91cd-250b897786b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433279935 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2433279935
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.711111894
Short name T609
Test name
Test status
Simulation time 157913989 ps
CPU time 3.92 seconds
Started Feb 26 03:16:16 PM PST 24
Finished Feb 26 03:16:20 PM PST 24
Peak memory 207328 kb
Host smart-aa9e4986-1053-47f2-95af-f427b02ae094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711111894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.711111894
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2132598130
Short name T586
Test name
Test status
Simulation time 561483135 ps
CPU time 14.14 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:29 PM PST 24
Peak memory 211200 kb
Host smart-b6b0fa4a-591d-436b-bde6-ee26adb0dfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132598130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2132598130
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2666160515
Short name T75
Test name
Test status
Simulation time 52618568 ps
CPU time 0.77 seconds
Started Feb 26 03:16:14 PM PST 24
Finished Feb 26 03:16:15 PM PST 24
Peak memory 205476 kb
Host smart-73bb5701-30ea-42ae-b9f6-898342159881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666160515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2666160515
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3633011194
Short name T9
Test name
Test status
Simulation time 108812111 ps
CPU time 2.36 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:17 PM PST 24
Peak memory 208808 kb
Host smart-f4237771-9801-4680-9b8e-745b7f865d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633011194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3633011194
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2542827990
Short name T548
Test name
Test status
Simulation time 197944021 ps
CPU time 2.15 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:16 PM PST 24
Peak memory 218428 kb
Host smart-5f8ab590-8a27-41b6-adf5-9d233bdf0f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542827990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2542827990
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2515362907
Short name T632
Test name
Test status
Simulation time 122108377 ps
CPU time 4.32 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 221220 kb
Host smart-2b4469b1-f801-4a48-b125-5c996cea4aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515362907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2515362907
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.543700018
Short name T1036
Test name
Test status
Simulation time 170779514 ps
CPU time 2.78 seconds
Started Feb 26 03:16:14 PM PST 24
Finished Feb 26 03:16:17 PM PST 24
Peak memory 222572 kb
Host smart-28e44f53-f940-4e47-81b6-7b0f0ebb19d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543700018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.543700018
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2724237946
Short name T968
Test name
Test status
Simulation time 928879581 ps
CPU time 4.45 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 208156 kb
Host smart-743d5857-d67e-48b2-aa31-e254f568a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724237946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2724237946
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4075486988
Short name T619
Test name
Test status
Simulation time 252753096 ps
CPU time 3.31 seconds
Started Feb 26 03:16:07 PM PST 24
Finished Feb 26 03:16:11 PM PST 24
Peak memory 206896 kb
Host smart-00ae6909-1ffb-4fa4-9baf-bce194de85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075486988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4075486988
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.993023145
Short name T1038
Test name
Test status
Simulation time 3206466883 ps
CPU time 31.9 seconds
Started Feb 26 03:16:19 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 208012 kb
Host smart-84ac2299-992f-46a0-beab-d00facb24b88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993023145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.993023145
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1436474281
Short name T388
Test name
Test status
Simulation time 530688761 ps
CPU time 10.81 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:25 PM PST 24
Peak memory 208144 kb
Host smart-4b4a900f-3afc-4811-b3da-86ba20531bb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436474281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1436474281
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1575595580
Short name T932
Test name
Test status
Simulation time 280965092 ps
CPU time 3.68 seconds
Started Feb 26 03:16:14 PM PST 24
Finished Feb 26 03:16:18 PM PST 24
Peak memory 206360 kb
Host smart-898d8400-1838-483f-8053-053e6d468d6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575595580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1575595580
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.922925807
Short name T814
Test name
Test status
Simulation time 62351119 ps
CPU time 2.39 seconds
Started Feb 26 03:16:13 PM PST 24
Finished Feb 26 03:16:16 PM PST 24
Peak memory 208080 kb
Host smart-d245a71e-2d95-4f4d-8e44-06a1bed7540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922925807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.922925807
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3835717915
Short name T380
Test name
Test status
Simulation time 253175608 ps
CPU time 2.36 seconds
Started Feb 26 03:16:06 PM PST 24
Finished Feb 26 03:16:08 PM PST 24
Peak memory 208476 kb
Host smart-9a941dab-396b-4729-bc9d-89b8b033926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835717915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3835717915
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3924284048
Short name T736
Test name
Test status
Simulation time 9010323844 ps
CPU time 91.96 seconds
Started Feb 26 03:16:14 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 216548 kb
Host smart-f82731df-11a3-4670-8bcd-f08bac52700e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924284048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3924284048
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3717732183
Short name T815
Test name
Test status
Simulation time 185203899 ps
CPU time 4.25 seconds
Started Feb 26 03:16:11 PM PST 24
Finished Feb 26 03:16:16 PM PST 24
Peak memory 219260 kb
Host smart-7647f2f8-e325-4ebd-a977-e5024b179f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717732183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3717732183
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.295575081
Short name T1067
Test name
Test status
Simulation time 88595318 ps
CPU time 4.28 seconds
Started Feb 26 03:16:15 PM PST 24
Finished Feb 26 03:16:19 PM PST 24
Peak memory 207704 kb
Host smart-fd2ceb17-be63-4e21-9e97-de2f0a1c3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295575081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.295575081
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.13079974
Short name T540
Test name
Test status
Simulation time 166099507 ps
CPU time 0.85 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 205868 kb
Host smart-7e6b958a-ca40-46d7-a43c-f988a49e239c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13079974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.13079974
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1342862635
Short name T221
Test name
Test status
Simulation time 55998111 ps
CPU time 2.56 seconds
Started Feb 26 03:16:26 PM PST 24
Finished Feb 26 03:16:29 PM PST 24
Peak memory 214276 kb
Host smart-518ea37d-4139-4425-a6e7-f063336c273a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342862635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1342862635
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1773972170
Short name T65
Test name
Test status
Simulation time 83963812 ps
CPU time 2.5 seconds
Started Feb 26 03:16:27 PM PST 24
Finished Feb 26 03:16:30 PM PST 24
Peak memory 209448 kb
Host smart-bc5f9a57-7c8b-437e-8341-ad9174a415d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773972170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1773972170
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2460487116
Short name T353
Test name
Test status
Simulation time 543817360 ps
CPU time 15.92 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 222388 kb
Host smart-1e587b31-9879-4684-b684-08e16cd75c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460487116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2460487116
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2595050025
Short name T237
Test name
Test status
Simulation time 144055653 ps
CPU time 5.53 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 210736 kb
Host smart-6b0dda3c-8183-4608-b316-de1ba30c7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595050025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2595050025
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1457898350
Short name T767
Test name
Test status
Simulation time 285045597 ps
CPU time 4.61 seconds
Started Feb 26 03:16:26 PM PST 24
Finished Feb 26 03:16:31 PM PST 24
Peak memory 214836 kb
Host smart-c08f9348-e8e0-4adc-84dd-1f122031f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457898350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1457898350
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3328752497
Short name T1062
Test name
Test status
Simulation time 84356961 ps
CPU time 4.21 seconds
Started Feb 26 03:16:29 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 208816 kb
Host smart-405c6c8b-74f9-4a2f-84bc-e9cee18948c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328752497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3328752497
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1790819271
Short name T249
Test name
Test status
Simulation time 46596921 ps
CPU time 2.42 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:31 PM PST 24
Peak memory 206796 kb
Host smart-b4735914-0221-46b3-8772-cef30992ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790819271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1790819271
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2782662361
Short name T671
Test name
Test status
Simulation time 70024201 ps
CPU time 2.62 seconds
Started Feb 26 03:16:26 PM PST 24
Finished Feb 26 03:16:30 PM PST 24
Peak memory 206932 kb
Host smart-46f5468e-9b95-46a2-92d4-03100f3d222a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782662361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2782662361
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.280379926
Short name T1045
Test name
Test status
Simulation time 58046450 ps
CPU time 2.45 seconds
Started Feb 26 03:16:29 PM PST 24
Finished Feb 26 03:16:32 PM PST 24
Peak memory 206968 kb
Host smart-530f11eb-1f7e-4ae4-8a6d-3ae2c7d8faff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280379926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.280379926
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1140297013
Short name T1053
Test name
Test status
Simulation time 241449221 ps
CPU time 7.44 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 207932 kb
Host smart-20c0dd28-c8d6-42a5-a368-8e997e449676
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140297013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1140297013
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.233530466
Short name T915
Test name
Test status
Simulation time 598587959 ps
CPU time 3.84 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:37 PM PST 24
Peak memory 209248 kb
Host smart-348e183f-9b62-443b-811d-4712f7db1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233530466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.233530466
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1843602556
Short name T1019
Test name
Test status
Simulation time 504390956 ps
CPU time 3.95 seconds
Started Feb 26 03:16:14 PM PST 24
Finished Feb 26 03:16:19 PM PST 24
Peak memory 206724 kb
Host smart-8ea9e4fa-42fd-4352-ad85-36b7989cd2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843602556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1843602556
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2997054332
Short name T672
Test name
Test status
Simulation time 107746193 ps
CPU time 1.9 seconds
Started Feb 26 03:16:32 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 214364 kb
Host smart-734ae285-d0ef-4d2e-ae09-706c6ff5f52a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997054332 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2997054332
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2299315929
Short name T325
Test name
Test status
Simulation time 2464560213 ps
CPU time 36.61 seconds
Started Feb 26 03:16:29 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 208900 kb
Host smart-e2d99989-44cf-43b0-88ac-2b3b8ca4163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299315929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2299315929
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.856793876
Short name T56
Test name
Test status
Simulation time 3480644040 ps
CPU time 16.46 seconds
Started Feb 26 03:16:29 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 211888 kb
Host smart-af0d72c7-546d-49d8-84b1-8e0f49d2987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856793876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.856793876
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.263376373
Short name T417
Test name
Test status
Simulation time 22767426 ps
CPU time 0.74 seconds
Started Feb 26 03:16:32 PM PST 24
Finished Feb 26 03:16:33 PM PST 24
Peak memory 205836 kb
Host smart-02a2fe6c-280e-4de8-8e91-c64a68c3f435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263376373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.263376373
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.70985746
Short name T924
Test name
Test status
Simulation time 176015713 ps
CPU time 3.46 seconds
Started Feb 26 03:16:30 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 214216 kb
Host smart-5c4f8edc-367a-4d1e-9820-a64e4ce7655a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70985746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.70985746
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1442956353
Short name T42
Test name
Test status
Simulation time 108743099 ps
CPU time 3.19 seconds
Started Feb 26 03:16:39 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 214328 kb
Host smart-4259a5c6-e390-402b-8d11-d4c1baee143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442956353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1442956353
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2052246414
Short name T722
Test name
Test status
Simulation time 275801729 ps
CPU time 3.91 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 209688 kb
Host smart-8b4cc4a4-57bf-4b2d-b3e5-f3ed9fe3d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052246414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2052246414
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1680410694
Short name T276
Test name
Test status
Simulation time 139638597 ps
CPU time 6.42 seconds
Started Feb 26 03:16:38 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 210736 kb
Host smart-e4dfad50-47d9-485b-9029-e7710f0f2e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680410694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1680410694
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1184549916
Short name T206
Test name
Test status
Simulation time 306679069 ps
CPU time 4.42 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 222484 kb
Host smart-939d93bc-b6f2-4d41-837c-42ec9885798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184549916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1184549916
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2530234927
Short name T888
Test name
Test status
Simulation time 9694048746 ps
CPU time 18.72 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:52 PM PST 24
Peak memory 218220 kb
Host smart-ad0969c5-1db1-4848-9c28-7b1dffe0921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530234927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2530234927
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.788916322
Short name T715
Test name
Test status
Simulation time 148901309 ps
CPU time 2.99 seconds
Started Feb 26 03:16:31 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 206824 kb
Host smart-328f9eae-8477-4aa6-a0de-70e3f5a4c548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788916322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.788916322
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2924100895
Short name T867
Test name
Test status
Simulation time 295067652 ps
CPU time 3.82 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 208760 kb
Host smart-966222b7-2409-480a-8364-5c4343c1b020
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924100895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2924100895
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3364287659
Short name T663
Test name
Test status
Simulation time 276811728 ps
CPU time 3.7 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:37 PM PST 24
Peak memory 208780 kb
Host smart-0083faa3-6ec3-4d75-b91f-10136f4ab532
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364287659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3364287659
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.975671763
Short name T901
Test name
Test status
Simulation time 147597646 ps
CPU time 2.81 seconds
Started Feb 26 03:16:15 PM PST 24
Finished Feb 26 03:16:19 PM PST 24
Peak memory 208836 kb
Host smart-395c02fd-a0f4-47c6-8c31-0a9f7c8ed66d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975671763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.975671763
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.673248775
Short name T978
Test name
Test status
Simulation time 257429804 ps
CPU time 3.16 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 218096 kb
Host smart-cfb9017e-204f-46d9-ac68-885ef34854a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673248775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.673248775
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1268621754
Short name T621
Test name
Test status
Simulation time 35768662 ps
CPU time 2.44 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 206040 kb
Host smart-9ecccf44-e18a-4326-b45e-df236afa5808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268621754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1268621754
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2259936898
Short name T302
Test name
Test status
Simulation time 3740090250 ps
CPU time 98.55 seconds
Started Feb 26 03:16:35 PM PST 24
Finished Feb 26 03:18:14 PM PST 24
Peak memory 217292 kb
Host smart-cd8cb773-5b7c-480e-8de9-e155480fee6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259936898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2259936898
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2071759794
Short name T192
Test name
Test status
Simulation time 562942680 ps
CPU time 10.43 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 222652 kb
Host smart-e0f9a9f7-5481-47f1-9215-7420f0d86f4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071759794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2071759794
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4123740786
Short name T225
Test name
Test status
Simulation time 131642200 ps
CPU time 6.15 seconds
Started Feb 26 03:16:32 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 218272 kb
Host smart-9f197233-f06b-4b36-9f9d-ef8e1ad18295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123740786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4123740786
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2347686908
Short name T559
Test name
Test status
Simulation time 44557042 ps
CPU time 2.34 seconds
Started Feb 26 03:16:39 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 210128 kb
Host smart-9db462f0-6d90-46aa-806b-aaf393a9f54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347686908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2347686908
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.832273130
Short name T787
Test name
Test status
Simulation time 36814656 ps
CPU time 0.76 seconds
Started Feb 26 03:16:22 PM PST 24
Finished Feb 26 03:16:23 PM PST 24
Peak memory 205868 kb
Host smart-8ee5e4ab-e8df-459f-b9d0-3634dc4e6b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832273130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.832273130
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.931539787
Short name T323
Test name
Test status
Simulation time 1194569237 ps
CPU time 16.84 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:17:00 PM PST 24
Peak memory 215000 kb
Host smart-807d24c8-42ea-42ae-8d40-a2af3f59f46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931539787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.931539787
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3469886123
Short name T781
Test name
Test status
Simulation time 107849809 ps
CPU time 3.64 seconds
Started Feb 26 03:16:23 PM PST 24
Finished Feb 26 03:16:27 PM PST 24
Peak memory 214600 kb
Host smart-319cdc9f-11e9-42f0-b4d5-ec623d1648fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469886123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3469886123
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3476788978
Short name T902
Test name
Test status
Simulation time 1263171851 ps
CPU time 21.09 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 219756 kb
Host smart-976a01c7-dc8c-4518-90d1-16bab621bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476788978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3476788978
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2419356764
Short name T250
Test name
Test status
Simulation time 1470257196 ps
CPU time 9.92 seconds
Started Feb 26 03:16:44 PM PST 24
Finished Feb 26 03:16:54 PM PST 24
Peak memory 214280 kb
Host smart-caec7830-3479-4e2c-a19c-5d4020a34522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419356764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2419356764
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3528437149
Short name T274
Test name
Test status
Simulation time 56195430 ps
CPU time 3.42 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:16:46 PM PST 24
Peak memory 210392 kb
Host smart-d29a5f99-2f37-4ce0-8cc0-16ccfe246f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528437149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3528437149
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.221082717
Short name T127
Test name
Test status
Simulation time 260759158 ps
CPU time 2.67 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 206052 kb
Host smart-5409c72d-357c-46e4-8c99-36f5fbf773f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221082717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.221082717
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1162378886
Short name T886
Test name
Test status
Simulation time 1777006508 ps
CPU time 30.37 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:17:08 PM PST 24
Peak memory 208768 kb
Host smart-704c0834-e623-4f0a-b3a6-82f47ec53010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162378886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1162378886
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.103727207
Short name T769
Test name
Test status
Simulation time 2421292278 ps
CPU time 23.89 seconds
Started Feb 26 03:16:35 PM PST 24
Finished Feb 26 03:16:59 PM PST 24
Peak memory 207648 kb
Host smart-f3b73326-36bd-49e0-a8ff-54e37f71ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103727207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.103727207
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2981641127
Short name T350
Test name
Test status
Simulation time 42910029 ps
CPU time 2.44 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:37 PM PST 24
Peak memory 206904 kb
Host smart-16d98f6d-3940-46d3-933a-e684302c3394
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981641127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2981641127
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2757619034
Short name T981
Test name
Test status
Simulation time 52620517 ps
CPU time 2.96 seconds
Started Feb 26 03:16:35 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 206400 kb
Host smart-65f12e25-8a41-4af5-b38e-7fbe028e3d13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757619034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2757619034
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2554870438
Short name T687
Test name
Test status
Simulation time 124539391 ps
CPU time 3.42 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 208456 kb
Host smart-59cce8dd-72dd-4abb-9161-d6f3371cd1da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554870438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2554870438
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1760780746
Short name T1043
Test name
Test status
Simulation time 149742707 ps
CPU time 3.58 seconds
Started Feb 26 03:16:21 PM PST 24
Finished Feb 26 03:16:25 PM PST 24
Peak memory 209812 kb
Host smart-be99630d-62ac-49e2-8bb1-d6aea7e6e9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760780746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1760780746
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3885365564
Short name T14
Test name
Test status
Simulation time 2499764200 ps
CPU time 8.1 seconds
Started Feb 26 03:16:32 PM PST 24
Finished Feb 26 03:16:40 PM PST 24
Peak memory 208508 kb
Host smart-73cdd86e-5219-43ea-ba54-d00166911b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885365564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3885365564
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1356783473
Short name T1007
Test name
Test status
Simulation time 566765708 ps
CPU time 8.68 seconds
Started Feb 26 03:16:19 PM PST 24
Finished Feb 26 03:16:28 PM PST 24
Peak memory 222716 kb
Host smart-92ae085d-85a1-4a07-b84f-ae148ee5d61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356783473 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1356783473
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1515617711
Short name T555
Test name
Test status
Simulation time 1238164776 ps
CPU time 4.51 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 207564 kb
Host smart-99479f6e-d973-4784-b636-862a16031779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515617711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1515617711
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.76689880
Short name T746
Test name
Test status
Simulation time 165434452 ps
CPU time 3.16 seconds
Started Feb 26 03:16:19 PM PST 24
Finished Feb 26 03:16:22 PM PST 24
Peak memory 209732 kb
Host smart-cf2f5ef4-3d3f-419b-a3e8-b401233b0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76689880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.76689880
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.672105469
Short name T1025
Test name
Test status
Simulation time 110496007 ps
CPU time 0.77 seconds
Started Feb 26 03:16:25 PM PST 24
Finished Feb 26 03:16:26 PM PST 24
Peak memory 205776 kb
Host smart-c9b969eb-aaeb-4b31-929b-d6d4ec8f9b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672105469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.672105469
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.409294379
Short name T183
Test name
Test status
Simulation time 50177783 ps
CPU time 3.18 seconds
Started Feb 26 03:16:25 PM PST 24
Finished Feb 26 03:16:28 PM PST 24
Peak memory 214300 kb
Host smart-73901376-4dd1-45be-949d-1712a1ecbbce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409294379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.409294379
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1409815912
Short name T33
Test name
Test status
Simulation time 118945599 ps
CPU time 4.69 seconds
Started Feb 26 03:16:27 PM PST 24
Finished Feb 26 03:16:32 PM PST 24
Peak memory 222736 kb
Host smart-27638268-0fc2-4e45-bc77-a32b1aa155f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409815912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1409815912
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.261027972
Short name T616
Test name
Test status
Simulation time 343825561 ps
CPU time 4.08 seconds
Started Feb 26 03:16:22 PM PST 24
Finished Feb 26 03:16:26 PM PST 24
Peak memory 209692 kb
Host smart-3f897354-c6c5-42a4-b9a4-de814a591c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261027972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.261027972
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1131826385
Short name T362
Test name
Test status
Simulation time 272376236 ps
CPU time 3.12 seconds
Started Feb 26 03:16:25 PM PST 24
Finished Feb 26 03:16:28 PM PST 24
Peak memory 219576 kb
Host smart-dd7c6a04-e455-48d5-9e8e-6f046e7eeb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131826385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1131826385
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2013135863
Short name T4
Test name
Test status
Simulation time 703069484 ps
CPU time 9.99 seconds
Started Feb 26 03:16:26 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 211232 kb
Host smart-631ca14c-5d65-4566-8e89-bf17bc057667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013135863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2013135863
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3339038180
Short name T577
Test name
Test status
Simulation time 297360383 ps
CPU time 4.21 seconds
Started Feb 26 03:16:27 PM PST 24
Finished Feb 26 03:16:32 PM PST 24
Peak memory 215488 kb
Host smart-cc5388c9-7862-47a1-9493-7b1062bda33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339038180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3339038180
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.964086350
Short name T260
Test name
Test status
Simulation time 674751843 ps
CPU time 22.3 seconds
Started Feb 26 03:16:20 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 218964 kb
Host smart-26ca0212-c87d-424f-b71f-0aa4a3b1f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964086350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.964086350
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3277838929
Short name T921
Test name
Test status
Simulation time 8466299657 ps
CPU time 42.72 seconds
Started Feb 26 03:16:19 PM PST 24
Finished Feb 26 03:17:02 PM PST 24
Peak memory 208540 kb
Host smart-521fa179-d1e8-4a4b-88f8-fe8a5cc31aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277838929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3277838929
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2074654106
Short name T365
Test name
Test status
Simulation time 293757549 ps
CPU time 3.87 seconds
Started Feb 26 03:16:21 PM PST 24
Finished Feb 26 03:16:25 PM PST 24
Peak memory 208504 kb
Host smart-06de2c9d-333c-48e8-ba24-30519cded6cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074654106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2074654106
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2957751899
Short name T927
Test name
Test status
Simulation time 319603429 ps
CPU time 3.68 seconds
Started Feb 26 03:16:20 PM PST 24
Finished Feb 26 03:16:24 PM PST 24
Peak memory 208428 kb
Host smart-33213175-bda1-481a-a04d-f5d64d9307a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957751899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2957751899
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.610616239
Short name T674
Test name
Test status
Simulation time 132597397 ps
CPU time 5.1 seconds
Started Feb 26 03:16:19 PM PST 24
Finished Feb 26 03:16:25 PM PST 24
Peak memory 208536 kb
Host smart-be3a3421-e0ec-4dd7-b66e-56ff89ab34ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610616239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.610616239
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3885024232
Short name T396
Test name
Test status
Simulation time 24296885 ps
CPU time 1.56 seconds
Started Feb 26 03:16:23 PM PST 24
Finished Feb 26 03:16:25 PM PST 24
Peak memory 207500 kb
Host smart-b7799842-0d6b-4020-99af-a556d5064cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885024232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3885024232
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.546209376
Short name T856
Test name
Test status
Simulation time 239342309 ps
CPU time 3.13 seconds
Started Feb 26 03:16:20 PM PST 24
Finished Feb 26 03:16:23 PM PST 24
Peak memory 206580 kb
Host smart-c948a8b1-0ad5-4007-9e34-6ce00d63bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546209376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.546209376
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3663622475
Short name T218
Test name
Test status
Simulation time 1818939194 ps
CPU time 23.12 seconds
Started Feb 26 03:16:28 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 222516 kb
Host smart-beefcae5-5df5-4938-8d85-8cc4e9a181ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663622475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3663622475
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1694939102
Short name T805
Test name
Test status
Simulation time 196326025 ps
CPU time 13.07 seconds
Started Feb 26 03:16:24 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 222624 kb
Host smart-ce5061e0-171c-4b97-bf7d-015bdb5a3afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694939102 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1694939102
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2619873092
Short name T860
Test name
Test status
Simulation time 431589231 ps
CPU time 12.39 seconds
Started Feb 26 03:16:25 PM PST 24
Finished Feb 26 03:16:37 PM PST 24
Peak memory 218380 kb
Host smart-874cc26f-2c63-4f01-8f2a-d333794532aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619873092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2619873092
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2738346070
Short name T36
Test name
Test status
Simulation time 215161135 ps
CPU time 4.69 seconds
Started Feb 26 03:16:25 PM PST 24
Finished Feb 26 03:16:30 PM PST 24
Peak memory 210500 kb
Host smart-b6443a55-3121-47dd-ab9e-37005ebda49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738346070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2738346070
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2507988914
Short name T541
Test name
Test status
Simulation time 16663170 ps
CPU time 1.06 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:39 PM PST 24
Peak memory 205976 kb
Host smart-396e705c-2030-4fa1-b9c6-0debffcee978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507988914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2507988914
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3098631435
Short name T402
Test name
Test status
Simulation time 231669211 ps
CPU time 4.67 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:39 PM PST 24
Peak memory 215312 kb
Host smart-963f2d7d-0d2e-4ed8-adf7-7315209ddbda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098631435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3098631435
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1958087992
Short name T28
Test name
Test status
Simulation time 140164120 ps
CPU time 1.84 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:40 PM PST 24
Peak memory 208412 kb
Host smart-7162a7fc-fe35-488d-847e-9a5adfd233ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958087992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1958087992
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2847628580
Short name T996
Test name
Test status
Simulation time 172447622 ps
CPU time 3.56 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 206916 kb
Host smart-30d890a5-b067-4c0e-9c63-dfb34efe05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847628580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2847628580
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2238927000
Short name T294
Test name
Test status
Simulation time 72660389 ps
CPU time 4.35 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 214308 kb
Host smart-07b3e353-0ad8-4914-b813-64f26e346409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238927000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2238927000
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1313395990
Short name T1056
Test name
Test status
Simulation time 99050000 ps
CPU time 3.89 seconds
Started Feb 26 03:16:32 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 211100 kb
Host smart-60f83380-860a-4d1b-8514-673fce28376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313395990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1313395990
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1522153244
Short name T94
Test name
Test status
Simulation time 293953743 ps
CPU time 1.57 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:35 PM PST 24
Peak memory 206052 kb
Host smart-3aa2ecf8-c67b-477d-9030-7b22db7fc7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522153244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1522153244
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.531194203
Short name T1068
Test name
Test status
Simulation time 533122660 ps
CPU time 10.27 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 209124 kb
Host smart-fe3a3e85-c51c-447f-8347-e5c0612a791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531194203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.531194203
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1948353148
Short name T858
Test name
Test status
Simulation time 294125369 ps
CPU time 3.66 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:38 PM PST 24
Peak memory 208632 kb
Host smart-95126857-089c-4fb3-92a6-0e109457753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948353148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1948353148
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.248282744
Short name T76
Test name
Test status
Simulation time 137815139 ps
CPU time 4.42 seconds
Started Feb 26 03:16:36 PM PST 24
Finished Feb 26 03:16:40 PM PST 24
Peak memory 208592 kb
Host smart-fc37cb06-f410-4b76-8c41-028c2f837570
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248282744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.248282744
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1645153564
Short name T549
Test name
Test status
Simulation time 1820520972 ps
CPU time 12.45 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:46 PM PST 24
Peak memory 207996 kb
Host smart-faac87c2-400d-4845-a4b9-d850de964902
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645153564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1645153564
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.227025964
Short name T944
Test name
Test status
Simulation time 27322133 ps
CPU time 1.87 seconds
Started Feb 26 03:16:34 PM PST 24
Finished Feb 26 03:16:36 PM PST 24
Peak memory 207564 kb
Host smart-6db0afe0-1ed3-432e-b3b9-18140b94ca0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227025964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.227025964
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.102437718
Short name T743
Test name
Test status
Simulation time 1154334121 ps
CPU time 14.29 seconds
Started Feb 26 03:16:31 PM PST 24
Finished Feb 26 03:16:46 PM PST 24
Peak memory 208912 kb
Host smart-e5f21f0d-2fd9-4023-bc78-e34fa3a9e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102437718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.102437718
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2277055520
Short name T666
Test name
Test status
Simulation time 182598277 ps
CPU time 4.77 seconds
Started Feb 26 03:16:29 PM PST 24
Finished Feb 26 03:16:34 PM PST 24
Peak memory 206728 kb
Host smart-4342ba23-e774-4b35-8ca7-d1d986f9fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277055520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2277055520
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2753246949
Short name T838
Test name
Test status
Simulation time 1730088302 ps
CPU time 14.14 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 215620 kb
Host smart-20f89893-b3b0-4841-a4fc-932454149642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753246949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2753246949
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2242335336
Short name T201
Test name
Test status
Simulation time 353296271 ps
CPU time 10.75 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:16:54 PM PST 24
Peak memory 222576 kb
Host smart-3396e83a-f929-4e76-9c20-34b53e3607c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242335336 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2242335336
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2336490573
Short name T248
Test name
Test status
Simulation time 3880861065 ps
CPU time 26.52 seconds
Started Feb 26 03:16:33 PM PST 24
Finished Feb 26 03:16:59 PM PST 24
Peak memory 208740 kb
Host smart-1684cb53-c773-4256-830d-6f22775dcc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336490573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2336490573
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4216304376
Short name T779
Test name
Test status
Simulation time 3963165062 ps
CPU time 22.03 seconds
Started Feb 26 03:16:42 PM PST 24
Finished Feb 26 03:17:05 PM PST 24
Peak memory 212328 kb
Host smart-ec16c443-d059-4e70-a590-2d3b15876f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216304376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4216304376
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.174369178
Short name T87
Test name
Test status
Simulation time 16636576 ps
CPU time 0.93 seconds
Started Feb 26 03:16:52 PM PST 24
Finished Feb 26 03:16:53 PM PST 24
Peak memory 206064 kb
Host smart-61d1c16f-cdf3-4fe1-a20b-b3066df731c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174369178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.174369178
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3983877084
Short name T394
Test name
Test status
Simulation time 198412043 ps
CPU time 4.12 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:41 PM PST 24
Peak memory 214252 kb
Host smart-0387b96d-345c-4ab5-a251-9b2e339bea1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983877084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3983877084
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3690106891
Short name T74
Test name
Test status
Simulation time 188511245 ps
CPU time 2.38 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:16:45 PM PST 24
Peak memory 209360 kb
Host smart-15c9a38d-75f2-44c0-8e54-5989b8520b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690106891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3690106891
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2047183156
Short name T82
Test name
Test status
Simulation time 61550979 ps
CPU time 3.14 seconds
Started Feb 26 03:16:44 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 214288 kb
Host smart-ad100960-0e2f-45ab-9550-d3a265f33ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047183156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2047183156
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3013326551
Short name T1032
Test name
Test status
Simulation time 568587869 ps
CPU time 17.08 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:17:04 PM PST 24
Peak memory 220592 kb
Host smart-b310a611-8848-4410-beeb-eab8c7adcc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013326551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3013326551
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2219396749
Short name T893
Test name
Test status
Simulation time 303124376 ps
CPU time 4.18 seconds
Started Feb 26 03:16:51 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 210084 kb
Host smart-503860ea-9909-44c6-b977-f6d133738c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219396749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2219396749
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3203146511
Short name T947
Test name
Test status
Simulation time 49667315 ps
CPU time 2.86 seconds
Started Feb 26 03:16:43 PM PST 24
Finished Feb 26 03:16:46 PM PST 24
Peak memory 206628 kb
Host smart-f8fbdc32-e0cc-4964-9ede-f323746f5e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203146511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3203146511
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2297740786
Short name T265
Test name
Test status
Simulation time 215325103 ps
CPU time 3.25 seconds
Started Feb 26 03:16:39 PM PST 24
Finished Feb 26 03:16:43 PM PST 24
Peak memory 207580 kb
Host smart-a0e05aab-3967-4249-b75d-a6ec748b5d4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297740786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2297740786
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2882591455
Short name T546
Test name
Test status
Simulation time 4467374464 ps
CPU time 44.66 seconds
Started Feb 26 03:16:44 PM PST 24
Finished Feb 26 03:17:28 PM PST 24
Peak memory 208276 kb
Host smart-15931bd7-59d7-46f1-973c-424c5e5a1406
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882591455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2882591455
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4052665318
Short name T699
Test name
Test status
Simulation time 126429708 ps
CPU time 5.15 seconds
Started Feb 26 03:16:37 PM PST 24
Finished Feb 26 03:16:43 PM PST 24
Peak memory 208868 kb
Host smart-387885fb-e4ae-464e-88b1-f4e70da0a6fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052665318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4052665318
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.795708651
Short name T542
Test name
Test status
Simulation time 153069409 ps
CPU time 2.67 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 207028 kb
Host smart-d07866e3-732b-4151-8eb5-ed9c153351ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795708651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.795708651
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.270813517
Short name T971
Test name
Test status
Simulation time 1140103498 ps
CPU time 4.58 seconds
Started Feb 26 03:16:38 PM PST 24
Finished Feb 26 03:16:43 PM PST 24
Peak memory 206804 kb
Host smart-8ebe7f28-3346-40c5-8c73-b9199594398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270813517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.270813517
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2828243615
Short name T205
Test name
Test status
Simulation time 1298753905 ps
CPU time 35.13 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:17:22 PM PST 24
Peak memory 222508 kb
Host smart-363c2653-a8e9-4665-b514-ccee3a31bcb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828243615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2828243615
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1378170204
Short name T98
Test name
Test status
Simulation time 394725952 ps
CPU time 3.95 seconds
Started Feb 26 03:16:49 PM PST 24
Finished Feb 26 03:16:53 PM PST 24
Peak memory 222512 kb
Host smart-4a8fbef4-a581-4b27-94c3-328ae6f167cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378170204 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1378170204
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1696713503
Short name T766
Test name
Test status
Simulation time 82006266 ps
CPU time 4 seconds
Started Feb 26 03:16:38 PM PST 24
Finished Feb 26 03:16:42 PM PST 24
Peak memory 209784 kb
Host smart-2b3d95f6-4260-44de-9ea1-e8518812338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696713503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1696713503
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2509115481
Short name T1011
Test name
Test status
Simulation time 80037056 ps
CPU time 2.5 seconds
Started Feb 26 03:16:53 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 211004 kb
Host smart-8ce28f8b-681f-4d66-8e5f-91cbbf857246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509115481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2509115481
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.760036077
Short name T861
Test name
Test status
Simulation time 10101575 ps
CPU time 0.71 seconds
Started Feb 26 03:16:46 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 205772 kb
Host smart-28b8ffd4-c0ce-4308-acdb-179b5fc4a34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760036077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.760036077
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.347117826
Short name T404
Test name
Test status
Simulation time 1311347948 ps
CPU time 17.33 seconds
Started Feb 26 03:16:44 PM PST 24
Finished Feb 26 03:17:01 PM PST 24
Peak memory 215280 kb
Host smart-66790dcf-acd3-4fe4-89f1-633839a4182f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347117826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.347117826
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.238263745
Short name T309
Test name
Test status
Simulation time 26710618 ps
CPU time 1.76 seconds
Started Feb 26 03:16:46 PM PST 24
Finished Feb 26 03:16:48 PM PST 24
Peak memory 214352 kb
Host smart-7fb6558e-bd39-4856-99e0-633f75e3abb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238263745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.238263745
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.381627634
Short name T85
Test name
Test status
Simulation time 852186329 ps
CPU time 6.33 seconds
Started Feb 26 03:16:42 PM PST 24
Finished Feb 26 03:16:49 PM PST 24
Peak memory 219792 kb
Host smart-7da966b7-ab94-4c41-946d-aafb398f5f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381627634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.381627634
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.237143021
Short name T49
Test name
Test status
Simulation time 106537933 ps
CPU time 4.69 seconds
Started Feb 26 03:16:52 PM PST 24
Finished Feb 26 03:16:57 PM PST 24
Peak memory 219740 kb
Host smart-b5e5dbb6-7180-41d2-8d0e-5056c75eeeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237143021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.237143021
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2427357060
Short name T93
Test name
Test status
Simulation time 268740402 ps
CPU time 4.98 seconds
Started Feb 26 03:16:45 PM PST 24
Finished Feb 26 03:16:50 PM PST 24
Peak memory 214376 kb
Host smart-001d0439-2ae9-4147-923f-b1e4331d47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427357060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2427357060
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2909172572
Short name T916
Test name
Test status
Simulation time 86826088 ps
CPU time 3.34 seconds
Started Feb 26 03:16:54 PM PST 24
Finished Feb 26 03:16:57 PM PST 24
Peak memory 206672 kb
Host smart-ff1ff520-fd1b-479e-a5fe-2ecc1775f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909172572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2909172572
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2690337113
Short name T623
Test name
Test status
Simulation time 93752360 ps
CPU time 2.11 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:50 PM PST 24
Peak memory 208656 kb
Host smart-00260ed4-76ac-4521-96b6-3ee09974045b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690337113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2690337113
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.424278336
Short name T889
Test name
Test status
Simulation time 78945294 ps
CPU time 2.84 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 208612 kb
Host smart-cae47643-9bde-4555-b455-f5f6db32dfac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424278336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.424278336
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1454637795
Short name T631
Test name
Test status
Simulation time 395682330 ps
CPU time 5.03 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:16:53 PM PST 24
Peak memory 208728 kb
Host smart-2de6f78d-d128-418b-8332-63470acb109a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454637795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1454637795
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2127526496
Short name T749
Test name
Test status
Simulation time 121925151 ps
CPU time 1.83 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 215680 kb
Host smart-fd826fb4-88b5-43c1-bc61-faccb147a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127526496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2127526496
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3936931822
Short name T686
Test name
Test status
Simulation time 51909092 ps
CPU time 2.76 seconds
Started Feb 26 03:16:50 PM PST 24
Finished Feb 26 03:16:53 PM PST 24
Peak memory 206124 kb
Host smart-66ffd178-bbd9-433d-8e94-6863c6bf2bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936931822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3936931822
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.800012479
Short name T266
Test name
Test status
Simulation time 885531250 ps
CPU time 24.74 seconds
Started Feb 26 03:16:45 PM PST 24
Finished Feb 26 03:17:10 PM PST 24
Peak memory 216864 kb
Host smart-c570059f-e6b2-4560-a722-061532d4ba2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800012479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.800012479
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3275027539
Short name T707
Test name
Test status
Simulation time 789595756 ps
CPU time 13.78 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:17:01 PM PST 24
Peak memory 222616 kb
Host smart-a76769e3-afd2-4182-8351-610e961fe80b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275027539 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3275027539
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2209873149
Short name T652
Test name
Test status
Simulation time 237034601 ps
CPU time 7.79 seconds
Started Feb 26 03:16:40 PM PST 24
Finished Feb 26 03:16:49 PM PST 24
Peak memory 209784 kb
Host smart-99e1639a-d720-4ac4-8245-74e0235543d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209873149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2209873149
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3196102195
Short name T153
Test name
Test status
Simulation time 51975540 ps
CPU time 1.7 seconds
Started Feb 26 03:16:46 PM PST 24
Finished Feb 26 03:16:47 PM PST 24
Peak memory 209868 kb
Host smart-82f4955d-452c-4797-a913-a222195c02dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196102195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3196102195
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4230901109
Short name T756
Test name
Test status
Simulation time 53901952 ps
CPU time 0.95 seconds
Started Feb 26 03:16:51 PM PST 24
Finished Feb 26 03:16:52 PM PST 24
Peak memory 206012 kb
Host smart-4ca47eda-1cf0-48b9-aba4-c55cb88534dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230901109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4230901109
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3271300162
Short name T29
Test name
Test status
Simulation time 187432119 ps
CPU time 7.81 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:23 PM PST 24
Peak memory 210128 kb
Host smart-7b0e34d6-6659-4623-bfc2-902d076e20bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271300162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3271300162
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2271481109
Short name T59
Test name
Test status
Simulation time 73946703 ps
CPU time 3.7 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:52 PM PST 24
Peak memory 209536 kb
Host smart-8c36b2b7-9ee0-4159-b54f-ab6837ed5528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271481109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2271481109
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3971562599
Short name T315
Test name
Test status
Simulation time 1447811125 ps
CPU time 12.47 seconds
Started Feb 26 03:16:58 PM PST 24
Finished Feb 26 03:17:10 PM PST 24
Peak memory 214204 kb
Host smart-f988ba94-ac18-4153-9bee-badee1ed1939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971562599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3971562599
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3633500505
Short name T293
Test name
Test status
Simulation time 757683525 ps
CPU time 7.22 seconds
Started Feb 26 03:16:51 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 214260 kb
Host smart-c6ee9259-752f-492d-a920-1cba7cf7916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633500505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3633500505
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2926939100
Short name T820
Test name
Test status
Simulation time 188029509 ps
CPU time 3.81 seconds
Started Feb 26 03:16:53 PM PST 24
Finished Feb 26 03:16:56 PM PST 24
Peak memory 220128 kb
Host smart-74a9982d-af90-4f85-b007-2a0f7952e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926939100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2926939100
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2305684717
Short name T340
Test name
Test status
Simulation time 82992213 ps
CPU time 3.82 seconds
Started Feb 26 03:16:45 PM PST 24
Finished Feb 26 03:16:48 PM PST 24
Peak memory 208268 kb
Host smart-5d22d534-c68b-4d7e-937b-e974fc1ee9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305684717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2305684717
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1666034581
Short name T361
Test name
Test status
Simulation time 497291497 ps
CPU time 10.16 seconds
Started Feb 26 03:16:52 PM PST 24
Finished Feb 26 03:17:02 PM PST 24
Peak memory 208328 kb
Host smart-ba9181c9-5492-41d2-bf53-413d9e234f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666034581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1666034581
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2846709447
Short name T705
Test name
Test status
Simulation time 557801988 ps
CPU time 2.96 seconds
Started Feb 26 03:16:47 PM PST 24
Finished Feb 26 03:16:50 PM PST 24
Peak memory 206844 kb
Host smart-3a69612a-090e-4e41-8103-0d99e669f297
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846709447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2846709447
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3478892503
Short name T688
Test name
Test status
Simulation time 1084632911 ps
CPU time 7.61 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 207984 kb
Host smart-abfe732e-b0d8-4fa5-ae42-7e279a9da8d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478892503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3478892503
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2302597163
Short name T909
Test name
Test status
Simulation time 137674744 ps
CPU time 3.33 seconds
Started Feb 26 03:16:50 PM PST 24
Finished Feb 26 03:16:53 PM PST 24
Peak memory 206852 kb
Host smart-0f0efd38-d294-4d34-8894-bcf46544afef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302597163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2302597163
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.563598428
Short name T754
Test name
Test status
Simulation time 38557606 ps
CPU time 2.1 seconds
Started Feb 26 03:16:50 PM PST 24
Finished Feb 26 03:16:52 PM PST 24
Peak memory 209416 kb
Host smart-1d0e31f0-96b6-4be2-96da-cf9a58035b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563598428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.563598428
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2701391021
Short name T636
Test name
Test status
Simulation time 381408215 ps
CPU time 6.26 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:17:02 PM PST 24
Peak memory 206804 kb
Host smart-b0d944de-dd85-47da-932b-1959a7faf556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701391021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2701391021
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2167319467
Short name T202
Test name
Test status
Simulation time 11791961897 ps
CPU time 41.6 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 222580 kb
Host smart-474806f4-62fa-419d-892e-82be6aedbdb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167319467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2167319467
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2036827294
Short name T844
Test name
Test status
Simulation time 107781607 ps
CPU time 4.72 seconds
Started Feb 26 03:16:50 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 222560 kb
Host smart-d0339541-5cf1-4180-bdeb-c742acc1f11d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036827294 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2036827294
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.513876973
Short name T822
Test name
Test status
Simulation time 428377621 ps
CPU time 4.51 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:18 PM PST 24
Peak memory 209376 kb
Host smart-e8d587fe-5f42-444f-bcea-ea7c9bfd9912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513876973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.513876973
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.816985486
Short name T158
Test name
Test status
Simulation time 56730799 ps
CPU time 2.47 seconds
Started Feb 26 03:16:52 PM PST 24
Finished Feb 26 03:16:55 PM PST 24
Peak memory 210020 kb
Host smart-f94ef90c-5aac-46ec-aa8f-ba3602bb18fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816985486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.816985486
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2967899861
Short name T539
Test name
Test status
Simulation time 38650746 ps
CPU time 0.85 seconds
Started Feb 26 03:14:19 PM PST 24
Finished Feb 26 03:14:20 PM PST 24
Peak memory 205856 kb
Host smart-2d194f0e-e78a-47b1-bb6f-93f9d14c969d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967899861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2967899861
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3558671528
Short name T280
Test name
Test status
Simulation time 1945081039 ps
CPU time 8.19 seconds
Started Feb 26 03:14:16 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 214252 kb
Host smart-80c56edf-0fe0-47b7-abfd-e2583a27427d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558671528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3558671528
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.340635363
Short name T212
Test name
Test status
Simulation time 275078413 ps
CPU time 4.05 seconds
Started Feb 26 03:14:14 PM PST 24
Finished Feb 26 03:14:18 PM PST 24
Peak memory 209492 kb
Host smart-ae0ca11e-5c7c-450b-9aed-d19fdc732eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340635363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.340635363
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2018843844
Short name T661
Test name
Test status
Simulation time 241192993 ps
CPU time 6.8 seconds
Started Feb 26 03:14:14 PM PST 24
Finished Feb 26 03:14:21 PM PST 24
Peak memory 209348 kb
Host smart-bf2a97e6-22aa-4faa-8876-f001aaea68d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018843844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2018843844
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.89982310
Short name T81
Test name
Test status
Simulation time 1566874284 ps
CPU time 10.59 seconds
Started Feb 26 03:14:14 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 219068 kb
Host smart-7db7aa37-e018-4d09-aef7-f4b0fe470143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89982310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.89982310
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3005044671
Short name T256
Test name
Test status
Simulation time 332230235 ps
CPU time 12.61 seconds
Started Feb 26 03:14:15 PM PST 24
Finished Feb 26 03:14:28 PM PST 24
Peak memory 214208 kb
Host smart-cf3baa50-3eb4-4b7c-8d3e-17d468c16528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005044671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3005044671
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.285567770
Short name T862
Test name
Test status
Simulation time 157402445 ps
CPU time 2.66 seconds
Started Feb 26 03:14:16 PM PST 24
Finished Feb 26 03:14:19 PM PST 24
Peak memory 218592 kb
Host smart-f9e8e3be-fca8-45ec-8787-874adc43a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285567770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.285567770
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3517355134
Short name T327
Test name
Test status
Simulation time 146068934 ps
CPU time 6.01 seconds
Started Feb 26 03:14:15 PM PST 24
Finished Feb 26 03:14:21 PM PST 24
Peak memory 208284 kb
Host smart-0c2e8553-7679-40bd-8141-e9e4fcea6f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517355134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3517355134
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4170951899
Short name T89
Test name
Test status
Simulation time 6102782666 ps
CPU time 38.47 seconds
Started Feb 26 03:14:19 PM PST 24
Finished Feb 26 03:14:58 PM PST 24
Peak memory 235896 kb
Host smart-03bf1ce4-161b-4ec9-aba5-f3add470c9c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170951899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4170951899
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4061444799
Short name T706
Test name
Test status
Simulation time 152896784 ps
CPU time 3.31 seconds
Started Feb 26 03:14:15 PM PST 24
Finished Feb 26 03:14:19 PM PST 24
Peak memory 208320 kb
Host smart-25b87c1c-1d9b-4288-902f-9ac341fd2ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061444799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4061444799
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3854227753
Short name T940
Test name
Test status
Simulation time 2378618172 ps
CPU time 29.23 seconds
Started Feb 26 03:14:18 PM PST 24
Finished Feb 26 03:14:48 PM PST 24
Peak memory 207980 kb
Host smart-256378ed-5d0c-4ea8-800b-3a3dc9004af8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854227753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3854227753
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.718344025
Short name T1054
Test name
Test status
Simulation time 290072013 ps
CPU time 3.81 seconds
Started Feb 26 03:14:14 PM PST 24
Finished Feb 26 03:14:18 PM PST 24
Peak memory 206896 kb
Host smart-a6e5c810-fa78-41ff-8b76-8ca80f759067
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718344025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.718344025
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2683228394
Short name T853
Test name
Test status
Simulation time 457794139 ps
CPU time 3.41 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 206776 kb
Host smart-a4210452-b5e9-4c30-811d-3cdd7d99e3b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683228394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2683228394
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2615808234
Short name T877
Test name
Test status
Simulation time 81193499 ps
CPU time 2.3 seconds
Started Feb 26 03:14:14 PM PST 24
Finished Feb 26 03:14:16 PM PST 24
Peak memory 214320 kb
Host smart-c78476bd-241f-400c-a41b-f3a592022595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615808234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2615808234
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3383217387
Short name T1046
Test name
Test status
Simulation time 1277418511 ps
CPU time 22.17 seconds
Started Feb 26 03:14:10 PM PST 24
Finished Feb 26 03:14:33 PM PST 24
Peak memory 208200 kb
Host smart-2e83740b-8e3c-4886-b249-8e687a6eb65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383217387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3383217387
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2267434397
Short name T363
Test name
Test status
Simulation time 19066769978 ps
CPU time 350.89 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:20:11 PM PST 24
Peak memory 214348 kb
Host smart-250107d9-05c3-4bc5-b0f8-cd3268685737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267434397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2267434397
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1871641774
Short name T742
Test name
Test status
Simulation time 269503166 ps
CPU time 7.5 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:28 PM PST 24
Peak memory 222732 kb
Host smart-6816e72e-731c-4da5-8b9c-5346d53bc411
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871641774 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1871641774
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2862410053
Short name T768
Test name
Test status
Simulation time 199862575 ps
CPU time 8.36 seconds
Started Feb 26 03:14:15 PM PST 24
Finished Feb 26 03:14:23 PM PST 24
Peak memory 218380 kb
Host smart-c618f1a1-03aa-47bb-8b46-c2cd4e9c97dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862410053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2862410053
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1975769668
Short name T138
Test name
Test status
Simulation time 512502559 ps
CPU time 1.8 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:22 PM PST 24
Peak memory 209960 kb
Host smart-796a97f1-e85f-4823-9b0f-6c9bc773c493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975769668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1975769668
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.404406821
Short name T582
Test name
Test status
Simulation time 187630410 ps
CPU time 0.81 seconds
Started Feb 26 03:16:57 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 205876 kb
Host smart-d6a38260-7e5b-4d0e-8c1c-e3589cef78db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404406821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.404406821
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2375079362
Short name T389
Test name
Test status
Simulation time 157166553 ps
CPU time 6.17 seconds
Started Feb 26 03:16:55 PM PST 24
Finished Feb 26 03:17:01 PM PST 24
Peak memory 215052 kb
Host smart-1191d396-6872-4560-9671-7c717653e103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375079362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2375079362
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2130391572
Short name T569
Test name
Test status
Simulation time 49770950 ps
CPU time 2.39 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:16:59 PM PST 24
Peak memory 218196 kb
Host smart-e4c2cc77-816e-4824-af24-099c4e21af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130391572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2130391572
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2975802405
Short name T982
Test name
Test status
Simulation time 3273930481 ps
CPU time 37.19 seconds
Started Feb 26 03:16:53 PM PST 24
Finished Feb 26 03:17:30 PM PST 24
Peak memory 209124 kb
Host smart-6d2b0da6-f2bc-4b17-b2b9-eb146bf8d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975802405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2975802405
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2753263181
Short name T257
Test name
Test status
Simulation time 38763884 ps
CPU time 2.79 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 221160 kb
Host smart-6d69d30b-8c0f-49c4-b7ee-4aa2f2dc76ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753263181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2753263181
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3228800601
Short name T196
Test name
Test status
Simulation time 502448998 ps
CPU time 3.27 seconds
Started Feb 26 03:16:53 PM PST 24
Finished Feb 26 03:16:56 PM PST 24
Peak memory 216088 kb
Host smart-687b3d2d-4e1e-42b6-8024-d0621a993979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228800601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3228800601
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1673722886
Short name T251
Test name
Test status
Simulation time 246587688 ps
CPU time 4.67 seconds
Started Feb 26 03:16:57 PM PST 24
Finished Feb 26 03:17:02 PM PST 24
Peak memory 218192 kb
Host smart-65b9bb7d-f997-4f75-ab56-a2b258dc0f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673722886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1673722886
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.281283827
Short name T817
Test name
Test status
Simulation time 142798920 ps
CPU time 4.25 seconds
Started Feb 26 03:16:54 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 208280 kb
Host smart-437bf268-66f4-487c-8ac5-8b6039ca7a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281283827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.281283827
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3442489695
Short name T1031
Test name
Test status
Simulation time 46035888 ps
CPU time 2.49 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:16:59 PM PST 24
Peak memory 208016 kb
Host smart-08a12011-2452-415a-9449-961224e1349d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442489695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3442489695
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2001327585
Short name T698
Test name
Test status
Simulation time 116042823 ps
CPU time 2.66 seconds
Started Feb 26 03:16:48 PM PST 24
Finished Feb 26 03:16:51 PM PST 24
Peak memory 207604 kb
Host smart-d3bb9353-bd8f-4a12-a2bf-cdeec15a90e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001327585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2001327585
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2141229482
Short name T1017
Test name
Test status
Simulation time 66839468 ps
CPU time 2.54 seconds
Started Feb 26 03:16:54 PM PST 24
Finished Feb 26 03:16:56 PM PST 24
Peak memory 207332 kb
Host smart-dcbd7417-734e-433e-8c0b-b110407c6ab5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141229482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2141229482
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3084553986
Short name T949
Test name
Test status
Simulation time 96603879 ps
CPU time 1.85 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 207180 kb
Host smart-fdcfd284-f52a-44a5-8116-749c83bbb231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084553986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3084553986
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4182888451
Short name T988
Test name
Test status
Simulation time 68377397 ps
CPU time 1.82 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 206884 kb
Host smart-e94d4969-b84a-401a-ab18-426c1e3e088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182888451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4182888451
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1238342763
Short name T243
Test name
Test status
Simulation time 121024380 ps
CPU time 5.98 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:21 PM PST 24
Peak memory 215240 kb
Host smart-3ea9da9c-b499-4dc5-bf4e-b53f710eb4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238342763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1238342763
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3069829358
Short name T930
Test name
Test status
Simulation time 289091638 ps
CPU time 11.45 seconds
Started Feb 26 03:16:55 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 222732 kb
Host smart-043a4f58-3e12-4720-913d-d614c8aaa253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069829358 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3069829358
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2391964616
Short name T401
Test name
Test status
Simulation time 213110128 ps
CPU time 7.99 seconds
Started Feb 26 03:16:55 PM PST 24
Finished Feb 26 03:17:03 PM PST 24
Peak memory 207804 kb
Host smart-95d949f4-d3aa-439a-ae76-87adca56dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391964616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2391964616
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1382894907
Short name T1015
Test name
Test status
Simulation time 466006094 ps
CPU time 1.75 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 209536 kb
Host smart-8629ffd5-af12-4002-9096-cb1cad70e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382894907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1382894907
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.896174855
Short name T669
Test name
Test status
Simulation time 10779620 ps
CPU time 0.76 seconds
Started Feb 26 03:17:04 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 205844 kb
Host smart-4765c8dc-c928-4ee1-bbdf-bf90691857b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896174855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.896174855
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1661706332
Short name T391
Test name
Test status
Simulation time 140014509 ps
CPU time 3.02 seconds
Started Feb 26 03:17:00 PM PST 24
Finished Feb 26 03:17:03 PM PST 24
Peak memory 214320 kb
Host smart-30419d1f-5ba7-43fa-a942-314a5ec9bb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661706332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1661706332
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1967372500
Short name T691
Test name
Test status
Simulation time 189623597 ps
CPU time 3.09 seconds
Started Feb 26 03:17:01 PM PST 24
Finished Feb 26 03:17:05 PM PST 24
Peak memory 219732 kb
Host smart-8a6d4b93-cb16-492b-bcdc-c0009ea6150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967372500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1967372500
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2244026401
Short name T876
Test name
Test status
Simulation time 32138250 ps
CPU time 1.77 seconds
Started Feb 26 03:16:58 PM PST 24
Finished Feb 26 03:17:00 PM PST 24
Peak memory 218184 kb
Host smart-b623b7c3-b72a-46e4-ac5e-7e2f83263640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244026401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2244026401
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1346951767
Short name T1060
Test name
Test status
Simulation time 91642883 ps
CPU time 3.08 seconds
Started Feb 26 03:16:57 PM PST 24
Finished Feb 26 03:17:00 PM PST 24
Peak memory 208276 kb
Host smart-63024cf8-4a11-4d67-a6f2-db10ef28c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346951767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1346951767
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.205888403
Short name T258
Test name
Test status
Simulation time 1407087235 ps
CPU time 10.45 seconds
Started Feb 26 03:16:57 PM PST 24
Finished Feb 26 03:17:07 PM PST 24
Peak memory 214332 kb
Host smart-8299ca7e-0bb1-46b5-8ce3-7fbbc89ca8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205888403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.205888403
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4050435417
Short name T596
Test name
Test status
Simulation time 164455312 ps
CPU time 4.9 seconds
Started Feb 26 03:17:01 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 220420 kb
Host smart-55652043-b393-4465-a462-8ae781fc07c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050435417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4050435417
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.845949319
Short name T605
Test name
Test status
Simulation time 8366861606 ps
CPU time 98.62 seconds
Started Feb 26 03:16:57 PM PST 24
Finished Feb 26 03:18:35 PM PST 24
Peak memory 209420 kb
Host smart-d11bfe1b-a1dd-49f1-8fab-f653d483fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845949319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.845949319
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2168314622
Short name T637
Test name
Test status
Simulation time 79375129 ps
CPU time 1.88 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 207584 kb
Host smart-fd3391aa-c15d-4cb6-b627-7a9fb18bf1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168314622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2168314622
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.581609835
Short name T313
Test name
Test status
Simulation time 1186463378 ps
CPU time 8.16 seconds
Started Feb 26 03:16:56 PM PST 24
Finished Feb 26 03:17:04 PM PST 24
Peak memory 208492 kb
Host smart-e820a91d-6b03-4d64-b687-f038659a9a98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581609835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.581609835
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2473018789
Short name T681
Test name
Test status
Simulation time 63314727 ps
CPU time 2.99 seconds
Started Feb 26 03:16:55 PM PST 24
Finished Feb 26 03:16:58 PM PST 24
Peak memory 208012 kb
Host smart-b272a225-747f-4763-b767-8aca99ff53b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473018789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2473018789
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3156577141
Short name T585
Test name
Test status
Simulation time 71118481 ps
CPU time 3.6 seconds
Started Feb 26 03:16:59 PM PST 24
Finished Feb 26 03:17:03 PM PST 24
Peak memory 208576 kb
Host smart-0b7369fa-23e9-4211-a53d-3706752d823e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156577141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3156577141
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3646370277
Short name T845
Test name
Test status
Simulation time 121366493 ps
CPU time 2.94 seconds
Started Feb 26 03:16:58 PM PST 24
Finished Feb 26 03:17:01 PM PST 24
Peak memory 215008 kb
Host smart-1d41a396-b803-4595-9cef-b9110ac12d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646370277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3646370277
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3308201880
Short name T868
Test name
Test status
Simulation time 120119530 ps
CPU time 3.53 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:19 PM PST 24
Peak memory 208820 kb
Host smart-ee9c17b9-11b1-48f9-9bfc-686e218af8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308201880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3308201880
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3654339521
Short name T341
Test name
Test status
Simulation time 7084296080 ps
CPU time 80.67 seconds
Started Feb 26 03:17:03 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 222512 kb
Host smart-69ce4ed9-8b85-4b8f-b536-43fac1aa7eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654339521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3654339521
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3926878185
Short name T913
Test name
Test status
Simulation time 601441569 ps
CPU time 7.88 seconds
Started Feb 26 03:17:03 PM PST 24
Finished Feb 26 03:17:11 PM PST 24
Peak memory 223096 kb
Host smart-2305ca37-2c17-40fb-9880-0d26501a7693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926878185 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3926878185
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1183698839
Short name T784
Test name
Test status
Simulation time 311617647 ps
CPU time 4.15 seconds
Started Feb 26 03:16:59 PM PST 24
Finished Feb 26 03:17:04 PM PST 24
Peak memory 207364 kb
Host smart-69f83911-8470-47ac-b99f-b7c91735f34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183698839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1183698839
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2236327301
Short name T550
Test name
Test status
Simulation time 62527538 ps
CPU time 1.55 seconds
Started Feb 26 03:17:04 PM PST 24
Finished Feb 26 03:17:06 PM PST 24
Peak memory 209968 kb
Host smart-4fbf0294-275e-47e9-b304-dd2bb618f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236327301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2236327301
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2644792508
Short name T717
Test name
Test status
Simulation time 65624227 ps
CPU time 0.76 seconds
Started Feb 26 03:17:06 PM PST 24
Finished Feb 26 03:17:07 PM PST 24
Peak memory 205800 kb
Host smart-a4930637-29ca-4f5b-b00f-05337d30fd44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644792508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2644792508
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.897423909
Short name T10
Test name
Test status
Simulation time 195332520 ps
CPU time 3.39 seconds
Started Feb 26 03:17:05 PM PST 24
Finished Feb 26 03:17:08 PM PST 24
Peak memory 221136 kb
Host smart-1a7ac842-5eaa-4aa4-97dc-33079ca2c7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897423909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.897423909
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1630959684
Short name T639
Test name
Test status
Simulation time 408817025 ps
CPU time 4.29 seconds
Started Feb 26 03:17:03 PM PST 24
Finished Feb 26 03:17:07 PM PST 24
Peak memory 209320 kb
Host smart-b267d9b0-ebb3-4920-bc0a-94b54768246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630959684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1630959684
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2544622733
Short name T21
Test name
Test status
Simulation time 273156260 ps
CPU time 7.1 seconds
Started Feb 26 03:17:08 PM PST 24
Finished Feb 26 03:17:16 PM PST 24
Peak memory 219612 kb
Host smart-a3407d62-69e3-484f-addb-7164bce36b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544622733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2544622733
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1123957952
Short name T958
Test name
Test status
Simulation time 118890602 ps
CPU time 5.41 seconds
Started Feb 26 03:17:08 PM PST 24
Finished Feb 26 03:17:13 PM PST 24
Peak memory 222464 kb
Host smart-c2af9427-2645-41dd-9684-66bf3f0970bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123957952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1123957952
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2288145163
Short name T935
Test name
Test status
Simulation time 127264344 ps
CPU time 3.94 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:15 PM PST 24
Peak memory 209276 kb
Host smart-cfe9c0ef-8af3-4b51-bbc1-7317c006f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288145163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2288145163
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1275883464
Short name T897
Test name
Test status
Simulation time 5930228133 ps
CPU time 66.31 seconds
Started Feb 26 03:17:02 PM PST 24
Finished Feb 26 03:18:08 PM PST 24
Peak memory 209988 kb
Host smart-638a7d5c-f643-4671-bc43-77515bb798d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275883464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1275883464
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2849696377
Short name T791
Test name
Test status
Simulation time 135854121 ps
CPU time 2.56 seconds
Started Feb 26 03:17:04 PM PST 24
Finished Feb 26 03:17:07 PM PST 24
Peak memory 207120 kb
Host smart-59cf2c06-5259-41e3-83d1-8ea7e8c48ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849696377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2849696377
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1611187830
Short name T782
Test name
Test status
Simulation time 49012988 ps
CPU time 2.98 seconds
Started Feb 26 03:17:07 PM PST 24
Finished Feb 26 03:17:10 PM PST 24
Peak memory 208872 kb
Host smart-a4c2b243-67d2-41d5-8119-68aa08679687
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611187830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1611187830
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1468542150
Short name T648
Test name
Test status
Simulation time 102304562 ps
CPU time 3.99 seconds
Started Feb 26 03:17:03 PM PST 24
Finished Feb 26 03:17:08 PM PST 24
Peak memory 208676 kb
Host smart-86e0c4e9-490b-4999-b5fb-19e568ba8301
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468542150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1468542150
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2945834835
Short name T580
Test name
Test status
Simulation time 92376733 ps
CPU time 4.16 seconds
Started Feb 26 03:17:01 PM PST 24
Finished Feb 26 03:17:05 PM PST 24
Peak memory 206832 kb
Host smart-0bd92be7-c32f-47cc-a572-7d319cbc8014
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945834835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2945834835
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2173950611
Short name T697
Test name
Test status
Simulation time 32135228 ps
CPU time 1.79 seconds
Started Feb 26 03:17:06 PM PST 24
Finished Feb 26 03:17:09 PM PST 24
Peak memory 208116 kb
Host smart-2a4cacd1-f25f-4142-8ca6-844cd8c1dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173950611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2173950611
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1507132741
Short name T378
Test name
Test status
Simulation time 91656539 ps
CPU time 3.86 seconds
Started Feb 26 03:17:03 PM PST 24
Finished Feb 26 03:17:07 PM PST 24
Peak memory 208584 kb
Host smart-4137fe48-25ab-4f9f-85b9-532d4c52cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507132741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1507132741
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3718753820
Short name T310
Test name
Test status
Simulation time 4122554682 ps
CPU time 18.54 seconds
Started Feb 26 03:17:09 PM PST 24
Finished Feb 26 03:17:27 PM PST 24
Peak memory 221660 kb
Host smart-0e3cc22d-87b8-4d61-bb76-f1852d40075c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718753820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3718753820
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3774442797
Short name T607
Test name
Test status
Simulation time 351895631 ps
CPU time 3.15 seconds
Started Feb 26 03:17:10 PM PST 24
Finished Feb 26 03:17:14 PM PST 24
Peak memory 217944 kb
Host smart-a5ee9067-9984-4d0c-8fa7-93611f202582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774442797 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3774442797
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2350028368
Short name T942
Test name
Test status
Simulation time 1499415082 ps
CPU time 10.08 seconds
Started Feb 26 03:17:07 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 207772 kb
Host smart-af286790-a9a4-49ed-8ffc-d9c2f626c65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350028368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2350028368
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3927110365
Short name T1005
Test name
Test status
Simulation time 281988957 ps
CPU time 3.05 seconds
Started Feb 26 03:17:07 PM PST 24
Finished Feb 26 03:17:10 PM PST 24
Peak memory 210228 kb
Host smart-d13594b0-aa4d-4fb0-ba4a-81ec51e08f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927110365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3927110365
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.752468172
Short name T859
Test name
Test status
Simulation time 16924982 ps
CPU time 1 seconds
Started Feb 26 03:17:10 PM PST 24
Finished Feb 26 03:17:11 PM PST 24
Peak memory 206020 kb
Host smart-8f6d1678-7285-4a41-ab56-6a08f41add29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752468172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.752468172
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3238712565
Short name T403
Test name
Test status
Simulation time 150195924 ps
CPU time 7.57 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:19 PM PST 24
Peak memory 214284 kb
Host smart-10d483c1-5a95-42e2-b5a3-02746b5afd9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238712565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3238712565
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.824795161
Short name T741
Test name
Test status
Simulation time 64634134 ps
CPU time 3.93 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:15 PM PST 24
Peak memory 207616 kb
Host smart-dc265db8-9b89-430f-bdd9-5bd2a4363bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824795161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.824795161
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.494228258
Short name T73
Test name
Test status
Simulation time 412474825 ps
CPU time 11.06 seconds
Started Feb 26 03:17:15 PM PST 24
Finished Feb 26 03:17:26 PM PST 24
Peak memory 218252 kb
Host smart-eb891391-c788-4d46-9109-e76d148a3812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494228258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.494228258
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3865833101
Short name T84
Test name
Test status
Simulation time 158899907 ps
CPU time 4.31 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:19 PM PST 24
Peak memory 208416 kb
Host smart-fd6f190f-d734-4144-9207-f0149d22a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865833101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3865833101
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2628320360
Short name T273
Test name
Test status
Simulation time 222280760 ps
CPU time 4.07 seconds
Started Feb 26 03:17:10 PM PST 24
Finished Feb 26 03:17:14 PM PST 24
Peak memory 211380 kb
Host smart-cccab50e-773a-40ef-b453-d24190337101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628320360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2628320360
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4241881965
Short name T873
Test name
Test status
Simulation time 50519865 ps
CPU time 3.31 seconds
Started Feb 26 03:17:16 PM PST 24
Finished Feb 26 03:17:20 PM PST 24
Peak memory 208156 kb
Host smart-879c8d70-3433-42d5-aa66-74a3ff02cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241881965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4241881965
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.775365611
Short name T813
Test name
Test status
Simulation time 156124608 ps
CPU time 3.84 seconds
Started Feb 26 03:17:04 PM PST 24
Finished Feb 26 03:17:09 PM PST 24
Peak memory 207232 kb
Host smart-d9657c49-c6eb-4eca-b583-bb12d96803b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775365611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.775365611
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4217345157
Short name T1000
Test name
Test status
Simulation time 60265206 ps
CPU time 3.07 seconds
Started Feb 26 03:17:07 PM PST 24
Finished Feb 26 03:17:10 PM PST 24
Peak memory 206868 kb
Host smart-28814476-0d9c-4398-bd5c-320e123c0ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217345157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4217345157
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1323629624
Short name T1027
Test name
Test status
Simulation time 215489511 ps
CPU time 3.83 seconds
Started Feb 26 03:17:06 PM PST 24
Finished Feb 26 03:17:11 PM PST 24
Peak memory 208724 kb
Host smart-1792d46c-35f6-4ef7-815e-578f64c3c23e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323629624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1323629624
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3067592455
Short name T187
Test name
Test status
Simulation time 1572430162 ps
CPU time 22.6 seconds
Started Feb 26 03:17:12 PM PST 24
Finished Feb 26 03:17:34 PM PST 24
Peak memory 208468 kb
Host smart-7d9c0581-e921-4e9d-ad16-68760efbd8d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067592455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3067592455
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2655055816
Short name T343
Test name
Test status
Simulation time 78339334 ps
CPU time 1.91 seconds
Started Feb 26 03:17:07 PM PST 24
Finished Feb 26 03:17:09 PM PST 24
Peak memory 206896 kb
Host smart-ec716cd8-f5c5-4bf1-81f7-4441499556e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655055816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2655055816
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.682166774
Short name T753
Test name
Test status
Simulation time 62328883 ps
CPU time 3.4 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:14 PM PST 24
Peak memory 209796 kb
Host smart-7f8704c5-8a74-4e55-87b0-cb526ecb76fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682166774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.682166774
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.49337491
Short name T620
Test name
Test status
Simulation time 235280356 ps
CPU time 2.84 seconds
Started Feb 26 03:17:04 PM PST 24
Finished Feb 26 03:17:08 PM PST 24
Peak memory 206672 kb
Host smart-2a3819b3-1c82-478e-8d15-edf93ff5bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49337491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.49337491
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3055998977
Short name T692
Test name
Test status
Simulation time 1057124928 ps
CPU time 5.64 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:21 PM PST 24
Peak memory 222568 kb
Host smart-9b887f79-b0a8-4e86-9b34-c42083080e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055998977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3055998977
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2104060037
Short name T326
Test name
Test status
Simulation time 112315015 ps
CPU time 4.44 seconds
Started Feb 26 03:17:12 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 207804 kb
Host smart-6e0f4fe3-4e7a-465c-9d74-b91ea77bf8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104060037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2104060037
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.357928601
Short name T849
Test name
Test status
Simulation time 88149846 ps
CPU time 1.56 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:12 PM PST 24
Peak memory 209848 kb
Host smart-f21d05b9-3086-49f9-8547-5757d56f89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357928601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.357928601
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4291480696
Short name T946
Test name
Test status
Simulation time 39844357 ps
CPU time 0.85 seconds
Started Feb 26 03:17:27 PM PST 24
Finished Feb 26 03:17:28 PM PST 24
Peak memory 205880 kb
Host smart-1a4577dc-cb5e-4cbb-b2c2-0c0992ce1f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291480696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4291480696
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1220753758
Short name T413
Test name
Test status
Simulation time 169772872 ps
CPU time 3.19 seconds
Started Feb 26 03:17:13 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 214992 kb
Host smart-0ca0e76e-f659-4cfb-b91a-a109ec4b1f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220753758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1220753758
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.857605690
Short name T356
Test name
Test status
Simulation time 458003743 ps
CPU time 10.93 seconds
Started Feb 26 03:17:25 PM PST 24
Finished Feb 26 03:17:36 PM PST 24
Peak memory 221480 kb
Host smart-38d508b4-2dae-40b0-be55-d15ba9e9aa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857605690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.857605690
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1154307917
Short name T665
Test name
Test status
Simulation time 208519832 ps
CPU time 5.36 seconds
Started Feb 26 03:17:27 PM PST 24
Finished Feb 26 03:17:33 PM PST 24
Peak memory 218284 kb
Host smart-8072bbe9-2984-45c1-8443-80ecadf0c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154307917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1154307917
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.162128773
Short name T292
Test name
Test status
Simulation time 6542603275 ps
CPU time 63.39 seconds
Started Feb 26 03:17:17 PM PST 24
Finished Feb 26 03:18:21 PM PST 24
Peak memory 224880 kb
Host smart-4af1ed41-8bde-45ab-b3dd-fccbc5a9709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162128773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.162128773
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1547156452
Short name T53
Test name
Test status
Simulation time 188686557 ps
CPU time 3.71 seconds
Started Feb 26 03:17:29 PM PST 24
Finished Feb 26 03:17:33 PM PST 24
Peak memory 208836 kb
Host smart-c858c215-a472-4697-b214-55850d0e9307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547156452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1547156452
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2747988991
Short name T615
Test name
Test status
Simulation time 241998924 ps
CPU time 3.63 seconds
Started Feb 26 03:17:13 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 207360 kb
Host smart-ba4481f4-455f-42d6-98d9-68759b708e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747988991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2747988991
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1846087656
Short name T299
Test name
Test status
Simulation time 165980406 ps
CPU time 3.68 seconds
Started Feb 26 03:17:13 PM PST 24
Finished Feb 26 03:17:16 PM PST 24
Peak memory 207080 kb
Host smart-a91bcc15-3b50-4c3f-81a1-41d1a157661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846087656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1846087656
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1811896990
Short name T685
Test name
Test status
Simulation time 73391010 ps
CPU time 3.43 seconds
Started Feb 26 03:17:12 PM PST 24
Finished Feb 26 03:17:16 PM PST 24
Peak memory 208400 kb
Host smart-d28c99ba-9611-4018-bec3-07e446d4b82e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811896990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1811896990
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4072745109
Short name T324
Test name
Test status
Simulation time 103542870 ps
CPU time 4.31 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:15 PM PST 24
Peak memory 206848 kb
Host smart-3db06694-0130-44d1-81b3-781af7493da4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072745109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4072745109
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2629789405
Short name T581
Test name
Test status
Simulation time 94062205 ps
CPU time 3.58 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:18 PM PST 24
Peak memory 206712 kb
Host smart-2cf89adf-6e29-49d6-b330-924437c53a8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629789405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2629789405
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3870967690
Short name T906
Test name
Test status
Simulation time 74737693 ps
CPU time 3.05 seconds
Started Feb 26 03:17:19 PM PST 24
Finished Feb 26 03:17:23 PM PST 24
Peak memory 215868 kb
Host smart-de7cdec5-305d-4ab3-b28e-9377df4e9611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870967690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3870967690
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.94342110
Short name T560
Test name
Test status
Simulation time 248603017 ps
CPU time 2.78 seconds
Started Feb 26 03:17:11 PM PST 24
Finished Feb 26 03:17:14 PM PST 24
Peak memory 208476 kb
Host smart-149146d8-9230-4110-9cf5-5807cf524975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94342110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.94342110
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1248320860
Short name T296
Test name
Test status
Simulation time 273657782 ps
CPU time 8.78 seconds
Started Feb 26 03:17:23 PM PST 24
Finished Feb 26 03:17:32 PM PST 24
Peak memory 222360 kb
Host smart-121c61c2-e19f-4ba9-9795-26f71538424f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248320860 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1248320860
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1335413382
Short name T928
Test name
Test status
Simulation time 1556055917 ps
CPU time 12.21 seconds
Started Feb 26 03:17:16 PM PST 24
Finished Feb 26 03:17:28 PM PST 24
Peak memory 218304 kb
Host smart-76f0fd13-0db1-4182-8812-2e51ad145b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335413382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1335413382
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1390694233
Short name T1055
Test name
Test status
Simulation time 159652469 ps
CPU time 2.46 seconds
Started Feb 26 03:17:28 PM PST 24
Finished Feb 26 03:17:31 PM PST 24
Peak memory 210044 kb
Host smart-572a1fb8-bbd3-43a1-a22e-74f844e45d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390694233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1390694233
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1532612637
Short name T690
Test name
Test status
Simulation time 31454968 ps
CPU time 0.7 seconds
Started Feb 26 03:17:31 PM PST 24
Finished Feb 26 03:17:33 PM PST 24
Peak memory 205840 kb
Host smart-886945fa-18f7-4a01-a786-cca831cd3ad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532612637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1532612637
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1977063747
Short name T900
Test name
Test status
Simulation time 534406846 ps
CPU time 17.42 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 222524 kb
Host smart-c67f684f-2f33-4b0b-abfc-3c81ff84a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977063747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1977063747
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2392413721
Short name T816
Test name
Test status
Simulation time 691334377 ps
CPU time 2.46 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:17 PM PST 24
Peak memory 207892 kb
Host smart-ed4620a5-4ec2-4426-a86d-03fc6627ea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392413721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2392413721
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.275023186
Short name T78
Test name
Test status
Simulation time 409791668 ps
CPU time 6.46 seconds
Started Feb 26 03:17:21 PM PST 24
Finished Feb 26 03:17:28 PM PST 24
Peak memory 214300 kb
Host smart-f19f5b1d-a50f-40ec-9ed0-0a96c7d41afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275023186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.275023186
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1931206971
Short name T275
Test name
Test status
Simulation time 156117400 ps
CPU time 6.9 seconds
Started Feb 26 03:17:27 PM PST 24
Finished Feb 26 03:17:34 PM PST 24
Peak memory 222288 kb
Host smart-185720d8-e6b2-4480-a66d-6ca400ae158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931206971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1931206971
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3868380055
Short name T50
Test name
Test status
Simulation time 287180055 ps
CPU time 5.24 seconds
Started Feb 26 03:17:20 PM PST 24
Finished Feb 26 03:17:25 PM PST 24
Peak memory 208716 kb
Host smart-b91e52a9-e2a7-40bd-adce-a42d89fed371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868380055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3868380055
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.157889722
Short name T847
Test name
Test status
Simulation time 320249618 ps
CPU time 4.38 seconds
Started Feb 26 03:17:17 PM PST 24
Finished Feb 26 03:17:22 PM PST 24
Peak memory 209704 kb
Host smart-56648713-a4b7-4321-9afd-cebfb4d8b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157889722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.157889722
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2895828201
Short name T738
Test name
Test status
Simulation time 848258757 ps
CPU time 6.18 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:17:31 PM PST 24
Peak memory 208716 kb
Host smart-0709b8a8-8be9-4985-a2df-039956e02588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895828201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2895828201
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2935740049
Short name T357
Test name
Test status
Simulation time 672850532 ps
CPU time 3.97 seconds
Started Feb 26 03:17:18 PM PST 24
Finished Feb 26 03:17:23 PM PST 24
Peak memory 208780 kb
Host smart-ed1fcad1-138d-4dc6-9dc2-a009452bec0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935740049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2935740049
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3907112366
Short name T727
Test name
Test status
Simulation time 43309955 ps
CPU time 2.62 seconds
Started Feb 26 03:17:28 PM PST 24
Finished Feb 26 03:17:31 PM PST 24
Peak memory 208148 kb
Host smart-4c9e3206-fc89-4a62-8d2e-390395d164b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907112366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3907112366
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3400867587
Short name T545
Test name
Test status
Simulation time 587636730 ps
CPU time 3.08 seconds
Started Feb 26 03:17:14 PM PST 24
Finished Feb 26 03:17:18 PM PST 24
Peak memory 206796 kb
Host smart-32a927d4-20a2-4c37-bc51-e22c1162c250
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400867587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3400867587
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4230920245
Short name T322
Test name
Test status
Simulation time 167899428 ps
CPU time 3.21 seconds
Started Feb 26 03:17:19 PM PST 24
Finished Feb 26 03:17:23 PM PST 24
Peak memory 208996 kb
Host smart-7ccb5939-67ed-4ff6-b25b-d3c3cf61256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230920245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4230920245
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4159218263
Short name T899
Test name
Test status
Simulation time 30018958 ps
CPU time 2.19 seconds
Started Feb 26 03:17:23 PM PST 24
Finished Feb 26 03:17:25 PM PST 24
Peak memory 206756 kb
Host smart-aa0895c1-ea53-491e-a7d3-cbfeb0195b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159218263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4159218263
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3876945347
Short name T62
Test name
Test status
Simulation time 13842251899 ps
CPU time 319.8 seconds
Started Feb 26 03:17:27 PM PST 24
Finished Feb 26 03:22:47 PM PST 24
Peak memory 220892 kb
Host smart-d14f4e13-d35e-406a-b619-82e3b96f0ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876945347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3876945347
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1712090595
Short name T803
Test name
Test status
Simulation time 283247101 ps
CPU time 5.48 seconds
Started Feb 26 03:17:19 PM PST 24
Finished Feb 26 03:17:25 PM PST 24
Peak memory 222512 kb
Host smart-b0526b5e-8eac-4436-b2bb-079818ffe006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712090595 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1712090595
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.156546265
Short name T773
Test name
Test status
Simulation time 530273577 ps
CPU time 3.68 seconds
Started Feb 26 03:17:18 PM PST 24
Finished Feb 26 03:17:22 PM PST 24
Peak memory 208236 kb
Host smart-b78bf959-25a4-4aa1-b230-e897295e843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156546265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.156546265
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2423981076
Short name T597
Test name
Test status
Simulation time 136536483 ps
CPU time 1.97 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:17:26 PM PST 24
Peak memory 210092 kb
Host smart-f253206c-3f29-442b-9ce7-a9c95a3baf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423981076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2423981076
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2022840685
Short name T850
Test name
Test status
Simulation time 17333641 ps
CPU time 0.73 seconds
Started Feb 26 03:17:32 PM PST 24
Finished Feb 26 03:17:33 PM PST 24
Peak memory 205880 kb
Host smart-52f775c5-b2d1-40ad-92ab-f4a36ff1ee93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022840685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2022840685
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2718984124
Short name T938
Test name
Test status
Simulation time 63488415 ps
CPU time 2.87 seconds
Started Feb 26 03:17:29 PM PST 24
Finished Feb 26 03:17:32 PM PST 24
Peak memory 214316 kb
Host smart-7f1ba365-3ea9-47bd-b711-f47424150b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718984124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2718984124
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3331885717
Short name T1071
Test name
Test status
Simulation time 194725234 ps
CPU time 6.4 seconds
Started Feb 26 03:17:36 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 214368 kb
Host smart-da536045-b18b-41fe-be99-7905581f069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331885717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3331885717
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1691350131
Short name T70
Test name
Test status
Simulation time 142155146 ps
CPU time 2.32 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:17:27 PM PST 24
Peak memory 207352 kb
Host smart-f17bc6f4-c3b5-4c1e-9ec6-12775cf912a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691350131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1691350131
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2569460898
Short name T823
Test name
Test status
Simulation time 1453553735 ps
CPU time 10.35 seconds
Started Feb 26 03:17:25 PM PST 24
Finished Feb 26 03:17:36 PM PST 24
Peak memory 214228 kb
Host smart-9c16e13c-363f-422d-9871-d5c5be8a7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569460898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2569460898
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4192384806
Short name T185
Test name
Test status
Simulation time 1055976070 ps
CPU time 14.42 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:56 PM PST 24
Peak memory 214256 kb
Host smart-2c83a572-c170-4b5b-9860-950f3dfb104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192384806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4192384806
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2436961403
Short name T700
Test name
Test status
Simulation time 137375080 ps
CPU time 3.61 seconds
Started Feb 26 03:17:34 PM PST 24
Finished Feb 26 03:17:38 PM PST 24
Peak memory 209596 kb
Host smart-27e1f2f8-f244-4f2e-b40e-bec62b0d5602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436961403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2436961403
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1458896925
Short name T395
Test name
Test status
Simulation time 1908205984 ps
CPU time 5.15 seconds
Started Feb 26 03:17:27 PM PST 24
Finished Feb 26 03:17:33 PM PST 24
Peak memory 207844 kb
Host smart-2b06d424-58ce-4351-b921-119ee0ac346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458896925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1458896925
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2636568117
Short name T295
Test name
Test status
Simulation time 456674492 ps
CPU time 10.05 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:17:35 PM PST 24
Peak memory 208344 kb
Host smart-75a995f1-357c-4c30-9b0f-23ac450d6d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636568117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2636568117
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2283106544
Short name T92
Test name
Test status
Simulation time 726331794 ps
CPU time 8.22 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:17:32 PM PST 24
Peak memory 208084 kb
Host smart-81e1a5a8-82f6-445b-aaa8-b876ea3571e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283106544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2283106544
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3626040046
Short name T704
Test name
Test status
Simulation time 5346478951 ps
CPU time 36.18 seconds
Started Feb 26 03:17:24 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 207840 kb
Host smart-1f4bc91a-49ff-4a14-b9e7-4345f13324b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626040046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3626040046
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2998523685
Short name T955
Test name
Test status
Simulation time 882459031 ps
CPU time 23.8 seconds
Started Feb 26 03:17:20 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 207848 kb
Host smart-7e9cdfd8-cc25-4f8a-9680-c49492bcaa5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998523685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2998523685
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2124388264
Short name T1002
Test name
Test status
Simulation time 1812721491 ps
CPU time 19.03 seconds
Started Feb 26 03:17:26 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 209424 kb
Host smart-4c422501-a20b-4400-a329-0e55ba75f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124388264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2124388264
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4260147928
Short name T675
Test name
Test status
Simulation time 207492545 ps
CPU time 2.6 seconds
Started Feb 26 03:17:34 PM PST 24
Finished Feb 26 03:17:37 PM PST 24
Peak memory 206812 kb
Host smart-6e9adb92-8e31-4a68-a52b-3b2d39204421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260147928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4260147928
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.923613718
Short name T678
Test name
Test status
Simulation time 767309577 ps
CPU time 5.53 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:40 PM PST 24
Peak memory 215316 kb
Host smart-ce822f74-5116-4ef7-855c-eb2fc3064723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923613718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.923613718
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4137790289
Short name T951
Test name
Test status
Simulation time 289903944 ps
CPU time 6.08 seconds
Started Feb 26 03:17:30 PM PST 24
Finished Feb 26 03:17:37 PM PST 24
Peak memory 222624 kb
Host smart-562df8a2-feaf-476d-aebf-0b0dbf598fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137790289 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4137790289
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3562565041
Short name T739
Test name
Test status
Simulation time 169386752 ps
CPU time 3.13 seconds
Started Feb 26 03:17:25 PM PST 24
Finished Feb 26 03:17:28 PM PST 24
Peak memory 222460 kb
Host smart-b089493f-2c0d-422e-beb2-f0e267ace55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562565041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3562565041
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1183905933
Short name T55
Test name
Test status
Simulation time 152528022 ps
CPU time 3.87 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 210016 kb
Host smart-b924e218-8fdf-4442-9324-e7714abbce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183905933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1183905933
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4185418122
Short name T415
Test name
Test status
Simulation time 77795889 ps
CPU time 0.92 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:39 PM PST 24
Peak memory 205876 kb
Host smart-b98f3aea-65b4-4303-9e2e-cbe79d042b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185418122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4185418122
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2550429935
Short name T26
Test name
Test status
Simulation time 591405700 ps
CPU time 5.17 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 210748 kb
Host smart-8773f883-c81f-4a38-baf4-d0af170fd7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550429935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2550429935
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.175509933
Short name T316
Test name
Test status
Simulation time 369999519 ps
CPU time 2.51 seconds
Started Feb 26 03:17:28 PM PST 24
Finished Feb 26 03:17:31 PM PST 24
Peak memory 217996 kb
Host smart-0233085b-32d5-407f-a6aa-16fced58a259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175509933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.175509933
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3222254238
Short name T230
Test name
Test status
Simulation time 172286981 ps
CPU time 4.48 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:43 PM PST 24
Peak memory 211828 kb
Host smart-174e962a-90f6-4dcf-8198-dd7cea0b5e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222254238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3222254238
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2235645521
Short name T213
Test name
Test status
Simulation time 45429721 ps
CPU time 3.07 seconds
Started Feb 26 03:17:28 PM PST 24
Finished Feb 26 03:17:32 PM PST 24
Peak memory 216472 kb
Host smart-f8d6dd16-d043-45de-b3ee-6fe68d85a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235645521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2235645521
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3061327809
Short name T818
Test name
Test status
Simulation time 3156256938 ps
CPU time 58.46 seconds
Started Feb 26 03:17:34 PM PST 24
Finished Feb 26 03:18:33 PM PST 24
Peak memory 221464 kb
Host smart-cb6ab9a4-5897-4a6c-a589-7666de943007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061327809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3061327809
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1245055685
Short name T602
Test name
Test status
Simulation time 46740287 ps
CPU time 1.92 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:43 PM PST 24
Peak memory 206740 kb
Host smart-f76d68bc-060a-4e1b-b009-abbaf38c6220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245055685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1245055685
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4193268364
Short name T794
Test name
Test status
Simulation time 91198853 ps
CPU time 2.7 seconds
Started Feb 26 03:17:26 PM PST 24
Finished Feb 26 03:17:29 PM PST 24
Peak memory 206872 kb
Host smart-762eb4dd-85c5-4814-b990-ae2c067ca766
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193268364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4193268364
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1128989957
Short name T1
Test name
Test status
Simulation time 1780950290 ps
CPU time 22.8 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:18:05 PM PST 24
Peak memory 207980 kb
Host smart-0341f317-4a76-41ca-b056-51d85f4d0852
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128989957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1128989957
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2408609933
Short name T682
Test name
Test status
Simulation time 3274273750 ps
CPU time 14.64 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:53 PM PST 24
Peak memory 208568 kb
Host smart-07bb5b34-779f-4d6f-ad95-593affc2fdf1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408609933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2408609933
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.694490578
Short name T1021
Test name
Test status
Simulation time 475714047 ps
CPU time 2.51 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 208988 kb
Host smart-82005f47-c527-472e-8044-b7ae2cb1620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694490578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.694490578
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3169077882
Short name T825
Test name
Test status
Simulation time 214495928 ps
CPU time 7.71 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:42 PM PST 24
Peak memory 207692 kb
Host smart-53c28c08-19bd-40ba-9210-a9e7ef41e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169077882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3169077882
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.961139974
Short name T809
Test name
Test status
Simulation time 82662946 ps
CPU time 3.49 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:42 PM PST 24
Peak memory 218020 kb
Host smart-eb6865e1-0949-4187-8a88-5c6dede28b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961139974 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.961139974
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1269857472
Short name T995
Test name
Test status
Simulation time 222402349 ps
CPU time 4.33 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 219764 kb
Host smart-865d99c2-5ef0-4344-89c4-93d2629f1c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269857472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1269857472
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3168324694
Short name T657
Test name
Test status
Simulation time 86382804 ps
CPU time 3.42 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 210296 kb
Host smart-03bcd025-9791-4e76-820d-ccb6ddb8c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168324694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3168324694
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2002685661
Short name T778
Test name
Test status
Simulation time 32308770 ps
CPU time 0.94 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 206032 kb
Host smart-497fe4f8-de0f-4fcf-9e37-1ca6ce261e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002685661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2002685661
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3005513851
Short name T25
Test name
Test status
Simulation time 93532531 ps
CPU time 3.9 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:37 PM PST 24
Peak memory 209704 kb
Host smart-00c0a8cb-37d1-452c-87d7-d0568dac03ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005513851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3005513851
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.418148622
Short name T638
Test name
Test status
Simulation time 403512406 ps
CPU time 2.85 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 207236 kb
Host smart-ed67bc37-5db0-44fc-b01b-81e3bd284a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418148622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.418148622
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1373890478
Short name T337
Test name
Test status
Simulation time 413491511 ps
CPU time 5.02 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:38 PM PST 24
Peak memory 219836 kb
Host smart-da977568-5021-4bea-9216-c10b320b0970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373890478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1373890478
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2186186441
Short name T291
Test name
Test status
Simulation time 529620238 ps
CPU time 8.66 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 214268 kb
Host smart-836d910c-34f1-4628-ab18-43212751f266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186186441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2186186441
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1105394662
Short name T979
Test name
Test status
Simulation time 120629088 ps
CPU time 4.78 seconds
Started Feb 26 03:17:34 PM PST 24
Finished Feb 26 03:17:39 PM PST 24
Peak memory 219420 kb
Host smart-694b3bd3-e2ba-4151-8ff2-daeea37947a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105394662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1105394662
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.365081031
Short name T247
Test name
Test status
Simulation time 183773055 ps
CPU time 5.91 seconds
Started Feb 26 03:17:32 PM PST 24
Finished Feb 26 03:17:38 PM PST 24
Peak memory 207912 kb
Host smart-adcbeefe-dc85-4291-9b0e-b81c64521dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365081031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.365081031
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2692327096
Short name T670
Test name
Test status
Simulation time 197457059 ps
CPU time 3.03 seconds
Started Feb 26 03:17:32 PM PST 24
Finished Feb 26 03:17:35 PM PST 24
Peak memory 206676 kb
Host smart-0bbf84dc-d814-48a1-8bef-45aecfbccc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692327096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2692327096
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2074155344
Short name T254
Test name
Test status
Simulation time 54254922 ps
CPU time 3.06 seconds
Started Feb 26 03:17:36 PM PST 24
Finished Feb 26 03:17:40 PM PST 24
Peak memory 208652 kb
Host smart-1fa343c2-8d3b-46c1-92a2-cb60adab2f69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074155344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2074155344
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2134827687
Short name T381
Test name
Test status
Simulation time 758396671 ps
CPU time 5.79 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 207884 kb
Host smart-b782f0ee-2289-4125-a6f8-11e930906152
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134827687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2134827687
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2516088027
Short name T1058
Test name
Test status
Simulation time 897704474 ps
CPU time 10.62 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:49 PM PST 24
Peak memory 208864 kb
Host smart-ee7a6828-3e70-4b32-993a-0cbd1fa92b19
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516088027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2516088027
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1158015091
Short name T694
Test name
Test status
Simulation time 221956829 ps
CPU time 2.04 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:36 PM PST 24
Peak memory 207116 kb
Host smart-9e6d8994-f4fe-44b7-b95c-cd1a4ab2fcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158015091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1158015091
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2826657195
Short name T568
Test name
Test status
Simulation time 224795587 ps
CPU time 2.96 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 206756 kb
Host smart-5599fc13-3069-41ca-a3f7-25a3b91b3ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826657195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2826657195
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3442266978
Short name T48
Test name
Test status
Simulation time 9530914782 ps
CPU time 45.54 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:18:20 PM PST 24
Peak memory 216236 kb
Host smart-29fabb5c-a395-4599-b263-b377317d7bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442266978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3442266978
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1468429483
Short name T984
Test name
Test status
Simulation time 187853704 ps
CPU time 14.68 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:58 PM PST 24
Peak memory 220908 kb
Host smart-84d2a42b-c3e0-49fc-8270-60d93201e319
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468429483 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1468429483
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.981772671
Short name T345
Test name
Test status
Simulation time 242534935 ps
CPU time 4.43 seconds
Started Feb 26 03:17:35 PM PST 24
Finished Feb 26 03:17:40 PM PST 24
Peak memory 218248 kb
Host smart-ba76d7e5-1247-4fc0-b3c2-9cdfe87c6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981772671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.981772671
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2545991303
Short name T61
Test name
Test status
Simulation time 177687469 ps
CPU time 4.83 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 211088 kb
Host smart-702c4042-c8f3-433e-a6c4-f5ccfa7e0454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545991303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2545991303
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3018797318
Short name T866
Test name
Test status
Simulation time 30738974 ps
CPU time 1.05 seconds
Started Feb 26 03:17:36 PM PST 24
Finished Feb 26 03:17:38 PM PST 24
Peak memory 205956 kb
Host smart-4e3b0dcd-226e-437d-87c9-2fa141b6edf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018797318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3018797318
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1608747242
Short name T406
Test name
Test status
Simulation time 334041626 ps
CPU time 9.74 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 214364 kb
Host smart-20c8ea3f-6fde-482f-a389-ccf456dc44d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608747242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1608747242
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2735755005
Short name T975
Test name
Test status
Simulation time 606935685 ps
CPU time 5.75 seconds
Started Feb 26 03:17:33 PM PST 24
Finished Feb 26 03:17:40 PM PST 24
Peak memory 220220 kb
Host smart-5817ff88-bf0c-489b-a37a-35d99bfd0701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735755005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2735755005
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.516758157
Short name T383
Test name
Test status
Simulation time 128125467 ps
CPU time 2.44 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 214344 kb
Host smart-13e45ef5-b51d-4d28-8259-3612c732c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516758157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.516758157
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2142216281
Short name T972
Test name
Test status
Simulation time 188093326 ps
CPU time 3.78 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 214396 kb
Host smart-28e6db63-926c-4b79-adfc-7f9c065e7512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142216281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2142216281
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3093659363
Short name T821
Test name
Test status
Simulation time 57202758 ps
CPU time 3.44 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:41 PM PST 24
Peak memory 210812 kb
Host smart-ecdd9132-cb7b-4a0c-9b03-0498536f45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093659363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3093659363
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3402447498
Short name T207
Test name
Test status
Simulation time 96496538 ps
CPU time 3.72 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 210356 kb
Host smart-ebc68252-37fd-4c73-a044-de76d5884ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402447498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3402447498
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.4051440707
Short name T810
Test name
Test status
Simulation time 79804282 ps
CPU time 3.82 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 207160 kb
Host smart-3a9af3a8-1373-4b8a-869f-843add31bf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051440707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4051440707
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2273941521
Short name T656
Test name
Test status
Simulation time 62827441 ps
CPU time 2.83 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 206956 kb
Host smart-dfe1ca47-1256-44dd-a26e-123f33e5d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273941521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2273941521
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2696408546
Short name T610
Test name
Test status
Simulation time 26212168 ps
CPU time 2.25 seconds
Started Feb 26 03:17:36 PM PST 24
Finished Feb 26 03:17:39 PM PST 24
Peak memory 208328 kb
Host smart-8309b0b8-180e-4862-a06b-8a9ec1ee65ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696408546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2696408546
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3014010610
Short name T1044
Test name
Test status
Simulation time 56650635 ps
CPU time 2.88 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:43 PM PST 24
Peak memory 208048 kb
Host smart-0e63ea35-d94a-4369-a29b-f511a747edf5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014010610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3014010610
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.170160484
Short name T939
Test name
Test status
Simulation time 134791746 ps
CPU time 2.17 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 208656 kb
Host smart-74e35f62-fe4f-454a-81a3-054315d44ab0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170160484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.170160484
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2106482861
Short name T689
Test name
Test status
Simulation time 317037802 ps
CPU time 3.6 seconds
Started Feb 26 03:17:36 PM PST 24
Finished Feb 26 03:17:40 PM PST 24
Peak memory 209524 kb
Host smart-38cdf7e2-97a4-49a9-bd67-ac9acd53a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106482861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2106482861
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3089562276
Short name T770
Test name
Test status
Simulation time 381407197 ps
CPU time 3.19 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 206812 kb
Host smart-90434a48-ec21-43e9-b54f-32b506b78f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089562276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3089562276
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1336762038
Short name T312
Test name
Test status
Simulation time 301007441 ps
CPU time 12.89 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 220428 kb
Host smart-2d9b636a-f175-4a37-aa41-afa0c4ff6da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336762038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1336762038
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3593287806
Short name T835
Test name
Test status
Simulation time 148960260 ps
CPU time 2.53 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 220860 kb
Host smart-2a49014c-6dd4-4032-94b5-6d4ed4de77b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593287806 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3593287806
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3599691835
Short name T969
Test name
Test status
Simulation time 699392066 ps
CPU time 16.36 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:18:00 PM PST 24
Peak memory 209068 kb
Host smart-e5c90691-4700-4ad5-8920-797b44410e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599691835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3599691835
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.118108613
Short name T613
Test name
Test status
Simulation time 74496767 ps
CPU time 2.84 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 209868 kb
Host smart-4c106b58-685d-4c58-a8de-502a1f412b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118108613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.118108613
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1607371336
Short name T1048
Test name
Test status
Simulation time 12747134 ps
CPU time 0.95 seconds
Started Feb 26 03:14:28 PM PST 24
Finished Feb 26 03:14:29 PM PST 24
Peak memory 206056 kb
Host smart-17ddc58f-f6fa-45df-ac7a-873fafecd7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607371336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1607371336
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1831212794
Short name T222
Test name
Test status
Simulation time 136863249 ps
CPU time 2.73 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 214308 kb
Host smart-f95a8cec-d0c4-41b4-9e98-a75cbff61b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831212794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1831212794
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3315295655
Short name T729
Test name
Test status
Simulation time 97275506 ps
CPU time 3.43 seconds
Started Feb 26 03:14:22 PM PST 24
Finished Feb 26 03:14:26 PM PST 24
Peak memory 210808 kb
Host smart-60fa0aba-2c8b-4e1a-932f-91ab8bddd778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315295655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3315295655
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2252279528
Short name T398
Test name
Test status
Simulation time 45679362 ps
CPU time 1.65 seconds
Started Feb 26 03:14:18 PM PST 24
Finished Feb 26 03:14:20 PM PST 24
Peak memory 208412 kb
Host smart-fa2787b9-0fec-4ba9-b2ad-267ca844b28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252279528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2252279528
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.644522651
Short name T943
Test name
Test status
Simulation time 152323745 ps
CPU time 4.94 seconds
Started Feb 26 03:14:24 PM PST 24
Finished Feb 26 03:14:30 PM PST 24
Peak memory 214244 kb
Host smart-f4a107bf-98df-471b-bfca-109fba00df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644522651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.644522651
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.591223956
Short name T892
Test name
Test status
Simulation time 99850105 ps
CPU time 1.84 seconds
Started Feb 26 03:14:22 PM PST 24
Finished Feb 26 03:14:25 PM PST 24
Peak memory 206920 kb
Host smart-f8942859-88c5-447e-b0ca-2d0c32fa02de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591223956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.591223956
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.178607799
Short name T676
Test name
Test status
Simulation time 219072921 ps
CPU time 4.99 seconds
Started Feb 26 03:14:19 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 209140 kb
Host smart-2510705c-cad7-4dcb-bc31-b935003a51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178607799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.178607799
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2326100542
Short name T90
Test name
Test status
Simulation time 40357668899 ps
CPU time 375.14 seconds
Started Feb 26 03:14:28 PM PST 24
Finished Feb 26 03:20:44 PM PST 24
Peak memory 311348 kb
Host smart-e0644a87-463c-4826-a028-6a6fed315d5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326100542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2326100542
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1057673381
Short name T774
Test name
Test status
Simulation time 196166494 ps
CPU time 2.45 seconds
Started Feb 26 03:14:21 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 206792 kb
Host smart-ae5e8321-2fdc-42e5-8e5f-606811bc79c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057673381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1057673381
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3637898914
Short name T668
Test name
Test status
Simulation time 966457420 ps
CPU time 10.52 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:31 PM PST 24
Peak memory 208088 kb
Host smart-7b9502a8-b582-4fb9-a2ca-e2d92c040748
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637898914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3637898914
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1463386280
Short name T793
Test name
Test status
Simulation time 73682739 ps
CPU time 3.5 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 208612 kb
Host smart-229c4dca-94b4-41df-b28c-009aa0603a7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463386280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1463386280
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3300162716
Short name T238
Test name
Test status
Simulation time 74904600 ps
CPU time 3.84 seconds
Started Feb 26 03:14:21 PM PST 24
Finished Feb 26 03:14:25 PM PST 24
Peak memory 208548 kb
Host smart-698cd43f-2ff9-4f35-8957-5f67aea3dc79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300162716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3300162716
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2330470178
Short name T758
Test name
Test status
Simulation time 357660099 ps
CPU time 6.14 seconds
Started Feb 26 03:14:23 PM PST 24
Finished Feb 26 03:14:31 PM PST 24
Peak memory 208704 kb
Host smart-77d9587c-5ae0-4d64-afdc-a61fc7b047c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330470178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2330470178
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3215722131
Short name T572
Test name
Test status
Simulation time 938422704 ps
CPU time 3.52 seconds
Started Feb 26 03:14:20 PM PST 24
Finished Feb 26 03:14:24 PM PST 24
Peak memory 208364 kb
Host smart-54c751c5-f6d7-45b9-b7b1-5dbe6a802276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215722131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3215722131
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1840559151
Short name T650
Test name
Test status
Simulation time 1623946591 ps
CPU time 21.66 seconds
Started Feb 26 03:14:24 PM PST 24
Finished Feb 26 03:14:46 PM PST 24
Peak memory 215668 kb
Host smart-95949de4-dd60-45eb-b48e-6ff822cf325e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840559151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1840559151
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2460205284
Short name T824
Test name
Test status
Simulation time 146652207 ps
CPU time 6.82 seconds
Started Feb 26 03:14:28 PM PST 24
Finished Feb 26 03:14:35 PM PST 24
Peak memory 222608 kb
Host smart-700f68b3-567e-49d5-8983-2a8c99c53a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460205284 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2460205284
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1211914992
Short name T841
Test name
Test status
Simulation time 182356887 ps
CPU time 5.62 seconds
Started Feb 26 03:14:19 PM PST 24
Finished Feb 26 03:14:25 PM PST 24
Peak memory 214280 kb
Host smart-4912a787-95d4-408b-b8e9-950fe06e71e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211914992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1211914992
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3610690507
Short name T633
Test name
Test status
Simulation time 250511918 ps
CPU time 3.5 seconds
Started Feb 26 03:14:24 PM PST 24
Finished Feb 26 03:14:28 PM PST 24
Peak memory 210480 kb
Host smart-1e48e85d-d77b-419e-9448-e671393cb8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610690507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3610690507
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2656807677
Short name T789
Test name
Test status
Simulation time 37173310 ps
CPU time 0.7 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 205828 kb
Host smart-994eea02-e228-4a6d-9169-101c10dad307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656807677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2656807677
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4103933690
Short name T130
Test name
Test status
Simulation time 255722260 ps
CPU time 8.24 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:53 PM PST 24
Peak memory 215824 kb
Host smart-685f53e6-5b1d-4f51-8f04-f734e6853e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103933690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4103933690
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1289717017
Short name T783
Test name
Test status
Simulation time 37794622 ps
CPU time 1.65 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:42 PM PST 24
Peak memory 209176 kb
Host smart-0e79e783-0330-4130-b15d-3aefbd6315f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289717017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1289717017
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.888773458
Short name T870
Test name
Test status
Simulation time 1223683047 ps
CPU time 7.9 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:51 PM PST 24
Peak memory 214308 kb
Host smart-3c754a1a-e2ff-48ff-920d-b733de40186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888773458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.888773458
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1232552436
Short name T255
Test name
Test status
Simulation time 96318605 ps
CPU time 4.81 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 222412 kb
Host smart-3fd36067-3a79-4b51-9d84-5dd76bf3b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232552436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1232552436
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.643437662
Short name T624
Test name
Test status
Simulation time 163126557 ps
CPU time 5.36 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 219736 kb
Host smart-02187280-b29b-409b-a9c7-d4db474fe17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643437662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.643437662
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.400375932
Short name T750
Test name
Test status
Simulation time 788593644 ps
CPU time 8.26 seconds
Started Feb 26 03:17:37 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 214304 kb
Host smart-b50a7814-bfa3-49d8-8db3-ec4b2332c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400375932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.400375932
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3218144309
Short name T965
Test name
Test status
Simulation time 82900260 ps
CPU time 1.82 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 206900 kb
Host smart-35416f9e-2273-448e-83f4-446f7dafb326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218144309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3218144309
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4037237645
Short name T1033
Test name
Test status
Simulation time 562526686 ps
CPU time 5.31 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 208624 kb
Host smart-00f62933-9dda-436e-bcd7-d371442b585a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037237645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4037237645
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1731456435
Short name T584
Test name
Test status
Simulation time 166084911 ps
CPU time 2.49 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 206856 kb
Host smart-ec7d0bb9-c6cd-490a-aa2d-1a2b1225a3e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731456435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1731456435
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1357098742
Short name T696
Test name
Test status
Simulation time 196376032 ps
CPU time 3.05 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 206816 kb
Host smart-1728df33-1803-4528-8407-e623f7c0c865
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357098742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1357098742
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4100546687
Short name T173
Test name
Test status
Simulation time 2860538179 ps
CPU time 19.25 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 214312 kb
Host smart-2764cca3-089b-41b0-bb85-1a6ca92a003c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100546687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4100546687
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1170171816
Short name T808
Test name
Test status
Simulation time 68413561 ps
CPU time 3.03 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 206136 kb
Host smart-3d72b231-89c9-4e2e-a6bf-4b5aa2916a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170171816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1170171816
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3222624297
Short name T826
Test name
Test status
Simulation time 350749123 ps
CPU time 4.12 seconds
Started Feb 26 03:17:39 PM PST 24
Finished Feb 26 03:17:44 PM PST 24
Peak memory 222548 kb
Host smart-a4d31dba-8a91-494c-aeba-73c2537a2d5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222624297 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3222624297
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2195085725
Short name T863
Test name
Test status
Simulation time 170817943 ps
CPU time 5.29 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:51 PM PST 24
Peak memory 209248 kb
Host smart-44eb274b-6478-4821-9c13-8ddb0e49b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195085725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2195085725
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3098115208
Short name T157
Test name
Test status
Simulation time 28641118 ps
CPU time 1.88 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 209908 kb
Host smart-3b4b079a-852e-44b1-a801-259dd4bb565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098115208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3098115208
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1557901630
Short name T617
Test name
Test status
Simulation time 27913640 ps
CPU time 0.75 seconds
Started Feb 26 03:17:47 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 205780 kb
Host smart-d2e71673-506e-4651-9a89-f908b64ea703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557901630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1557901630
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2631098120
Short name T399
Test name
Test status
Simulation time 3910069188 ps
CPU time 84.09 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:19:10 PM PST 24
Peak memory 214532 kb
Host smart-6b3c85be-ee2f-43ab-b270-6b8a5d8048c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631098120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2631098120
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3517304449
Short name T1059
Test name
Test status
Simulation time 67129195 ps
CPU time 2.02 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 207332 kb
Host smart-2417f101-2303-42c6-a692-ca7405879fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517304449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3517304449
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.535440682
Short name T83
Test name
Test status
Simulation time 185660216 ps
CPU time 5.75 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:49 PM PST 24
Peak memory 214276 kb
Host smart-c2891553-4b92-4af3-b97d-ebe2e849b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535440682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.535440682
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.961202834
Short name T740
Test name
Test status
Simulation time 64462346 ps
CPU time 3.29 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 209168 kb
Host smart-fbff4af5-6994-45a8-bf05-ef3bd1d90c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961202834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.961202834
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2902833595
Short name T904
Test name
Test status
Simulation time 1809139919 ps
CPU time 53.02 seconds
Started Feb 26 03:17:38 PM PST 24
Finished Feb 26 03:18:32 PM PST 24
Peak memory 209324 kb
Host smart-92ede1ab-a632-42d1-9a50-f9a9ab0e985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902833595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2902833595
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2684458924
Short name T830
Test name
Test status
Simulation time 1826120888 ps
CPU time 38.13 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:18:20 PM PST 24
Peak memory 208344 kb
Host smart-dcff3951-5613-4b81-9952-ec1959ae431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684458924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2684458924
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1895123888
Short name T658
Test name
Test status
Simulation time 434294115 ps
CPU time 3.71 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 208592 kb
Host smart-a1c832c3-bdc4-4b7d-8025-946407ae6d83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895123888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1895123888
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3314183401
Short name T905
Test name
Test status
Simulation time 2599960856 ps
CPU time 27.68 seconds
Started Feb 26 03:17:38 PM PST 24
Finished Feb 26 03:18:07 PM PST 24
Peak memory 208740 kb
Host smart-2d19af75-8613-4da4-afca-26417b3e0a19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314183401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3314183401
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4069318664
Short name T1012
Test name
Test status
Simulation time 52660443 ps
CPU time 2.72 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 208028 kb
Host smart-f57b75a6-b3ed-4eb0-a58f-48c6baecb113
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069318664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4069318664
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2299883854
Short name T667
Test name
Test status
Simulation time 88450933 ps
CPU time 3.91 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 207392 kb
Host smart-4fe26a8e-e80e-45b5-b49c-a5565064a931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299883854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2299883854
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2357790878
Short name T1052
Test name
Test status
Simulation time 56800952 ps
CPU time 2.84 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 207904 kb
Host smart-9073ffe0-4393-44f4-b2fd-5ead00dc6d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357790878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2357790878
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3834064375
Short name T922
Test name
Test status
Simulation time 163403813 ps
CPU time 3.95 seconds
Started Feb 26 03:17:41 PM PST 24
Finished Feb 26 03:17:46 PM PST 24
Peak memory 222644 kb
Host smart-2cd277ab-808d-4bf5-84e6-8af7b8c0e833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834064375 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3834064375
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4032284449
Short name T1020
Test name
Test status
Simulation time 48714569 ps
CPU time 3.36 seconds
Started Feb 26 03:17:43 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 207680 kb
Host smart-e7d1d909-6ac8-4278-b256-28e64528fbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032284449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4032284449
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.495012474
Short name T556
Test name
Test status
Simulation time 117897190 ps
CPU time 3.13 seconds
Started Feb 26 03:17:40 PM PST 24
Finished Feb 26 03:17:45 PM PST 24
Peak memory 210056 kb
Host smart-5298fae2-333d-440d-b301-2e8be4654864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495012474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.495012474
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2233201906
Short name T731
Test name
Test status
Simulation time 22636966 ps
CPU time 0.81 seconds
Started Feb 26 03:17:47 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 205864 kb
Host smart-194a4d19-f429-4faf-a3ec-589dc53407ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233201906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2233201906
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.17272314
Short name T409
Test name
Test status
Simulation time 109456046 ps
CPU time 4.29 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:49 PM PST 24
Peak memory 214252 kb
Host smart-a8704fd2-0a31-4604-814e-e27ad4b1c0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17272314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.17272314
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1418596201
Short name T40
Test name
Test status
Simulation time 191183715 ps
CPU time 5.39 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:54 PM PST 24
Peak memory 214272 kb
Host smart-af6657ee-881b-4786-8f81-47021637959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418596201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1418596201
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3178226361
Short name T367
Test name
Test status
Simulation time 214071404 ps
CPU time 2.88 seconds
Started Feb 26 03:17:47 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 208688 kb
Host smart-b110a42c-da40-4d86-aae9-acc599763ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178226361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3178226361
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4053581753
Short name T339
Test name
Test status
Simulation time 480557654 ps
CPU time 8.83 seconds
Started Feb 26 03:17:42 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 214316 kb
Host smart-513dc0be-7705-4f63-afd8-236f015fd5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053581753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4053581753
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3807229353
Short name T34
Test name
Test status
Simulation time 430694674 ps
CPU time 3.45 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:48 PM PST 24
Peak memory 219732 kb
Host smart-0bdab304-2393-476d-90f9-246ce6652cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807229353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3807229353
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3957013366
Short name T594
Test name
Test status
Simulation time 215797145 ps
CPU time 5.85 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 218340 kb
Host smart-69fece1a-0750-4998-8e55-512f186214b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957013366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3957013366
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2407037719
Short name T925
Test name
Test status
Simulation time 332888966 ps
CPU time 4.05 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 208664 kb
Host smart-01fd48e7-24be-4a65-82e6-b5fdf575f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407037719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2407037719
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2292903900
Short name T1069
Test name
Test status
Simulation time 504156075 ps
CPU time 6.82 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 208520 kb
Host smart-7c14a8f0-8437-4fec-b622-254af2d50c42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292903900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2292903900
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1257781074
Short name T1024
Test name
Test status
Simulation time 138026313 ps
CPU time 5.12 seconds
Started Feb 26 03:17:47 PM PST 24
Finished Feb 26 03:17:52 PM PST 24
Peak memory 207944 kb
Host smart-b15b6b66-a4d8-44f8-9a7c-69547a56cac4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257781074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1257781074
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2113785629
Short name T649
Test name
Test status
Simulation time 157795572 ps
CPU time 2.84 seconds
Started Feb 26 03:17:44 PM PST 24
Finished Feb 26 03:17:47 PM PST 24
Peak memory 208728 kb
Host smart-2e904e86-f6e1-4a24-8bca-7cc8edc75384
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113785629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2113785629
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.13877920
Short name T919
Test name
Test status
Simulation time 133862895 ps
CPU time 2.5 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:49 PM PST 24
Peak memory 209168 kb
Host smart-bd40ccf9-c0e3-40d6-ac19-ce188e440913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13877920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.13877920
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1533673806
Short name T733
Test name
Test status
Simulation time 909528816 ps
CPU time 2.96 seconds
Started Feb 26 03:17:47 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 206636 kb
Host smart-4fecb938-06c4-4c1e-9141-217ffcde8520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533673806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1533673806
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.759935330
Short name T261
Test name
Test status
Simulation time 1385575787 ps
CPU time 10.54 seconds
Started Feb 26 03:17:49 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 218728 kb
Host smart-702fe577-31da-4e1a-84d5-958793e41369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759935330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.759935330
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.596730374
Short name T884
Test name
Test status
Simulation time 197208321 ps
CPU time 4.34 seconds
Started Feb 26 03:17:49 PM PST 24
Finished Feb 26 03:17:54 PM PST 24
Peak memory 222644 kb
Host smart-df079d0b-52ac-44d3-85ed-e3ee774b52a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596730374 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.596730374
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.96251355
Short name T655
Test name
Test status
Simulation time 725678170 ps
CPU time 5.56 seconds
Started Feb 26 03:17:45 PM PST 24
Finished Feb 26 03:17:51 PM PST 24
Peak memory 208104 kb
Host smart-ecf0b053-fe0c-4b7d-8ef6-a55d5fbf2263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96251355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.96251355
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.862712778
Short name T807
Test name
Test status
Simulation time 47227537 ps
CPU time 1.74 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 210000 kb
Host smart-7a424255-1a37-485f-9895-8024f5dd760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862712778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.862712778
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1944650022
Short name T977
Test name
Test status
Simulation time 17831748 ps
CPU time 0.83 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:17:58 PM PST 24
Peak memory 205788 kb
Host smart-a4d8af8c-8272-40eb-9de4-ecb2cadf34ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944650022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1944650022
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1599881969
Short name T994
Test name
Test status
Simulation time 656574345 ps
CPU time 3.82 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 215560 kb
Host smart-3942bddd-34b9-4975-ae92-fcacb0ff7df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599881969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1599881969
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1316611346
Short name T728
Test name
Test status
Simulation time 3409419829 ps
CPU time 31.91 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:18:18 PM PST 24
Peak memory 214336 kb
Host smart-78dac60a-bf3d-4a09-9cc6-601ce3093848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316611346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1316611346
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2198102420
Short name T966
Test name
Test status
Simulation time 3733183180 ps
CPU time 10.04 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:18:06 PM PST 24
Peak memory 208252 kb
Host smart-0691ce65-9412-4640-818c-f1364b113ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198102420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2198102420
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.241214380
Short name T872
Test name
Test status
Simulation time 80988908 ps
CPU time 4.06 seconds
Started Feb 26 03:17:55 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 214164 kb
Host smart-6f936481-1cbd-45d6-a57a-7868bb212c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241214380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.241214380
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3767714411
Short name T918
Test name
Test status
Simulation time 78115355 ps
CPU time 2.82 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:18:00 PM PST 24
Peak memory 206080 kb
Host smart-42887d6c-8077-4c47-8734-e7bd630a7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767714411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3767714411
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2442704241
Short name T625
Test name
Test status
Simulation time 302572753 ps
CPU time 8.56 seconds
Started Feb 26 03:17:50 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 209576 kb
Host smart-2b6eeba2-57fc-47d0-a208-e11affb5df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442704241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2442704241
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3748167940
Short name T684
Test name
Test status
Simulation time 295850279 ps
CPU time 3.83 seconds
Started Feb 26 03:17:46 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 208560 kb
Host smart-d4550078-8d87-4307-a654-8d2698336f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748167940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3748167940
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1314208644
Short name T297
Test name
Test status
Simulation time 126082238 ps
CPU time 3.65 seconds
Started Feb 26 03:17:51 PM PST 24
Finished Feb 26 03:17:56 PM PST 24
Peak memory 208804 kb
Host smart-5c700ee2-8d32-4f78-9407-e7bf8ab11c3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314208644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1314208644
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.135125046
Short name T985
Test name
Test status
Simulation time 129842418 ps
CPU time 4.2 seconds
Started Feb 26 03:17:52 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 208160 kb
Host smart-8ce2929a-ff09-4a34-900f-296ca31ffad0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135125046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.135125046
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2260529612
Short name T564
Test name
Test status
Simulation time 634173019 ps
CPU time 5.95 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:55 PM PST 24
Peak memory 206876 kb
Host smart-02b5f719-257e-400f-8006-a45cf7cffaf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260529612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2260529612
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2954629405
Short name T931
Test name
Test status
Simulation time 51771062 ps
CPU time 2.47 seconds
Started Feb 26 03:17:51 PM PST 24
Finished Feb 26 03:17:54 PM PST 24
Peak memory 218288 kb
Host smart-26f3b307-fee4-4fe5-a4d0-6d1e1a29b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954629405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2954629405
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.709681561
Short name T869
Test name
Test status
Simulation time 56692247 ps
CPU time 2.89 seconds
Started Feb 26 03:17:48 PM PST 24
Finished Feb 26 03:17:51 PM PST 24
Peak memory 207856 kb
Host smart-945cf4f1-6afc-420d-8a0f-a1e7207a8255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709681561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.709681561
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1494658271
Short name T1049
Test name
Test status
Simulation time 849165789 ps
CPU time 29.79 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:18:26 PM PST 24
Peak memory 215052 kb
Host smart-13737562-e7ec-4219-8ecf-b3a164d1ea9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494658271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1494658271
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2303351263
Short name T216
Test name
Test status
Simulation time 501603913 ps
CPU time 13.15 seconds
Started Feb 26 03:17:58 PM PST 24
Finished Feb 26 03:18:11 PM PST 24
Peak memory 220648 kb
Host smart-afcf7512-1af9-4742-af20-dea6227e4dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303351263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2303351263
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1035197962
Short name T659
Test name
Test status
Simulation time 1084026635 ps
CPU time 12.49 seconds
Started Feb 26 03:17:52 PM PST 24
Finished Feb 26 03:18:04 PM PST 24
Peak memory 218432 kb
Host smart-71b2b407-ea8c-4e93-b770-04c12f9e8df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035197962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1035197962
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1206190060
Short name T612
Test name
Test status
Simulation time 97591812 ps
CPU time 2.78 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 209672 kb
Host smart-9edbbd98-0d91-46c8-909b-b69a71beb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206190060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1206190060
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2841791149
Short name T800
Test name
Test status
Simulation time 159658517 ps
CPU time 0.8 seconds
Started Feb 26 03:18:00 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 205888 kb
Host smart-f516e36d-e8ec-420b-802e-c463eccca90f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841791149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2841791149
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2895130639
Short name T967
Test name
Test status
Simulation time 105536397 ps
CPU time 2.73 seconds
Started Feb 26 03:17:54 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 209476 kb
Host smart-ebab9172-192f-49c6-9152-04b94ddefa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895130639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2895130639
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3199022647
Short name T46
Test name
Test status
Simulation time 109361836 ps
CPU time 1.92 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:17:58 PM PST 24
Peak memory 217848 kb
Host smart-3b128a97-cabe-4722-864e-f5263e0838f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199022647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3199022647
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1346310933
Short name T840
Test name
Test status
Simulation time 799539370 ps
CPU time 7.11 seconds
Started Feb 26 03:17:53 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 208984 kb
Host smart-5269de7c-24df-4d84-8c65-7b334da6d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346310933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1346310933
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3394096489
Short name T331
Test name
Test status
Simulation time 183426538 ps
CPU time 3.52 seconds
Started Feb 26 03:17:55 PM PST 24
Finished Feb 26 03:17:59 PM PST 24
Peak memory 209236 kb
Host smart-3d8d7e24-56b2-4403-accd-f5dc0434e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394096489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3394096489
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2398499289
Short name T745
Test name
Test status
Simulation time 91023496 ps
CPU time 3.2 seconds
Started Feb 26 03:17:53 PM PST 24
Finished Feb 26 03:17:56 PM PST 24
Peak memory 208212 kb
Host smart-17e4d072-9043-4b36-ad22-97686b0344e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398499289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2398499289
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1260511347
Short name T598
Test name
Test status
Simulation time 277830542 ps
CPU time 5.4 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:18:02 PM PST 24
Peak memory 214308 kb
Host smart-a4172ba8-8b4c-4fcf-a52b-af05fc07609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260511347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1260511347
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4251498377
Short name T1029
Test name
Test status
Simulation time 1020770092 ps
CPU time 4.05 seconds
Started Feb 26 03:17:53 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 208468 kb
Host smart-6116779f-bb36-4b81-8bcb-075b7f93f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251498377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4251498377
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.206513405
Short name T1061
Test name
Test status
Simulation time 1264142034 ps
CPU time 5.96 seconds
Started Feb 26 03:17:55 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 207904 kb
Host smart-31484519-e0ab-414d-a0ff-f7918d63a988
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206513405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.206513405
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3333947698
Short name T606
Test name
Test status
Simulation time 86852488 ps
CPU time 3.76 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:18:00 PM PST 24
Peak memory 208496 kb
Host smart-5595bf25-f8b4-4801-a513-5230dbd9e102
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333947698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3333947698
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2198243520
Short name T987
Test name
Test status
Simulation time 247382122 ps
CPU time 4.09 seconds
Started Feb 26 03:17:51 PM PST 24
Finished Feb 26 03:17:56 PM PST 24
Peak memory 208548 kb
Host smart-78c24520-91fe-4147-80aa-cc759d5ad815
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198243520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2198243520
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3919551039
Short name T352
Test name
Test status
Simulation time 3571063278 ps
CPU time 24.09 seconds
Started Feb 26 03:17:58 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 221720 kb
Host smart-5604ea2c-192c-4df3-8de2-f890986530e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919551039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3919551039
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.507378115
Short name T418
Test name
Test status
Simulation time 537252949 ps
CPU time 3.49 seconds
Started Feb 26 03:17:52 PM PST 24
Finished Feb 26 03:17:55 PM PST 24
Peak memory 208372 kb
Host smart-73f1569a-270c-4e7e-bc55-0778f63d5611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507378115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.507378115
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3245244448
Short name T300
Test name
Test status
Simulation time 321822016 ps
CPU time 13.23 seconds
Started Feb 26 03:18:00 PM PST 24
Finished Feb 26 03:18:14 PM PST 24
Peak memory 216808 kb
Host smart-0d72c8af-ad94-44ff-ba74-35a4ee240fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245244448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3245244448
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.603254236
Short name T1070
Test name
Test status
Simulation time 685657742 ps
CPU time 7.32 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:18:04 PM PST 24
Peak memory 218184 kb
Host smart-e58ad9f7-c289-4115-8681-0bf49b675c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603254236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.603254236
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2578920693
Short name T60
Test name
Test status
Simulation time 298216796 ps
CPU time 6.9 seconds
Started Feb 26 03:18:01 PM PST 24
Finished Feb 26 03:18:08 PM PST 24
Peak memory 210232 kb
Host smart-69e967f7-d3cf-4a10-87bf-e2dbedfcdc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578920693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2578920693
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.860606738
Short name T751
Test name
Test status
Simulation time 11539039 ps
CPU time 0.72 seconds
Started Feb 26 03:18:01 PM PST 24
Finished Feb 26 03:18:02 PM PST 24
Peak memory 205736 kb
Host smart-cac48ae3-5275-43d3-b580-0fefebbe3243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860606738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.860606738
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.581297513
Short name T411
Test name
Test status
Simulation time 263208167 ps
CPU time 4.1 seconds
Started Feb 26 03:18:03 PM PST 24
Finished Feb 26 03:18:07 PM PST 24
Peak memory 214992 kb
Host smart-6f14d3d2-8c9d-4e0d-b609-991cdf99684c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581297513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.581297513
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2702296720
Short name T679
Test name
Test status
Simulation time 26128582 ps
CPU time 1.77 seconds
Started Feb 26 03:18:01 PM PST 24
Finished Feb 26 03:18:03 PM PST 24
Peak memory 209216 kb
Host smart-f73ee965-1503-4c38-af19-e93f7b5e41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702296720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2702296720
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4029254118
Short name T642
Test name
Test status
Simulation time 1119983380 ps
CPU time 5.96 seconds
Started Feb 26 03:18:03 PM PST 24
Finished Feb 26 03:18:10 PM PST 24
Peak memory 214184 kb
Host smart-4a0283a1-f43c-4072-b773-0550d49945ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029254118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4029254118
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2195529263
Short name T259
Test name
Test status
Simulation time 1284181253 ps
CPU time 10.12 seconds
Started Feb 26 03:18:02 PM PST 24
Finished Feb 26 03:18:12 PM PST 24
Peak memory 214304 kb
Host smart-71672a8f-d2b5-4b5b-aa92-b4ed5220f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195529263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2195529263
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1794055111
Short name T128
Test name
Test status
Simulation time 159758582 ps
CPU time 5.6 seconds
Started Feb 26 03:17:58 PM PST 24
Finished Feb 26 03:18:04 PM PST 24
Peak memory 210136 kb
Host smart-0c1c67cf-4c30-4262-b795-49eff872c9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794055111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1794055111
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.418328515
Short name T182
Test name
Test status
Simulation time 123801980 ps
CPU time 4.71 seconds
Started Feb 26 03:17:58 PM PST 24
Finished Feb 26 03:18:03 PM PST 24
Peak memory 208416 kb
Host smart-4d58ce92-b43c-49b1-826d-6bd859f41736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418328515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.418328515
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1225840206
Short name T777
Test name
Test status
Simulation time 79371166 ps
CPU time 2.83 seconds
Started Feb 26 03:17:59 PM PST 24
Finished Feb 26 03:18:01 PM PST 24
Peak memory 208564 kb
Host smart-a4e02876-3acd-4b93-a884-95453585bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225840206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1225840206
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3418736172
Short name T1041
Test name
Test status
Simulation time 5170530499 ps
CPU time 57.22 seconds
Started Feb 26 03:18:00 PM PST 24
Finished Feb 26 03:18:58 PM PST 24
Peak memory 208980 kb
Host smart-d6125331-b435-481f-a8b5-82ab3f0389d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418736172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3418736172
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3859639920
Short name T270
Test name
Test status
Simulation time 52570379 ps
CPU time 1.9 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:17:58 PM PST 24
Peak memory 206836 kb
Host smart-4af4ada7-697f-41de-b364-73e192017a1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859639920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3859639920
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3257367770
Short name T907
Test name
Test status
Simulation time 1329665832 ps
CPU time 14.61 seconds
Started Feb 26 03:17:56 PM PST 24
Finished Feb 26 03:18:11 PM PST 24
Peak memory 208488 kb
Host smart-0d704358-c4d6-41b6-864b-bf05fae0f063
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257367770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3257367770
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.577145419
Short name T961
Test name
Test status
Simulation time 108200829 ps
CPU time 2.96 seconds
Started Feb 26 03:18:08 PM PST 24
Finished Feb 26 03:18:12 PM PST 24
Peak memory 208716 kb
Host smart-5bc02e27-32ce-45b2-9832-20ee0fe120fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577145419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.577145419
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2724774917
Short name T386
Test name
Test status
Simulation time 24687418 ps
CPU time 1.81 seconds
Started Feb 26 03:17:55 PM PST 24
Finished Feb 26 03:17:57 PM PST 24
Peak memory 207008 kb
Host smart-ccd8f542-a2c0-4ff2-98f3-6a04a18990ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724774917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2724774917
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2401574850
Short name T1039
Test name
Test status
Simulation time 96667247 ps
CPU time 2.87 seconds
Started Feb 26 03:18:03 PM PST 24
Finished Feb 26 03:18:06 PM PST 24
Peak memory 217952 kb
Host smart-f353adca-4aa8-414a-b951-d779d68a0d7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401574850 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2401574850
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4113655245
Short name T702
Test name
Test status
Simulation time 217974370 ps
CPU time 6.98 seconds
Started Feb 26 03:17:57 PM PST 24
Finished Feb 26 03:18:04 PM PST 24
Peak memory 208964 kb
Host smart-901c8640-30ba-4f00-8563-4cd4a1d862c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113655245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4113655245
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3157834546
Short name T920
Test name
Test status
Simulation time 289643049 ps
CPU time 2.42 seconds
Started Feb 26 03:18:06 PM PST 24
Finished Feb 26 03:18:09 PM PST 24
Peak memory 210328 kb
Host smart-331175c2-8f14-42a1-b73d-b59349853008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157834546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3157834546
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2087655850
Short name T801
Test name
Test status
Simulation time 100611651 ps
CPU time 0.77 seconds
Started Feb 26 03:18:18 PM PST 24
Finished Feb 26 03:18:19 PM PST 24
Peak memory 205836 kb
Host smart-9f01613a-40b6-4ecf-b630-97197b685825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087655850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2087655850
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3709383794
Short name T405
Test name
Test status
Simulation time 256624694 ps
CPU time 13.19 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:30 PM PST 24
Peak memory 214180 kb
Host smart-d4f7225e-27f5-4ac0-af1b-73ae59d1db1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709383794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3709383794
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3986911570
Short name T832
Test name
Test status
Simulation time 419731011 ps
CPU time 2.63 seconds
Started Feb 26 03:18:12 PM PST 24
Finished Feb 26 03:18:15 PM PST 24
Peak memory 214308 kb
Host smart-5dc2dd1c-3182-4d08-af22-b4b56a68f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986911570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3986911570
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2594511791
Short name T375
Test name
Test status
Simulation time 69050340 ps
CPU time 1.68 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:17 PM PST 24
Peak memory 218360 kb
Host smart-18914f37-ca72-4d23-a456-543661fbef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594511791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2594511791
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2869558776
Short name T780
Test name
Test status
Simulation time 250075292 ps
CPU time 7.72 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:28 PM PST 24
Peak memory 214140 kb
Host smart-487e728a-f1d0-4da2-ab07-710e16723ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869558776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2869558776
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1533719669
Short name T1001
Test name
Test status
Simulation time 495641684 ps
CPU time 3.67 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:19 PM PST 24
Peak memory 220096 kb
Host smart-49e63069-0f10-4696-a55e-1c35ecea64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533719669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1533719669
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3334874269
Short name T896
Test name
Test status
Simulation time 1169579902 ps
CPU time 10.43 seconds
Started Feb 26 03:18:21 PM PST 24
Finished Feb 26 03:18:31 PM PST 24
Peak memory 210016 kb
Host smart-404d45fa-67ee-490d-974e-28441f8679a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334874269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3334874269
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4158708199
Short name T737
Test name
Test status
Simulation time 165735889 ps
CPU time 5.34 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 207792 kb
Host smart-5808c889-3169-4a0a-90ba-7b85e01f1a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158708199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4158708199
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3222062335
Short name T956
Test name
Test status
Simulation time 388622563 ps
CPU time 5.8 seconds
Started Feb 26 03:18:21 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 208664 kb
Host smart-4a5d684e-1347-4cf9-b763-9a8b9bcd2778
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222062335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3222062335
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2453261599
Short name T1008
Test name
Test status
Simulation time 8817385972 ps
CPU time 41.61 seconds
Started Feb 26 03:18:13 PM PST 24
Finished Feb 26 03:18:55 PM PST 24
Peak memory 208084 kb
Host smart-11c6a367-6138-44db-95c3-d3bb1f6c9839
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453261599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2453261599
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.918581075
Short name T903
Test name
Test status
Simulation time 255960892 ps
CPU time 7.39 seconds
Started Feb 26 03:18:14 PM PST 24
Finished Feb 26 03:18:21 PM PST 24
Peak memory 208828 kb
Host smart-8be5a2da-6b07-47e2-ad9f-ac96bf10fa62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918581075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.918581075
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3890188049
Short name T553
Test name
Test status
Simulation time 67656309 ps
CPU time 2.8 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:21 PM PST 24
Peak memory 215356 kb
Host smart-20e0e7f2-7061-4f17-ba7c-c3b9ff03cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890188049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3890188049
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1054863959
Short name T563
Test name
Test status
Simulation time 1260810088 ps
CPU time 14.23 seconds
Started Feb 26 03:18:02 PM PST 24
Finished Feb 26 03:18:17 PM PST 24
Peak memory 208680 kb
Host smart-1d9017d4-6791-4852-9097-d5e40fb88d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054863959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1054863959
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2199806126
Short name T744
Test name
Test status
Simulation time 2253207960 ps
CPU time 55.55 seconds
Started Feb 26 03:18:15 PM PST 24
Finished Feb 26 03:19:11 PM PST 24
Peak memory 222612 kb
Host smart-b5d61336-7e46-4108-94f8-80fa44663178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199806126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2199806126
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3922874943
Short name T319
Test name
Test status
Simulation time 327336666 ps
CPU time 4.07 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:21 PM PST 24
Peak memory 218184 kb
Host smart-363d4cd4-04be-4b6f-b9d7-5441c00f50c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922874943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3922874943
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.293921452
Short name T1006
Test name
Test status
Simulation time 68653482 ps
CPU time 1.15 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:18 PM PST 24
Peak memory 209552 kb
Host smart-7f7f9750-6b83-474b-99a2-aae0ee58556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293921452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.293921452
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3045622284
Short name T757
Test name
Test status
Simulation time 12888264 ps
CPU time 0.89 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:19 PM PST 24
Peak memory 205876 kb
Host smart-9baa7e85-ed61-4793-a375-cd0d38c52ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045622284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3045622284
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2063898108
Short name T223
Test name
Test status
Simulation time 109034574 ps
CPU time 2.48 seconds
Started Feb 26 03:18:18 PM PST 24
Finished Feb 26 03:18:20 PM PST 24
Peak memory 214200 kb
Host smart-dc39eb09-4a7a-42e6-98ce-d2285e317961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063898108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2063898108
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.849335014
Short name T890
Test name
Test status
Simulation time 463659610 ps
CPU time 2.79 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 208964 kb
Host smart-3a9f8041-2e92-4d9c-b393-1a824aaa1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849335014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.849335014
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3344704460
Short name T287
Test name
Test status
Simulation time 28719183 ps
CPU time 2.18 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:19 PM PST 24
Peak memory 207580 kb
Host smart-51767d5b-406a-4af3-96c9-c74e1cb43c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344704460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3344704460
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3334291477
Short name T608
Test name
Test status
Simulation time 355465272 ps
CPU time 7.57 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:26 PM PST 24
Peak memory 208836 kb
Host smart-6b3ad900-21fd-4014-ba3f-e6ba346db94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334291477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3334291477
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4224121854
Short name T231
Test name
Test status
Simulation time 229836919 ps
CPU time 9.88 seconds
Started Feb 26 03:18:14 PM PST 24
Finished Feb 26 03:18:24 PM PST 24
Peak memory 211396 kb
Host smart-ebdcd6ec-528a-44db-95fc-cacc49197473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224121854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4224121854
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1917135672
Short name T211
Test name
Test status
Simulation time 539104159 ps
CPU time 5.12 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:24 PM PST 24
Peak memory 220368 kb
Host smart-2cd1ca5f-2636-41e3-826a-bf641493de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917135672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1917135672
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2857343950
Short name T364
Test name
Test status
Simulation time 3297235516 ps
CPU time 85.51 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:19:45 PM PST 24
Peak memory 218472 kb
Host smart-3d3ca885-3874-4882-8806-8d6640ae4240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857343950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2857343950
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2573939054
Short name T719
Test name
Test status
Simulation time 246656722 ps
CPU time 3.14 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:20 PM PST 24
Peak memory 206912 kb
Host smart-abbea5e2-d13b-4347-8ae7-0fb53f545536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573939054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2573939054
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3164324390
Short name T347
Test name
Test status
Simulation time 264743290 ps
CPU time 9.06 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:29 PM PST 24
Peak memory 208596 kb
Host smart-eb6cf9c7-0ca2-4edb-ad5c-15a9bbe8edf9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164324390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3164324390
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.641005699
Short name T239
Test name
Test status
Simulation time 433667356 ps
CPU time 3.82 seconds
Started Feb 26 03:18:16 PM PST 24
Finished Feb 26 03:18:20 PM PST 24
Peak memory 208572 kb
Host smart-68a5637b-1723-47f5-ae9a-63c3fe9c5763
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641005699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.641005699
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3464781044
Short name T735
Test name
Test status
Simulation time 1262745821 ps
CPU time 14.53 seconds
Started Feb 26 03:18:14 PM PST 24
Finished Feb 26 03:18:29 PM PST 24
Peak memory 208592 kb
Host smart-0f93ebe6-db75-4d48-bbf0-9e5326fcb42b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464781044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3464781044
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1064009003
Short name T990
Test name
Test status
Simulation time 240672115 ps
CPU time 3.69 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 214336 kb
Host smart-1bfd8897-ae86-4b1a-9820-55b6b0de3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064009003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1064009003
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2998177448
Short name T416
Test name
Test status
Simulation time 1234337453 ps
CPU time 27.06 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:46 PM PST 24
Peak memory 208540 kb
Host smart-6d5dd1e1-74fe-4c92-870e-f478af69ee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998177448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2998177448
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1791062989
Short name T878
Test name
Test status
Simulation time 3782950307 ps
CPU time 34.1 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:53 PM PST 24
Peak memory 207972 kb
Host smart-59273817-3be7-48d4-97d6-3ec77f68e5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791062989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1791062989
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1481865936
Short name T377
Test name
Test status
Simulation time 1043358060 ps
CPU time 7.39 seconds
Started Feb 26 03:18:14 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 222612 kb
Host smart-e2985e2e-6219-4892-b450-3249423382b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481865936 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1481865936
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1803109249
Short name T268
Test name
Test status
Simulation time 215138222 ps
CPU time 8.43 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:29 PM PST 24
Peak memory 208376 kb
Host smart-269d7584-a2f9-4a99-ac38-1c14b2e9569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803109249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1803109249
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3304528853
Short name T812
Test name
Test status
Simulation time 894290034 ps
CPU time 3.76 seconds
Started Feb 26 03:18:20 PM PST 24
Finished Feb 26 03:18:24 PM PST 24
Peak memory 210532 kb
Host smart-3e856015-fec6-4c13-a298-0319ebc91503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304528853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3304528853
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3495837589
Short name T1066
Test name
Test status
Simulation time 339704561 ps
CPU time 0.9 seconds
Started Feb 26 03:18:21 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 205808 kb
Host smart-38a4f232-a4f4-4926-83eb-182765b25a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495837589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3495837589
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1564020479
Short name T285
Test name
Test status
Simulation time 111288603 ps
CPU time 2.42 seconds
Started Feb 26 03:18:24 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 214212 kb
Host smart-10a415b9-1cd0-437d-9c24-b9690d6848bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564020479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1564020479
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2608383070
Short name T831
Test name
Test status
Simulation time 49460553 ps
CPU time 2.91 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 208584 kb
Host smart-919dae1d-632e-41b8-99a2-b794a8957ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608383070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2608383070
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.356644265
Short name T1034
Test name
Test status
Simulation time 61372331 ps
CPU time 2.97 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:29 PM PST 24
Peak memory 218452 kb
Host smart-bd475367-a95e-4509-8fbe-d37153e7dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356644265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.356644265
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.28097585
Short name T933
Test name
Test status
Simulation time 411355859 ps
CPU time 5.09 seconds
Started Feb 26 03:18:17 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 214296 kb
Host smart-c8d42f34-1ce9-4114-aef1-5183ec539c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28097585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.28097585
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4269522996
Short name T974
Test name
Test status
Simulation time 261091808 ps
CPU time 3.93 seconds
Started Feb 26 03:18:22 PM PST 24
Finished Feb 26 03:18:26 PM PST 24
Peak memory 209768 kb
Host smart-8326df48-8d7d-4e4a-b7f4-3451e81d4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269522996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4269522996
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1539680170
Short name T643
Test name
Test status
Simulation time 287359844 ps
CPU time 3.81 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:30 PM PST 24
Peak memory 208376 kb
Host smart-8bee8a42-22b1-4322-af47-34c54da44b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539680170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1539680170
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2050545439
Short name T846
Test name
Test status
Simulation time 129444776 ps
CPU time 2.34 seconds
Started Feb 26 03:18:28 PM PST 24
Finished Feb 26 03:18:31 PM PST 24
Peak memory 207276 kb
Host smart-e8210b45-2608-42cc-8080-9d01b88b82c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050545439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2050545439
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1037473905
Short name T35
Test name
Test status
Simulation time 78172701 ps
CPU time 3.64 seconds
Started Feb 26 03:18:18 PM PST 24
Finished Feb 26 03:18:22 PM PST 24
Peak memory 208124 kb
Host smart-43061584-c1e8-4f81-92fe-4383065432fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037473905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1037473905
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3568368345
Short name T284
Test name
Test status
Simulation time 1503817566 ps
CPU time 15.49 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:42 PM PST 24
Peak memory 208792 kb
Host smart-98cfe53b-32b1-463e-8324-f8570a7adfa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568368345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3568368345
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.94020183
Short name T366
Test name
Test status
Simulation time 130813224 ps
CPU time 4.19 seconds
Started Feb 26 03:18:19 PM PST 24
Finished Feb 26 03:18:23 PM PST 24
Peak memory 207832 kb
Host smart-59cffcb6-8449-4053-b012-a17f18cf36a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94020183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.94020183
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.342695647
Short name T355
Test name
Test status
Simulation time 9594158078 ps
CPU time 41.7 seconds
Started Feb 26 03:18:27 PM PST 24
Finished Feb 26 03:19:09 PM PST 24
Peak memory 218240 kb
Host smart-b6307f4c-e43e-4bfe-9cd9-caff3b851861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342695647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.342695647
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.910396422
Short name T718
Test name
Test status
Simulation time 1999983108 ps
CPU time 50.91 seconds
Started Feb 26 03:18:15 PM PST 24
Finished Feb 26 03:19:07 PM PST 24
Peak memory 208784 kb
Host smart-ea0919cf-b762-4340-968b-80dd247a4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910396422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.910396422
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.445993778
Short name T69
Test name
Test status
Simulation time 1307855656 ps
CPU time 29.02 seconds
Started Feb 26 03:18:21 PM PST 24
Finished Feb 26 03:18:50 PM PST 24
Peak memory 216364 kb
Host smart-0257dd5f-98c1-4907-bac7-1f778d4eb938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445993778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.445993778
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3829467994
Short name T88
Test name
Test status
Simulation time 473098645 ps
CPU time 4.41 seconds
Started Feb 26 03:18:22 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 222548 kb
Host smart-e61cc517-16b2-43b2-8ce2-04a536a7727c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829467994 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3829467994
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2195328413
Short name T993
Test name
Test status
Simulation time 6302768362 ps
CPU time 55.34 seconds
Started Feb 26 03:18:21 PM PST 24
Finished Feb 26 03:19:16 PM PST 24
Peak memory 209288 kb
Host smart-517a9580-38ee-48fd-aee6-bbf204ec34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195328413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2195328413
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4024783604
Short name T562
Test name
Test status
Simulation time 87507046 ps
CPU time 2.28 seconds
Started Feb 26 03:18:24 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 209616 kb
Host smart-b241eeff-cf4b-4e5a-bf91-ede97175317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024783604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4024783604
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3978025281
Short name T1028
Test name
Test status
Simulation time 13776269 ps
CPU time 0.89 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 206048 kb
Host smart-f0fdb408-35b9-4797-9459-538d59634317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978025281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3978025281
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3800913906
Short name T306
Test name
Test status
Simulation time 1197286689 ps
CPU time 14.39 seconds
Started Feb 26 03:18:30 PM PST 24
Finished Feb 26 03:18:46 PM PST 24
Peak memory 215328 kb
Host smart-5d1c90cc-ae36-40ba-9179-1e9b20976b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800913906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3800913906
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2772570336
Short name T1022
Test name
Test status
Simulation time 44504817 ps
CPU time 2.15 seconds
Started Feb 26 03:18:26 PM PST 24
Finished Feb 26 03:18:28 PM PST 24
Peak memory 218824 kb
Host smart-c74e1d21-aa59-4cc2-a4fd-f8208a537d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772570336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2772570336
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.514312317
Short name T941
Test name
Test status
Simulation time 37505744 ps
CPU time 1.67 seconds
Started Feb 26 03:18:25 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 208064 kb
Host smart-b3223056-878d-4e0a-867b-008263d1320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514312317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.514312317
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2058917351
Short name T336
Test name
Test status
Simulation time 567685877 ps
CPU time 5.37 seconds
Started Feb 26 03:18:25 PM PST 24
Finished Feb 26 03:18:31 PM PST 24
Peak memory 221640 kb
Host smart-6455bc1e-ac1d-4cc9-aaa1-443a2862667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058917351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2058917351
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.997544848
Short name T836
Test name
Test status
Simulation time 73842097 ps
CPU time 2.17 seconds
Started Feb 26 03:18:31 PM PST 24
Finished Feb 26 03:18:34 PM PST 24
Peak memory 214328 kb
Host smart-5fad579a-f31c-45ce-b509-7a773ed7ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997544848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.997544848
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3340110112
Short name T1037
Test name
Test status
Simulation time 2021816788 ps
CPU time 66.8 seconds
Started Feb 26 03:18:25 PM PST 24
Finished Feb 26 03:19:32 PM PST 24
Peak memory 209860 kb
Host smart-8a551c10-a22d-4c77-b45e-9b934ad229d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340110112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3340110112
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1958027919
Short name T964
Test name
Test status
Simulation time 54101038 ps
CPU time 2.96 seconds
Started Feb 26 03:18:32 PM PST 24
Finished Feb 26 03:18:35 PM PST 24
Peak memory 208372 kb
Host smart-4744e562-17a1-4f0d-b778-99662e40f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958027919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1958027919
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4034954809
Short name T912
Test name
Test status
Simulation time 418428119 ps
CPU time 6.41 seconds
Started Feb 26 03:18:28 PM PST 24
Finished Feb 26 03:18:34 PM PST 24
Peak memory 208412 kb
Host smart-efc88fb6-f141-4251-aac2-a6c443923024
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034954809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4034954809
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.197992830
Short name T593
Test name
Test status
Simulation time 64153358 ps
CPU time 2.9 seconds
Started Feb 26 03:18:24 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 206948 kb
Host smart-290cd7e7-2360-4f30-a287-b0289a401129
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197992830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.197992830
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3795666668
Short name T989
Test name
Test status
Simulation time 125742706 ps
CPU time 2.62 seconds
Started Feb 26 03:18:25 PM PST 24
Finished Feb 26 03:18:28 PM PST 24
Peak memory 206724 kb
Host smart-e3ad98fd-d922-4575-a56e-13c5bdf4c6cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795666668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3795666668
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.648325824
Short name T732
Test name
Test status
Simulation time 188350296 ps
CPU time 2.44 seconds
Started Feb 26 03:18:31 PM PST 24
Finished Feb 26 03:18:35 PM PST 24
Peak memory 208108 kb
Host smart-82be39af-568d-4adf-bd50-424a95014b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648325824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.648325824
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1653331833
Short name T761
Test name
Test status
Simulation time 157357215 ps
CPU time 2.74 seconds
Started Feb 26 03:18:24 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 208404 kb
Host smart-004a12c2-3b9e-4fb1-a94d-cb28585af53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653331833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1653331833
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2897293707
Short name T1063
Test name
Test status
Simulation time 490296475 ps
CPU time 7.41 seconds
Started Feb 26 03:18:31 PM PST 24
Finished Feb 26 03:18:39 PM PST 24
Peak memory 216392 kb
Host smart-d18c19cb-4018-4ef2-83a5-622a49167a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897293707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2897293707
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3400162266
Short name T288
Test name
Test status
Simulation time 569169555 ps
CPU time 11.69 seconds
Started Feb 26 03:18:31 PM PST 24
Finished Feb 26 03:18:44 PM PST 24
Peak memory 222564 kb
Host smart-9306f110-a7bf-4243-b577-4f3596afbf4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400162266 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3400162266
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3147410482
Short name T804
Test name
Test status
Simulation time 184279312 ps
CPU time 4.08 seconds
Started Feb 26 03:18:22 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 208212 kb
Host smart-9e3918b7-a121-482e-8795-424c964398c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147410482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3147410482
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3577926457
Short name T1050
Test name
Test status
Simulation time 44063502 ps
CPU time 2.35 seconds
Started Feb 26 03:18:25 PM PST 24
Finished Feb 26 03:18:27 PM PST 24
Peak memory 210380 kb
Host smart-d4e84fcc-63e4-45ea-9705-d747ef7d55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577926457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3577926457
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1496849128
Short name T344
Test name
Test status
Simulation time 94838124 ps
CPU time 4.38 seconds
Started Feb 26 03:14:38 PM PST 24
Finished Feb 26 03:14:43 PM PST 24
Peak memory 214324 kb
Host smart-871bf404-cc27-4081-87d8-47b281e287ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496849128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1496849128
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1576749813
Short name T20
Test name
Test status
Simulation time 227328040 ps
CPU time 6.82 seconds
Started Feb 26 03:14:40 PM PST 24
Finished Feb 26 03:14:47 PM PST 24
Peak memory 218944 kb
Host smart-3b660322-a460-472d-80ec-48b6a8c1bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576749813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1576749813
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4252717783
Short name T721
Test name
Test status
Simulation time 796580593 ps
CPU time 4.98 seconds
Started Feb 26 03:14:37 PM PST 24
Finished Feb 26 03:14:42 PM PST 24
Peak memory 214272 kb
Host smart-c531e908-bb5b-4e6b-b38b-5546bbbaec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252717783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4252717783
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2783086578
Short name T279
Test name
Test status
Simulation time 866614105 ps
CPU time 5.23 seconds
Started Feb 26 03:14:41 PM PST 24
Finished Feb 26 03:14:46 PM PST 24
Peak memory 214316 kb
Host smart-96c216d0-e72c-4541-ae89-73b45bd15226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783086578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2783086578
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3297552091
Short name T179
Test name
Test status
Simulation time 54449606 ps
CPU time 3.83 seconds
Started Feb 26 03:14:38 PM PST 24
Finished Feb 26 03:14:42 PM PST 24
Peak memory 222460 kb
Host smart-b2a32379-f964-4a67-bfce-1f9d9146e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297552091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3297552091
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1002205539
Short name T334
Test name
Test status
Simulation time 98356329 ps
CPU time 4.66 seconds
Started Feb 26 03:14:35 PM PST 24
Finished Feb 26 03:14:40 PM PST 24
Peak memory 214336 kb
Host smart-5e76283e-70e0-46aa-968c-cf8a24b73f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002205539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1002205539
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3801794956
Short name T590
Test name
Test status
Simulation time 343389845 ps
CPU time 6.88 seconds
Started Feb 26 03:14:28 PM PST 24
Finished Feb 26 03:14:35 PM PST 24
Peak memory 214260 kb
Host smart-862ccb68-113f-45f8-8579-fa72fde3c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801794956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3801794956
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3029460653
Short name T997
Test name
Test status
Simulation time 252922915 ps
CPU time 3.97 seconds
Started Feb 26 03:14:29 PM PST 24
Finished Feb 26 03:14:33 PM PST 24
Peak memory 206864 kb
Host smart-db485842-8c9f-4e78-8f76-6afcf86c677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029460653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3029460653
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3121908307
Short name T253
Test name
Test status
Simulation time 2932057616 ps
CPU time 32.23 seconds
Started Feb 26 03:14:30 PM PST 24
Finished Feb 26 03:15:02 PM PST 24
Peak memory 208488 kb
Host smart-cf96235a-7a63-473c-8e6d-c5746215aaf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121908307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3121908307
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3031530460
Short name T379
Test name
Test status
Simulation time 806533060 ps
CPU time 8.48 seconds
Started Feb 26 03:14:26 PM PST 24
Finished Feb 26 03:14:35 PM PST 24
Peak memory 208256 kb
Host smart-add4b176-45b7-47b6-b344-7696205eb814
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031530460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3031530460
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.739606091
Short name T579
Test name
Test status
Simulation time 575180265 ps
CPU time 3.99 seconds
Started Feb 26 03:14:28 PM PST 24
Finished Feb 26 03:14:32 PM PST 24
Peak memory 207420 kb
Host smart-35a9def3-d357-47e8-9af3-5cd113ce4350
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739606091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.739606091
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3948653154
Short name T802
Test name
Test status
Simulation time 82895581 ps
CPU time 3.15 seconds
Started Feb 26 03:14:38 PM PST 24
Finished Feb 26 03:14:41 PM PST 24
Peak memory 215896 kb
Host smart-a78aa4b9-e7fa-465c-906e-6d14ee67ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948653154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3948653154
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1853060232
Short name T547
Test name
Test status
Simulation time 22273188 ps
CPU time 1.85 seconds
Started Feb 26 03:14:30 PM PST 24
Finished Feb 26 03:14:32 PM PST 24
Peak memory 207148 kb
Host smart-9e569dd0-446d-4d67-880b-a98c76b850e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853060232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1853060232
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2834269117
Short name T962
Test name
Test status
Simulation time 17083402894 ps
CPU time 192.35 seconds
Started Feb 26 03:14:37 PM PST 24
Finished Feb 26 03:17:50 PM PST 24
Peak memory 217052 kb
Host smart-504fb552-2741-44ad-8d73-b7cc8fbb21cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834269117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2834269117
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2407424101
Short name T980
Test name
Test status
Simulation time 907702641 ps
CPU time 13.82 seconds
Started Feb 26 03:14:40 PM PST 24
Finished Feb 26 03:14:54 PM PST 24
Peak memory 222500 kb
Host smart-082c6732-51df-4de6-b4cc-40ab1ef01d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407424101 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2407424101
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3858338681
Short name T565
Test name
Test status
Simulation time 54911278 ps
CPU time 3.28 seconds
Started Feb 26 03:14:33 PM PST 24
Finished Feb 26 03:14:36 PM PST 24
Peak memory 209432 kb
Host smart-1d33b9b8-6630-4bee-987f-6f917dc75f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858338681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3858338681
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2495330553
Short name T37
Test name
Test status
Simulation time 607384697 ps
CPU time 2.15 seconds
Started Feb 26 03:14:42 PM PST 24
Finished Feb 26 03:14:44 PM PST 24
Peak memory 210048 kb
Host smart-a62b713c-a48a-44c7-924a-68a9ee918d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495330553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2495330553
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.204398323
Short name T730
Test name
Test status
Simulation time 11904369 ps
CPU time 0.73 seconds
Started Feb 26 03:14:44 PM PST 24
Finished Feb 26 03:14:46 PM PST 24
Peak memory 205836 kb
Host smart-6a4768b2-6515-4a15-9c20-e08f3083b7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204398323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.204398323
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2260485296
Short name T407
Test name
Test status
Simulation time 1821422625 ps
CPU time 47.89 seconds
Started Feb 26 03:14:39 PM PST 24
Finished Feb 26 03:15:27 PM PST 24
Peak memory 215004 kb
Host smart-3848ef2d-b4a2-4453-8fde-543bd144ae8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260485296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2260485296
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2301418923
Short name T71
Test name
Test status
Simulation time 200029578 ps
CPU time 2.01 seconds
Started Feb 26 03:14:36 PM PST 24
Finished Feb 26 03:14:38 PM PST 24
Peak memory 209416 kb
Host smart-fd7756e6-7ce7-4ae2-b553-3caafddefa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301418923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2301418923
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1337124526
Short name T1057
Test name
Test status
Simulation time 20005196099 ps
CPU time 43.36 seconds
Started Feb 26 03:14:40 PM PST 24
Finished Feb 26 03:15:23 PM PST 24
Peak memory 214372 kb
Host smart-d580023a-2800-4773-9a68-1c035b0fbfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337124526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1337124526
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3283031214
Short name T188
Test name
Test status
Simulation time 118199192 ps
CPU time 5.23 seconds
Started Feb 26 03:14:44 PM PST 24
Finished Feb 26 03:14:50 PM PST 24
Peak memory 222484 kb
Host smart-4aa77b3e-b9ee-48be-8bd5-b2e00e77e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283031214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3283031214
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.262583224
Short name T1013
Test name
Test status
Simulation time 74213496 ps
CPU time 3.44 seconds
Started Feb 26 03:14:46 PM PST 24
Finished Feb 26 03:14:50 PM PST 24
Peak memory 206408 kb
Host smart-7ce89c88-c5fd-45b8-bd72-5254b5e05b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262583224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.262583224
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3678744735
Short name T321
Test name
Test status
Simulation time 670911832 ps
CPU time 10 seconds
Started Feb 26 03:14:36 PM PST 24
Finished Feb 26 03:14:46 PM PST 24
Peak memory 207176 kb
Host smart-46d8ddd7-4547-4766-829f-f9d023b18f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678744735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3678744735
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1879544789
Short name T286
Test name
Test status
Simulation time 1199482745 ps
CPU time 10.9 seconds
Started Feb 26 03:14:38 PM PST 24
Finished Feb 26 03:14:49 PM PST 24
Peak memory 208240 kb
Host smart-feb7d56c-5d4b-40b9-8077-826e1dd9dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879544789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1879544789
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.349115263
Short name T591
Test name
Test status
Simulation time 454685735 ps
CPU time 6.05 seconds
Started Feb 26 03:14:40 PM PST 24
Finished Feb 26 03:14:46 PM PST 24
Peak memory 206984 kb
Host smart-322f17de-40a6-4a52-8fd7-a59ebb686d97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349115263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.349115263
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.451980961
Short name T963
Test name
Test status
Simulation time 157871601 ps
CPU time 6.39 seconds
Started Feb 26 03:14:39 PM PST 24
Finished Feb 26 03:14:45 PM PST 24
Peak memory 208784 kb
Host smart-b21ec7b5-9e6d-46c6-b19e-3b10ce791390
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451980961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.451980961
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4225514102
Short name T654
Test name
Test status
Simulation time 1101581152 ps
CPU time 8.35 seconds
Started Feb 26 03:14:36 PM PST 24
Finished Feb 26 03:14:44 PM PST 24
Peak memory 207956 kb
Host smart-5befd468-5a38-42ce-9795-e683d896df3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225514102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4225514102
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1785526541
Short name T833
Test name
Test status
Simulation time 22141970 ps
CPU time 1.84 seconds
Started Feb 26 03:14:41 PM PST 24
Finished Feb 26 03:14:43 PM PST 24
Peak memory 215608 kb
Host smart-7e3d8ef3-a938-4b0e-a159-a2f19470a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785526541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1785526541
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3918656187
Short name T660
Test name
Test status
Simulation time 94718687 ps
CPU time 1.73 seconds
Started Feb 26 03:14:39 PM PST 24
Finished Feb 26 03:14:41 PM PST 24
Peak memory 206764 kb
Host smart-ac6a242f-1279-46b9-accc-a63235ccded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918656187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3918656187
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2953236113
Short name T723
Test name
Test status
Simulation time 1744877219 ps
CPU time 18.47 seconds
Started Feb 26 03:14:41 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 215348 kb
Host smart-1cf75bf9-f010-4928-9d70-dd0a3b490244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953236113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2953236113
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3287474177
Short name T382
Test name
Test status
Simulation time 1092053519 ps
CPU time 8.05 seconds
Started Feb 26 03:14:46 PM PST 24
Finished Feb 26 03:14:55 PM PST 24
Peak memory 222704 kb
Host smart-bdbdf7d5-6610-48a8-bc9b-67c65180cff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287474177 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3287474177
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2997492650
Short name T304
Test name
Test status
Simulation time 1240545070 ps
CPU time 17.59 seconds
Started Feb 26 03:14:41 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 214364 kb
Host smart-6e0148b6-d949-44a7-b89d-cc0fb3804de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997492650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2997492650
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2011756566
Short name T51
Test name
Test status
Simulation time 235552714 ps
CPU time 2.14 seconds
Started Feb 26 03:14:41 PM PST 24
Finished Feb 26 03:14:43 PM PST 24
Peak memory 209652 kb
Host smart-b5fb5501-7e8e-4bca-ba13-001c60643842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011756566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2011756566
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2661974792
Short name T626
Test name
Test status
Simulation time 25933555 ps
CPU time 1.09 seconds
Started Feb 26 03:14:51 PM PST 24
Finished Feb 26 03:14:53 PM PST 24
Peak memory 205988 kb
Host smart-7ab2be72-77e5-4ee6-8c09-aa6ffd2317d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661974792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2661974792
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.488413052
Short name T354
Test name
Test status
Simulation time 2544227278 ps
CPU time 24.94 seconds
Started Feb 26 03:14:48 PM PST 24
Finished Feb 26 03:15:13 PM PST 24
Peak memory 209764 kb
Host smart-c24f52b2-97b8-449e-88cb-c5dc0f91d75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488413052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.488413052
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.311808373
Short name T369
Test name
Test status
Simulation time 145349506 ps
CPU time 4.84 seconds
Started Feb 26 03:14:48 PM PST 24
Finished Feb 26 03:14:55 PM PST 24
Peak memory 208228 kb
Host smart-975c38ff-9cb7-47cf-8302-f1597d227364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311808373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.311808373
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2754997460
Short name T819
Test name
Test status
Simulation time 184438377 ps
CPU time 4.61 seconds
Started Feb 26 03:14:53 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 210228 kb
Host smart-2eed2ec1-ff87-468b-b3c8-16c3f5118b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754997460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2754997460
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3086887712
Short name T307
Test name
Test status
Simulation time 462270258 ps
CPU time 4.41 seconds
Started Feb 26 03:14:47 PM PST 24
Finished Feb 26 03:14:53 PM PST 24
Peak memory 214288 kb
Host smart-204ac9f1-7d8c-4bfb-b46a-eacad816f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086887712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3086887712
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1025096952
Short name T799
Test name
Test status
Simulation time 191405526 ps
CPU time 5.46 seconds
Started Feb 26 03:14:53 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 208476 kb
Host smart-396ac7f8-e115-43a4-a54c-459b54158529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025096952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1025096952
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1334941988
Short name T575
Test name
Test status
Simulation time 181769564 ps
CPU time 2.91 seconds
Started Feb 26 03:14:47 PM PST 24
Finished Feb 26 03:14:51 PM PST 24
Peak memory 206900 kb
Host smart-2cf8519a-4081-4255-900e-6b3ed80a86be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334941988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1334941988
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.810796452
Short name T855
Test name
Test status
Simulation time 130997046 ps
CPU time 5.53 seconds
Started Feb 26 03:14:43 PM PST 24
Finished Feb 26 03:14:50 PM PST 24
Peak memory 208520 kb
Host smart-05fe0b4c-12d4-4a36-89ad-c89848cfb21b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810796452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.810796452
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2170309911
Short name T1042
Test name
Test status
Simulation time 131204270 ps
CPU time 4.36 seconds
Started Feb 26 03:14:48 PM PST 24
Finished Feb 26 03:14:53 PM PST 24
Peak memory 209012 kb
Host smart-5ade87bf-4759-4802-ae84-5360ea581d98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170309911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2170309911
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2946863609
Short name T226
Test name
Test status
Simulation time 69432084 ps
CPU time 3.17 seconds
Started Feb 26 03:14:49 PM PST 24
Finished Feb 26 03:14:55 PM PST 24
Peak memory 208148 kb
Host smart-13d024a2-abd1-4576-bf42-cde2678d2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946863609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2946863609
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2252426036
Short name T790
Test name
Test status
Simulation time 59597050 ps
CPU time 2.82 seconds
Started Feb 26 03:14:48 PM PST 24
Finished Feb 26 03:14:51 PM PST 24
Peak memory 208264 kb
Host smart-46ba08c0-6986-4b2c-b982-66ea6a451087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252426036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2252426036
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2623856674
Short name T917
Test name
Test status
Simulation time 666632247 ps
CPU time 7.87 seconds
Started Feb 26 03:14:51 PM PST 24
Finished Feb 26 03:15:00 PM PST 24
Peak memory 222552 kb
Host smart-7e34fa06-7221-410d-a571-d9ef8a215747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623856674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2623856674
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2623650617
Short name T857
Test name
Test status
Simulation time 275818682 ps
CPU time 9.49 seconds
Started Feb 26 03:14:47 PM PST 24
Finished Feb 26 03:14:58 PM PST 24
Peak memory 208888 kb
Host smart-365a03a7-09b4-4063-8056-5f3a9852737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623650617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2623650617
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3067537260
Short name T146
Test name
Test status
Simulation time 302162928 ps
CPU time 2.86 seconds
Started Feb 26 03:14:50 PM PST 24
Finished Feb 26 03:14:55 PM PST 24
Peak memory 210552 kb
Host smart-27f94e06-79ce-4d9a-97ad-7b53b6e185e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067537260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3067537260
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4085966901
Short name T603
Test name
Test status
Simulation time 21075009 ps
CPU time 0.83 seconds
Started Feb 26 03:14:57 PM PST 24
Finished Feb 26 03:14:57 PM PST 24
Peak memory 205812 kb
Host smart-5a0ebac7-0aba-4b74-9ed8-6c3380256423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085966901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4085966901
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3894124475
Short name T91
Test name
Test status
Simulation time 57189834 ps
CPU time 4.35 seconds
Started Feb 26 03:14:57 PM PST 24
Finished Feb 26 03:15:01 PM PST 24
Peak memory 214340 kb
Host smart-299a1ab1-8ac3-4053-99b0-734806ab1d0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894124475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3894124475
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3371916172
Short name T41
Test name
Test status
Simulation time 332085935 ps
CPU time 3.78 seconds
Started Feb 26 03:14:54 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 218528 kb
Host smart-f5473677-8513-4c3b-bd78-6f6d7c310272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371916172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3371916172
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.803358733
Short name T58
Test name
Test status
Simulation time 161228812 ps
CPU time 2.31 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:10 PM PST 24
Peak memory 207528 kb
Host smart-9b2367d5-1f2d-42bd-b1ae-35a03c504372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803358733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.803358733
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1490111092
Short name T175
Test name
Test status
Simulation time 138676590 ps
CPU time 5.78 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:13 PM PST 24
Peak memory 220408 kb
Host smart-5ec324fb-2b34-453a-8a90-1e9eb0f5a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490111092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1490111092
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4266236405
Short name T914
Test name
Test status
Simulation time 1556872956 ps
CPU time 10.04 seconds
Started Feb 26 03:14:58 PM PST 24
Finished Feb 26 03:15:08 PM PST 24
Peak memory 222344 kb
Host smart-8f013e44-31b1-479e-8394-4aa35e752bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266236405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4266236405
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3319677038
Short name T397
Test name
Test status
Simulation time 176007252 ps
CPU time 2.3 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:10 PM PST 24
Peak memory 206468 kb
Host smart-0e8ceb76-947a-4e78-aa92-7b95a1c2711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319677038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3319677038
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1054603241
Short name T172
Test name
Test status
Simulation time 455986076 ps
CPU time 5.65 seconds
Started Feb 26 03:14:54 PM PST 24
Finished Feb 26 03:15:01 PM PST 24
Peak memory 218320 kb
Host smart-efa7da54-0eba-4b10-a9f2-a7ac05002271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054603241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1054603241
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1850494604
Short name T263
Test name
Test status
Simulation time 3947335520 ps
CPU time 73.43 seconds
Started Feb 26 03:14:49 PM PST 24
Finished Feb 26 03:16:03 PM PST 24
Peak memory 208872 kb
Host smart-5d77c709-9b40-46cd-9bc0-6140f6002ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850494604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1850494604
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.98008846
Short name T1040
Test name
Test status
Simulation time 89067583 ps
CPU time 3.52 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:11 PM PST 24
Peak memory 206908 kb
Host smart-26b51e94-d310-459b-ae94-b51ef170033c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98008846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.98008846
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1373659328
Short name T710
Test name
Test status
Simulation time 3854677914 ps
CPU time 30 seconds
Started Feb 26 03:14:58 PM PST 24
Finished Feb 26 03:15:28 PM PST 24
Peak memory 208124 kb
Host smart-f8f509c0-5768-406a-87fc-c30f6481d172
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373659328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1373659328
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3561058004
Short name T566
Test name
Test status
Simulation time 455968636 ps
CPU time 5.43 seconds
Started Feb 26 03:14:53 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 208304 kb
Host smart-35a84407-0f30-42f9-93dc-faa75c59bdac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561058004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3561058004
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1822137522
Short name T834
Test name
Test status
Simulation time 62836535 ps
CPU time 2.74 seconds
Started Feb 26 03:14:56 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 215212 kb
Host smart-499eb6cc-3133-47d1-9195-b83dff30e413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822137522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1822137522
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3105068667
Short name T419
Test name
Test status
Simulation time 1706430332 ps
CPU time 6.96 seconds
Started Feb 26 03:14:54 PM PST 24
Finished Feb 26 03:15:02 PM PST 24
Peak memory 206720 kb
Host smart-049add29-30f3-467f-b9a6-36739babb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105068667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3105068667
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1484604945
Short name T209
Test name
Test status
Simulation time 477925235 ps
CPU time 18.5 seconds
Started Feb 26 03:14:54 PM PST 24
Finished Feb 26 03:15:13 PM PST 24
Peak memory 220580 kb
Host smart-0dea8eb4-97b0-4afc-a264-3880bc571fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484604945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1484604945
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3477924175
Short name T796
Test name
Test status
Simulation time 316420059 ps
CPU time 4.46 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:15:03 PM PST 24
Peak memory 222640 kb
Host smart-980a19e2-07c5-49dc-b6d9-c53a5439adcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477924175 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3477924175
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3030981394
Short name T269
Test name
Test status
Simulation time 129797162 ps
CPU time 5.94 seconds
Started Feb 26 03:14:56 PM PST 24
Finished Feb 26 03:15:02 PM PST 24
Peak memory 218084 kb
Host smart-d83e7cc6-19dc-4d23-937f-f49da5ce3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030981394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3030981394
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1250179067
Short name T954
Test name
Test status
Simulation time 1197900379 ps
CPU time 6.02 seconds
Started Feb 26 03:14:55 PM PST 24
Finished Feb 26 03:15:02 PM PST 24
Peak memory 210348 kb
Host smart-edc2cd28-dfa0-4e5a-b7ea-a1c0342cc9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250179067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1250179067
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1260653353
Short name T747
Test name
Test status
Simulation time 65275819 ps
CPU time 0.99 seconds
Started Feb 26 03:15:10 PM PST 24
Finished Feb 26 03:15:11 PM PST 24
Peak memory 206088 kb
Host smart-579fd795-df5b-440c-83f4-3f265945fb06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260653353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1260653353
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.352241475
Short name T281
Test name
Test status
Simulation time 45131657 ps
CPU time 3.38 seconds
Started Feb 26 03:15:00 PM PST 24
Finished Feb 26 03:15:04 PM PST 24
Peak memory 214260 kb
Host smart-4640027d-dd5b-4aca-8ea4-61e7c4bd12cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352241475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.352241475
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.10869277
Short name T64
Test name
Test status
Simulation time 62952347 ps
CPU time 3.34 seconds
Started Feb 26 03:14:57 PM PST 24
Finished Feb 26 03:15:01 PM PST 24
Peak memory 217496 kb
Host smart-d7b4252f-0601-4d59-bba2-a798a295823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10869277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.10869277
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1574367909
Short name T351
Test name
Test status
Simulation time 281418740 ps
CPU time 2.67 seconds
Started Feb 26 03:15:04 PM PST 24
Finished Feb 26 03:15:07 PM PST 24
Peak memory 207896 kb
Host smart-0e9ac3e2-ad9a-4e64-8271-550edd8fdd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574367909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1574367909
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3241701669
Short name T368
Test name
Test status
Simulation time 858519257 ps
CPU time 5.64 seconds
Started Feb 26 03:14:58 PM PST 24
Finished Feb 26 03:15:04 PM PST 24
Peak memory 214256 kb
Host smart-33d917fe-88d7-496f-9121-85f1c15b8d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241701669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3241701669
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.332262904
Short name T233
Test name
Test status
Simulation time 231023039 ps
CPU time 5.5 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:15:05 PM PST 24
Peak memory 214240 kb
Host smart-c98ebf18-1696-4781-8ff3-a47a68f62f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332262904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.332262904
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3401298046
Short name T229
Test name
Test status
Simulation time 125989162 ps
CPU time 2.6 seconds
Started Feb 26 03:14:58 PM PST 24
Finished Feb 26 03:15:00 PM PST 24
Peak memory 208136 kb
Host smart-3ca2f1dd-0c52-4ec9-b0c4-0c44b0d8c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401298046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3401298046
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1690467305
Short name T865
Test name
Test status
Simulation time 439929896 ps
CPU time 6.4 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:15:06 PM PST 24
Peak memory 218456 kb
Host smart-fd75de68-384c-4037-ad74-b4e941bff507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690467305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1690467305
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2423461486
Short name T328
Test name
Test status
Simulation time 23294033 ps
CPU time 1.74 seconds
Started Feb 26 03:14:58 PM PST 24
Finished Feb 26 03:15:00 PM PST 24
Peak memory 206692 kb
Host smart-041df6d8-6a4a-4857-9cd9-2338b8860ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423461486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2423461486
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2636730562
Short name T651
Test name
Test status
Simulation time 157911002 ps
CPU time 2.67 seconds
Started Feb 26 03:15:01 PM PST 24
Finished Feb 26 03:15:03 PM PST 24
Peak memory 208616 kb
Host smart-245eb384-2535-41e5-93b5-fc1cd812ad73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636730562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2636730562
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.369531814
Short name T228
Test name
Test status
Simulation time 265596940 ps
CPU time 2.67 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:10 PM PST 24
Peak memory 206836 kb
Host smart-4a84caa9-7e0a-42c8-ae80-04ef33f42f76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369531814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.369531814
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.384823192
Short name T948
Test name
Test status
Simulation time 3227494991 ps
CPU time 33.99 seconds
Started Feb 26 03:15:07 PM PST 24
Finished Feb 26 03:15:41 PM PST 24
Peak memory 208444 kb
Host smart-50195e10-f7a9-4366-87a9-1bf0df33f78b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384823192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.384823192
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.316046263
Short name T898
Test name
Test status
Simulation time 275333535 ps
CPU time 1.89 seconds
Started Feb 26 03:14:57 PM PST 24
Finished Feb 26 03:14:59 PM PST 24
Peak memory 207764 kb
Host smart-fbcb94e3-3d8b-4fef-9a4d-09cd532d2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316046263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.316046263
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3555792656
Short name T945
Test name
Test status
Simulation time 49723206 ps
CPU time 2.61 seconds
Started Feb 26 03:15:02 PM PST 24
Finished Feb 26 03:15:05 PM PST 24
Peak memory 206752 kb
Host smart-dfe5380c-a512-4393-bf57-7e3e6b222cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555792656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3555792656
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3036187562
Short name T701
Test name
Test status
Simulation time 42803346387 ps
CPU time 422.73 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:22:02 PM PST 24
Peak memory 222444 kb
Host smart-d8247a08-ca7f-4660-9730-2ad2f8cf36fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036187562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3036187562
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2311174709
Short name T200
Test name
Test status
Simulation time 656511759 ps
CPU time 14.3 seconds
Started Feb 26 03:15:00 PM PST 24
Finished Feb 26 03:15:15 PM PST 24
Peak memory 222548 kb
Host smart-add01bae-c12e-4bd7-b3fd-9e3673d5a87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311174709 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2311174709
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3226674773
Short name T839
Test name
Test status
Simulation time 265543200 ps
CPU time 6.81 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:15:06 PM PST 24
Peak memory 218428 kb
Host smart-9b08d6e7-3537-4918-8e57-f8657f6449c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226674773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3226674773
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3023879653
Short name T703
Test name
Test status
Simulation time 354913158 ps
CPU time 2.43 seconds
Started Feb 26 03:14:59 PM PST 24
Finished Feb 26 03:15:02 PM PST 24
Peak memory 210164 kb
Host smart-f9620cb1-79a4-425a-b49d-627ba154c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023879653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3023879653
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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