Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3960592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

587436

1

T1

2157

T2

170

T3

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4167516	1			T1	3558		T2	464		T3	1193
values[0x0]	188432	1			T1	795		T2	84		T3	149
values[0x1]	192080	1			T1	797		T2	77		T3	145

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2698181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1849847

1

T1

2894

T2

284

T3

721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24087	1			T1	16		T12	4		T13	3
valid_sources[0x01]	14927	1			T1	17		T12	6		T13	2
valid_sources[0x02]	20504	1			T1	17		T13	6		T14	81
valid_sources[0x03]	22066	1			T1	15		T12	1		T13	3
valid_sources[0x04]	14939	1			T1	14		T12	6		T13	4
valid_sources[0x05]	12604	1			T1	23		T13	3		T14	86
valid_sources[0x06]	17816	1			T1	20		T12	5		T13	4
valid_sources[0x07]	17744	1			T1	16		T12	4		T13	4
valid_sources[0x08]	15430	1			T1	21		T12	1		T13	4
valid_sources[0x09]	12666	1			T1	22		T12	11		T13	4
valid_sources[0x0a]	12172	1			T1	20		T12	6		T13	2
valid_sources[0x0b]	14609	1			T1	22		T12	1		T13	1
valid_sources[0x0c]	33811	1			T1	16		T13	4		T14	85
valid_sources[0x0d]	13856	1			T1	18		T12	2		T13	8
valid_sources[0x0e]	18457	1			T1	22		T12	5		T13	3
valid_sources[0x0f]	13197	1			T1	17		T13	3		T14	97
valid_sources[0x10]	16561	1			T1	20		T12	7		T13	2
valid_sources[0x11]	19964	1			T1	22		T12	3		T13	7
valid_sources[0x12]	13625	1			T1	19		T12	4		T13	6
valid_sources[0x13]	29674	1			T1	14		T12	5		T13	1
valid_sources[0x14]	23350	1			T1	17		T12	2		T13	5
valid_sources[0x15]	12845	1			T1	23		T12	1		T13	5
valid_sources[0x16]	14410	1			T1	15		T12	3		T13	6
valid_sources[0x17]	21728	1			T1	23		T12	3		T13	6
valid_sources[0x18]	24659	1			T1	23		T12	1		T13	7
valid_sources[0x19]	16571	1			T1	28		T12	3		T13	6
valid_sources[0x1a]	28824	1			T1	15		T12	1		T13	2
valid_sources[0x1b]	17594	1			T1	22		T12	4		T13	3
valid_sources[0x1c]	13152	1			T1	17		T12	1		T13	1
valid_sources[0x1d]	29555	1			T1	15		T12	3		T13	7
valid_sources[0x1e]	12851	1			T1	20		T12	1		T13	3
valid_sources[0x1f]	14851	1			T1	20		T12	2		T13	8
valid_sources[0x20]	12258	1			T1	20		T12	1		T13	3
valid_sources[0x21]	19203	1			T1	20		T12	6		T13	1
valid_sources[0x22]	12732	1			T1	24		T12	2		T13	2
valid_sources[0x23]	26452	1			T1	14		T12	1		T13	6
valid_sources[0x24]	14269	1			T1	17		T12	1		T13	3
valid_sources[0x25]	18244	1			T1	21		T12	2		T13	4
valid_sources[0x26]	48691	1			T1	26		T12	4		T13	2
valid_sources[0x27]	13762	1			T1	13		T12	2		T13	2
valid_sources[0x28]	17229	1			T1	21		T12	1		T13	5
valid_sources[0x29]	29921	1			T1	16		T12	3		T13	4
valid_sources[0x2a]	12259	1			T1	21		T13	2		T14	95
valid_sources[0x2b]	17394	1			T1	30		T13	3		T14	92
valid_sources[0x2c]	12943	1			T1	22		T12	6		T13	5
valid_sources[0x2d]	23395	1			T1	17		T12	1		T13	2
valid_sources[0x2e]	12132	1			T1	11		T13	3		T14	91
valid_sources[0x2f]	14799	1			T1	14		T12	4		T13	2
valid_sources[0x30]	12768	1			T1	25		T12	3		T13	3
valid_sources[0x31]	14924	1			T1	19		T2	625		T12	1
valid_sources[0x32]	22100	1			T1	16		T12	1		T13	3
valid_sources[0x33]	12747	1			T1	22		T13	2		T14	102
valid_sources[0x34]	13020	1			T1	24		T12	2		T13	8
valid_sources[0x35]	14442	1			T1	19		T12	1		T13	3
valid_sources[0x36]	12353	1			T1	15		T13	2		T14	81
valid_sources[0x37]	22345	1			T1	24		T12	3		T13	5
valid_sources[0x38]	33082	1			T1	19		T13	2		T14	95
valid_sources[0x39]	18378	1			T1	19		T12	1		T13	7
valid_sources[0x3a]	12653	1			T1	12		T13	7		T14	78
valid_sources[0x3b]	15871	1			T1	20		T12	14		T13	2
valid_sources[0x3c]	13127	1			T1	25		T13	7		T14	76
valid_sources[0x3d]	15803	1			T1	25		T13	2		T14	85
valid_sources[0x3e]	16468	1			T1	20		T14	83		T18	140
valid_sources[0x3f]	13930	1			T1	31		T12	9		T13	3
valid_sources[0x40]	12964	1			T1	20		T12	1		T13	4
valid_sources[0x41]	16952	1			T1	22		T13	6		T14	84
valid_sources[0x42]	12103	1			T1	19		T12	1		T13	9
valid_sources[0x43]	14895	1			T1	21		T12	3		T14	93
valid_sources[0x44]	13562	1			T1	21		T12	1		T13	3
valid_sources[0x45]	12658	1			T1	14		T12	4		T13	5
valid_sources[0x46]	22543	1			T1	19		T12	1		T13	4
valid_sources[0x47]	13040	1			T1	17		T12	3		T14	80
valid_sources[0x48]	13791	1			T1	28		T12	10		T13	3
valid_sources[0x49]	12317	1			T1	17		T12	4		T13	4
valid_sources[0x4a]	13165	1			T1	24		T12	2		T13	3
valid_sources[0x4b]	25925	1			T1	22		T13	5		T14	87
valid_sources[0x4c]	30253	1			T1	22		T13	9		T14	82
valid_sources[0x4d]	16385	1			T1	14		T12	3		T13	9
valid_sources[0x4e]	37255	1			T1	15		T12	2		T13	1
valid_sources[0x4f]	19692	1			T1	21		T12	5		T13	4
valid_sources[0x50]	13907	1			T1	15		T13	4		T14	92
valid_sources[0x51]	20697	1			T1	25		T12	7		T13	5
valid_sources[0x52]	25801	1			T1	16		T12	1		T13	2
valid_sources[0x53]	14196	1			T1	19		T12	3		T13	5
valid_sources[0x54]	12838	1			T1	15		T12	2		T13	7
valid_sources[0x55]	15799	1			T1	13		T12	4		T13	3
valid_sources[0x56]	14805	1			T1	23		T12	6		T13	4
valid_sources[0x57]	12366	1			T1	31		T12	5		T13	4
valid_sources[0x58]	15045	1			T1	23		T12	1		T13	7
valid_sources[0x59]	15976	1			T1	19		T12	2		T13	3
valid_sources[0x5a]	16922	1			T1	28		T12	8		T13	5
valid_sources[0x5b]	13386	1			T1	11		T13	3		T14	97
valid_sources[0x5c]	36702	1			T1	19		T12	3		T13	4
valid_sources[0x5d]	17591	1			T1	15		T12	5		T13	1
valid_sources[0x5e]	13722	1			T1	29		T13	7		T14	91
valid_sources[0x5f]	12173	1			T1	14		T12	5		T13	2
valid_sources[0x60]	37577	1			T1	14		T12	1		T13	6
valid_sources[0x61]	12668	1			T1	21		T12	2		T13	2
valid_sources[0x62]	12629	1			T1	15		T13	1		T14	79
valid_sources[0x63]	15334	1			T1	25		T12	8		T13	4
valid_sources[0x64]	12096	1			T1	22		T12	4		T13	2
valid_sources[0x65]	51687	1			T1	15		T13	2		T14	107
valid_sources[0x66]	13935	1			T1	17		T12	2		T13	3
valid_sources[0x67]	12479	1			T1	14		T12	1		T13	4
valid_sources[0x68]	18737	1			T1	23		T12	3		T13	6
valid_sources[0x69]	12113	1			T1	16		T12	3		T13	1
valid_sources[0x6a]	14328	1			T1	13		T12	4		T13	2
valid_sources[0x6b]	26808	1			T1	17		T12	2		T13	1
valid_sources[0x6c]	13419	1			T1	18		T12	1		T13	1
valid_sources[0x6d]	15552	1			T1	17		T12	2		T13	2
valid_sources[0x6e]	15012	1			T1	27		T12	1		T13	3
valid_sources[0x6f]	19196	1			T1	21		T12	6		T13	4
valid_sources[0x70]	15848	1			T1	31		T12	3		T13	4
valid_sources[0x71]	15761	1			T1	15		T12	2		T13	3
valid_sources[0x72]	12823	1			T1	19		T12	10		T13	2
valid_sources[0x73]	16262	1			T1	18		T12	1		T13	4
valid_sources[0x74]	25307	1			T1	22		T12	1		T13	3
valid_sources[0x75]	13576	1			T1	17		T12	4		T13	5
valid_sources[0x76]	14453	1			T1	16		T12	2		T13	2
valid_sources[0x77]	13068	1			T1	18		T12	1		T13	2
valid_sources[0x78]	13364	1			T1	16		T13	3		T14	94
valid_sources[0x79]	46110	1			T1	18		T12	1		T13	3
valid_sources[0x7a]	39221	1			T1	18		T12	1		T13	8
valid_sources[0x7b]	17234	1			T1	24		T13	4		T14	84
valid_sources[0x7c]	12909	1			T1	19		T12	2		T13	4
valid_sources[0x7d]	18641	1			T1	23		T12	7		T13	3
valid_sources[0x7e]	14661	1			T1	11		T12	1		T13	2
valid_sources[0x7f]	15494	1			T1	27		T12	7		T13	6
valid_sources[0x80]	11875	1			T1	17		T12	1		T13	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330500

1

T1

1194

T2

108

T3

161

values[0x0]

all_enables

biggest_size

135012

1

T1

514

T2

37

T3

115

values[0x1]

all_enables

biggest_size

121924

1

T1

449

T2

25

T3

112