Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28647721	17183	0	0
attest_sw_binding_0_rd_A	28647721	1096	0	0
attest_sw_binding_1_rd_A	28647721	939	0	0
attest_sw_binding_2_rd_A	28647721	923	0	0
attest_sw_binding_3_rd_A	28647721	927	0	0
attest_sw_binding_4_rd_A	28647721	893	0	0
attest_sw_binding_5_rd_A	28647721	964	0	0
attest_sw_binding_6_rd_A	28647721	913	0	0
attest_sw_binding_7_rd_A	28647721	906	0	0
intr_enable_rd_A	28647721	1574	0	0
key_version_rd_A	28647721	899	0	0
max_creator_key_ver_regwen_rd_A	28647721	959	0	0
max_owner_int_key_ver_regwen_rd_A	28647721	865	0	0
max_owner_key_ver_regwen_rd_A	28647721	952	0	0
reseed_interval_regwen_rd_A	28647721	905	0	0
salt_0_rd_A	28647721	919	0	0
salt_1_rd_A	28647721	959	0	0
salt_2_rd_A	28647721	868	0	0
salt_3_rd_A	28647721	828	0	0
salt_4_rd_A	28647721	825	0	0
salt_5_rd_A	28647721	984	0	0
salt_6_rd_A	28647721	938	0	0
salt_7_rd_A	28647721	902	0	0
sealing_sw_binding_0_rd_A	28647721	884	0	0
sealing_sw_binding_1_rd_A	28647721	788	0	0
sealing_sw_binding_2_rd_A	28647721	923	0	0
sealing_sw_binding_3_rd_A	28647721	965	0	0
sealing_sw_binding_4_rd_A	28647721	840	0	0
sealing_sw_binding_5_rd_A	28647721	865	0	0
sealing_sw_binding_6_rd_A	28647721	872	0	0
sealing_sw_binding_7_rd_A	28647721	871	0	0
sideload_clear_rd_A	28647721	1022	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	17183	0	0
T16	6747	51	0	0
T17	11378	0	0	0
T18	135720	0	0	0
T21	5983	0	0	0
T32	283111	0	0	0
T33	11039	0	0	0
T34	13474	0	0	0
T38	9811	0	0	0
T42	0	222	0	0
T72	7271	0	0	0
T73	1104	0	0	0
T88	0	185	0	0
T98	0	21	0	0
T109	0	69	0	0
T110	0	62	0	0
T111	0	290	0	0
T112	0	118	0	0
T113	0	31	0	0
T114	0	136	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	1096	0	0
T42	25107	82	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	39	0	0
T102	0	31	0	0
T107	0	40	0	0
T109	11171	0	0	0
T111	0	30	0	0
T122	0	8	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	10	0	0
T163	0	47	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	939	0	0
T42	25107	91	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	41	0	0
T102	0	16	0	0
T107	0	22	0	0
T109	11171	0	0	0
T111	0	17	0	0
T112	0	3	0	0
T122	0	9	0	0
T160	0	5	0	0
T163	0	42	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	8	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	923	0	0
T42	25107	69	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	43	0	0
T102	0	23	0	0
T107	0	25	0	0
T109	11171	0	0	0
T111	0	32	0	0
T112	0	4	0	0
T122	0	1	0	0
T160	0	6	0	0
T161	0	2	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	11	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	927	0	0
T42	25107	72	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	24	0	0
T102	0	24	0	0
T107	0	31	0	0
T109	11171	0	0	0
T111	0	31	0	0
T112	0	5	0	0
T122	0	3	0	0
T161	0	1	0	0
T162	0	3	0	0
T163	0	18	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	893	0	0
T42	25107	63	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	26	0	0
T102	0	37	0	0
T107	0	14	0	0
T109	11171	0	0	0
T111	0	13	0	0
T122	0	2	0	0
T160	0	4	0	0
T162	0	7	0	0
T163	0	36	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	14	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	964	0	0
T42	25107	50	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	29	0	0
T102	0	30	0	0
T107	0	33	0	0
T109	11171	0	0	0
T111	0	1	0	0
T112	0	10	0	0
T122	0	1	0	0
T160	0	5	0	0
T161	0	3	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	28	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	913	0	0
T42	25107	44	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	41	0	0
T102	0	20	0	0
T107	0	36	0	0
T109	11171	0	0	0
T111	0	2	0	0
T112	0	1	0	0
T161	0	1	0	0
T163	0	38	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T170	0	8	0	0
T171	0	7	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	906	0	0
T42	25107	54	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	20	0	0
T102	0	29	0	0
T107	0	20	0	0
T109	11171	0	0	0
T111	0	28	0	0
T112	0	19	0	0
T122	0	16	0	0
T160	0	1	0	0
T161	0	4	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	1574	0	0
T21	5983	0	0	0
T32	283111	17	0	0
T33	11039	0	0	0
T34	13474	0	0	0
T38	9811	0	0	0
T42	0	76	0	0
T72	7271	0	0	0
T73	1104	0	0	0
T74	16965	0	0	0
T75	4937	0	0	0
T76	18786	0	0	0
T98	0	48	0	0
T102	0	28	0	0
T111	0	14	0	0
T112	0	8	0	0
T122	0	2	0	0
T124	0	8	0	0
T160	0	6	0	0
T172	0	23	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	899	0	0
T42	25107	32	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	41	0	0
T102	0	29	0	0
T107	0	24	0	0
T109	11171	0	0	0
T111	0	24	0	0
T112	0	1	0	0
T122	0	3	0	0
T160	0	6	0	0
T161	0	2	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	11	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	959	0	0
T42	25107	66	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	18	0	0
T102	0	29	0	0
T107	0	21	0	0
T109	11171	0	0	0
T111	0	26	0	0
T112	0	9	0	0
T122	0	7	0	0
T160	0	1	0	0
T161	0	4	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	23	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	865	0	0
T42	25107	38	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	22	0	0
T102	0	22	0	0
T107	0	9	0	0
T109	11171	0	0	0
T111	0	10	0	0
T112	0	4	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	15	0	0
T163	0	35	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	952	0	0
T42	25107	46	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	49	0	0
T102	0	18	0	0
T107	0	28	0	0
T109	11171	0	0	0
T111	0	16	0	0
T112	0	18	0	0
T122	0	1	0	0
T160	0	10	0	0
T161	0	5	0	0
T162	0	1	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	905	0	0
T42	25107	53	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	23	0	0
T102	0	24	0	0
T107	0	28	0	0
T109	11171	0	0	0
T111	0	21	0	0
T112	0	18	0	0
T122	0	9	0	0
T160	0	4	0	0
T161	0	8	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	13	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	919	0	0
T42	25107	37	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	27	0	0
T102	0	27	0	0
T107	0	28	0	0
T109	11171	0	0	0
T111	0	21	0	0
T112	0	5	0	0
T122	0	26	0	0
T160	0	5	0	0
T161	0	7	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	6	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	959	0	0
T42	25107	40	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	38	0	0
T102	0	33	0	0
T107	0	13	0	0
T109	11171	0	0	0
T111	0	19	0	0
T122	0	14	0	0
T160	0	6	0	0
T161	0	7	0	0
T162	0	3	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	9	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	868	0	0
T42	25107	36	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	27	0	0
T102	0	33	0	0
T107	0	32	0	0
T109	11171	0	0	0
T111	0	11	0	0
T112	0	7	0	0
T122	0	1	0	0
T160	0	7	0	0
T161	0	1	0	0
T162	0	5	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	828	0	0
T42	25107	44	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	41	0	0
T102	0	31	0	0
T107	0	13	0	0
T109	11171	0	0	0
T111	0	6	0	0
T112	0	5	0	0
T122	0	1	0	0
T160	0	6	0	0
T161	0	2	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	825	0	0
T42	25107	60	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	21	0	0
T102	0	20	0	0
T107	0	17	0	0
T109	11171	0	0	0
T111	0	25	0	0
T122	0	11	0	0
T160	0	5	0	0
T162	0	9	0	0
T163	0	35	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	27	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	984	0	0
T42	25107	74	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	30	0	0
T102	0	42	0	0
T107	0	24	0	0
T109	11171	0	0	0
T111	0	11	0	0
T112	0	1	0	0
T122	0	8	0	0
T160	0	6	0	0
T161	0	9	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	15	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	938	0	0
T42	25107	63	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	38	0	0
T102	0	41	0	0
T107	0	31	0	0
T109	11171	0	0	0
T111	0	5	0	0
T112	0	1	0	0
T122	0	4	0	0
T160	0	7	0	0
T161	0	2	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	902	0	0
T42	25107	69	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	22	0	0
T102	0	25	0	0
T107	0	14	0	0
T109	11171	0	0	0
T111	0	3	0	0
T112	0	1	0	0
T122	0	1	0	0
T160	0	2	0	0
T161	0	4	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	5	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	884	0	0
T42	25107	76	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	26	0	0
T102	0	36	0	0
T107	0	27	0	0
T109	11171	0	0	0
T111	0	13	0	0
T112	0	2	0	0
T122	0	1	0	0
T160	0	9	0	0
T161	0	5	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	2	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	788	0	0
T42	25107	74	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	13	0	0
T102	0	15	0	0
T107	0	18	0	0
T109	11171	0	0	0
T111	0	16	0	0
T112	0	1	0	0
T122	0	5	0	0
T160	0	8	0	0
T161	0	8	0	0
T163	0	38	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	923	0	0
T42	25107	45	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	11	0	0
T102	0	31	0	0
T107	0	17	0	0
T109	11171	0	0	0
T111	0	13	0	0
T112	0	20	0	0
T122	0	2	0	0
T160	0	3	0	0
T161	0	7	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	1	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	965	0	0
T42	25107	71	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	24	0	0
T102	0	27	0	0
T107	0	11	0	0
T109	11171	0	0	0
T111	0	22	0	0
T112	0	8	0	0
T122	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	3	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	840	0	0
T42	25107	43	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	33	0	0
T102	0	38	0	0
T107	0	14	0	0
T109	11171	0	0	0
T111	0	14	0	0
T112	0	6	0	0
T122	0	7	0	0
T160	0	8	0	0
T161	0	6	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	4	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	865	0	0
T42	25107	71	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	31	0	0
T102	0	27	0	0
T107	0	33	0	0
T109	11171	0	0	0
T111	0	14	0	0
T112	0	1	0	0
T122	0	1	0	0
T160	0	4	0	0
T161	0	3	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	5	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	872	0	0
T42	25107	51	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	38	0	0
T102	0	21	0	0
T107	0	31	0	0
T109	11171	0	0	0
T111	0	16	0	0
T112	0	9	0	0
T122	0	10	0	0
T160	0	7	0	0
T161	0	1	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	7	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	871	0	0
T42	25107	69	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	36	0	0
T102	0	25	0	0
T107	0	17	0	0
T109	11171	0	0	0
T111	0	16	0	0
T112	0	6	0	0
T122	0	5	0	0
T160	0	8	0	0
T161	0	4	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0
T169	0	7	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28647721	1022	0	0
T42	25107	96	0	0
T46	5041	0	0	0
T77	8720	0	0	0
T98	9712	27	0	0
T102	0	31	0	0
T107	0	14	0	0
T109	11171	0	0	0
T111	0	24	0	0
T112	0	4	0	0
T122	0	4	0	0
T160	0	9	0	0
T161	0	1	0	0
T162	0	9	0	0
T164	10759	0	0	0
T165	3440	0	0	0
T166	3074	0	0	0
T167	10883	0	0	0
T168	28570	0	0	0