Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4503149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

579260

1

T1

146

T2

167

T3

485

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4700284	1			T1	1449		T2	1776		T3	5370
values[0x0]	189405	1			T1	46		T2	93		T3	184
values[0x1]	192720	1			T1	42		T2	71		T3	169

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3057694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2024715

1

T1

558

T2

731

T3

2183

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14359	1			T1	7		T4	7		T15	2
valid_sources[0x01]	14184	1			T1	7		T4	7		T14	1
valid_sources[0x02]	14433	1			T1	6		T4	6		T14	2
valid_sources[0x03]	51902	1			T1	5		T4	5		T13	70
valid_sources[0x04]	14922	1			T1	6		T4	5		T14	10
valid_sources[0x05]	14840	1			T1	3		T4	5		T14	1
valid_sources[0x06]	14328	1			T1	11		T4	4		T15	2
valid_sources[0x07]	18077	1			T1	9		T4	14		T14	2
valid_sources[0x08]	16297	1			T1	5		T4	2		T13	1
valid_sources[0x09]	15434	1			T1	7		T4	5		T14	1
valid_sources[0x0a]	14242	1			T1	7		T4	7		T14	2
valid_sources[0x0b]	18876	1			T1	10		T4	14		T15	1
valid_sources[0x0c]	340671	1			T1	5		T4	7		T14	2
valid_sources[0x0d]	18422	1			T1	3		T4	2		T14	3
valid_sources[0x0e]	15800	1			T1	2		T4	4		T14	2
valid_sources[0x0f]	14054	1			T1	7		T4	1		T14	3
valid_sources[0x10]	14428	1			T1	4		T4	3		T14	3
valid_sources[0x11]	15422	1			T1	6		T4	5		T13	1
valid_sources[0x12]	18898	1			T1	7		T4	6		T14	2
valid_sources[0x13]	14659	1			T1	7		T4	6		T18	6
valid_sources[0x14]	14693	1			T1	2		T4	16		T18	5
valid_sources[0x15]	20521	1			T1	7		T4	10		T13	2
valid_sources[0x16]	15681	1			T1	10		T4	6		T13	210
valid_sources[0x17]	21829	1			T1	8		T4	15		T14	4
valid_sources[0x18]	14697	1			T1	9		T4	15		T13	52
valid_sources[0x19]	27870	1			T1	6		T4	18		T14	1
valid_sources[0x1a]	22252	1			T1	3		T4	8		T14	1
valid_sources[0x1b]	15209	1			T1	7		T4	11		T14	1
valid_sources[0x1c]	13793	1			T1	5		T4	16		T14	3
valid_sources[0x1d]	16050	1			T1	5		T4	10		T13	1
valid_sources[0x1e]	15288	1			T1	8		T4	18		T14	1
valid_sources[0x1f]	15456	1			T1	5		T4	1		T14	5
valid_sources[0x20]	14744	1			T1	2		T4	10		T13	7
valid_sources[0x21]	15165	1			T1	6		T4	9		T14	4
valid_sources[0x22]	15018	1			T1	5		T4	4		T14	1
valid_sources[0x23]	14886	1			T1	3		T4	5		T13	1
valid_sources[0x24]	14540	1			T1	10		T4	7		T13	117
valid_sources[0x25]	16014	1			T1	3		T4	5		T14	2
valid_sources[0x26]	15876	1			T1	3		T4	3		T13	45
valid_sources[0x27]	14944	1			T1	6		T4	18		T14	4
valid_sources[0x28]	14726	1			T1	5		T4	6		T14	2
valid_sources[0x29]	15101	1			T1	3		T4	16		T14	1
valid_sources[0x2a]	14736	1			T1	8		T4	6		T14	4
valid_sources[0x2b]	14578	1			T1	6		T4	25		T14	1
valid_sources[0x2c]	16196	1			T1	11		T4	6		T15	4
valid_sources[0x2d]	14907	1			T1	6		T4	3		T14	2
valid_sources[0x2e]	15650	1			T1	4		T4	24		T14	2
valid_sources[0x2f]	20886	1			T1	5		T4	15		T14	2
valid_sources[0x30]	15849	1			T1	11		T4	11		T15	1
valid_sources[0x31]	14348	1			T1	10		T4	17		T15	4
valid_sources[0x32]	15881	1			T1	5		T4	5		T14	1
valid_sources[0x33]	16044	1			T1	6		T4	10		T14	4
valid_sources[0x34]	18267	1			T1	4		T4	8		T14	1
valid_sources[0x35]	15000	1			T1	8		T4	16		T13	41
valid_sources[0x36]	15962	1			T1	7		T4	11		T14	2
valid_sources[0x37]	15283	1			T1	7		T4	8		T14	5
valid_sources[0x38]	17219	1			T1	6		T4	7		T14	2
valid_sources[0x39]	14799	1			T1	5		T4	10		T14	1
valid_sources[0x3a]	31274	1			T1	4		T4	7		T14	1
valid_sources[0x3b]	14671	1			T1	9		T4	14		T18	7
valid_sources[0x3c]	14566	1			T1	5		T4	14		T14	4
valid_sources[0x3d]	27082	1			T1	5		T4	4		T15	6
valid_sources[0x3e]	16366	1			T1	6		T4	8		T14	2
valid_sources[0x3f]	14284	1			T1	9		T4	4		T14	2
valid_sources[0x40]	34196	1			T1	8		T4	2		T14	2
valid_sources[0x41]	15659	1			T1	5		T4	10		T13	3
valid_sources[0x42]	13809	1			T1	6		T4	6		T14	1
valid_sources[0x43]	14679	1			T1	4		T4	4		T14	5
valid_sources[0x44]	14612	1			T1	6		T4	10		T14	1
valid_sources[0x45]	14769	1			T1	7		T4	7		T14	1
valid_sources[0x46]	15384	1			T1	11		T4	9		T13	2
valid_sources[0x47]	26891	1			T1	6		T4	5		T13	38
valid_sources[0x48]	24118	1			T1	2		T4	7		T15	1
valid_sources[0x49]	15338	1			T1	7		T4	9		T18	11
valid_sources[0x4a]	19354	1			T1	4		T4	9		T15	6
valid_sources[0x4b]	17286	1			T1	4		T4	7		T14	6
valid_sources[0x4c]	22219	1			T1	7		T2	1940		T3	5723
valid_sources[0x4d]	14382	1			T1	3		T4	5		T14	2
valid_sources[0x4e]	13968	1			T1	13		T4	10		T15	1
valid_sources[0x4f]	14346	1			T1	1		T4	6		T14	1
valid_sources[0x50]	15744	1			T4	16		T14	2		T15	2
valid_sources[0x51]	14353	1			T1	4		T4	23		T13	3
valid_sources[0x52]	15575	1			T1	3		T4	15		T14	4
valid_sources[0x53]	30449	1			T1	6		T4	13		T14	2
valid_sources[0x54]	16966	1			T1	8		T4	13		T14	1
valid_sources[0x55]	39901	1			T1	7		T4	7		T14	3
valid_sources[0x56]	18025	1			T1	3		T4	8		T14	1
valid_sources[0x57]	22347	1			T1	9		T4	5		T13	3
valid_sources[0x58]	14973	1			T1	4		T4	22		T14	2
valid_sources[0x59]	15065	1			T1	8		T4	5		T14	2
valid_sources[0x5a]	35167	1			T1	3		T4	11		T13	1
valid_sources[0x5b]	14984	1			T1	4		T4	5		T15	4
valid_sources[0x5c]	16354	1			T1	5		T4	13		T13	15
valid_sources[0x5d]	19347	1			T1	5		T4	20		T13	10
valid_sources[0x5e]	15849	1			T1	3		T4	13		T14	2
valid_sources[0x5f]	15095	1			T1	4		T4	10		T14	1
valid_sources[0x60]	15394	1			T1	8		T4	11		T13	1
valid_sources[0x61]	19615	1			T1	5		T4	5		T13	1
valid_sources[0x62]	15132	1			T1	5		T4	6		T13	79
valid_sources[0x63]	15228	1			T1	4		T4	5		T14	1
valid_sources[0x64]	15470	1			T1	8		T4	9		T15	4
valid_sources[0x65]	14602	1			T1	4		T4	1		T14	1
valid_sources[0x66]	15070	1			T1	5		T4	21		T14	2
valid_sources[0x67]	14801	1			T1	2		T4	11		T14	3
valid_sources[0x68]	16075	1			T1	4		T4	9		T13	65
valid_sources[0x69]	24652	1			T1	4		T4	12		T15	7
valid_sources[0x6a]	24711	1			T1	9		T4	7		T14	3
valid_sources[0x6b]	14658	1			T1	7		T4	3		T14	2
valid_sources[0x6c]	17469	1			T1	8		T4	9		T14	1
valid_sources[0x6d]	15659	1			T1	9		T4	8		T14	1
valid_sources[0x6e]	15310	1			T1	8		T4	5		T14	3
valid_sources[0x6f]	18149	1			T1	6		T4	4		T15	2
valid_sources[0x70]	14627	1			T1	5		T4	3		T14	3
valid_sources[0x71]	14960	1			T1	10		T4	5		T14	4
valid_sources[0x72]	15010	1			T1	2		T4	7		T15	3
valid_sources[0x73]	15342	1			T1	5		T4	6		T14	5
valid_sources[0x74]	15252	1			T1	1		T4	10		T14	5
valid_sources[0x75]	28407	1			T1	7		T4	5		T14	2
valid_sources[0x76]	14525	1			T1	2		T4	22		T14	2
valid_sources[0x77]	15827	1			T1	5		T4	16		T13	5
valid_sources[0x78]	14241	1			T1	8		T4	16		T14	3
valid_sources[0x79]	15307	1			T1	5		T4	12		T13	1
valid_sources[0x7a]	14608	1			T1	9		T4	9		T14	6
valid_sources[0x7b]	15201	1			T1	8		T4	4		T15	1
valid_sources[0x7c]	17886	1			T1	8		T4	3		T15	2
valid_sources[0x7d]	43466	1			T1	7		T4	17		T18	15
valid_sources[0x7e]	14922	1			T1	10		T4	6		T14	1
valid_sources[0x7f]	15019	1			T1	10		T4	9		T13	127
valid_sources[0x80]	16532	1			T1	2		T4	12		T13	69

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

317657

1

T1

119

T2

50

T3

284

values[0x0]

all_enables

biggest_size

137606

1

T1

19

T2

72

T3

123

values[0x1]

all_enables

biggest_size

123997

1

T1

8

T2

45

T3

78