Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4891850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

560927

1

T1

93

T2

112

T3

339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5081573	1			T1	178		T2	714		T3	328
values[0x0]	183930	1			T1	33		T2	25		T3	106
values[0x1]	187274	1			T1	32		T2	31		T3	120

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3314270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2138507

1

T1

129

T2

320

T3

384

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23336	1			T4	2		T13	36		T15	19
valid_sources[0x01]	18302	1			T3	2		T13	28		T15	19
valid_sources[0x02]	18156	1			T3	1		T13	41		T15	17
valid_sources[0x03]	21037	1			T1	1		T3	3		T13	46
valid_sources[0x04]	32092	1			T1	1		T13	36		T15	31
valid_sources[0x05]	21078	1			T1	1		T3	2		T13	35
valid_sources[0x06]	39166	1			T3	3		T4	2		T13	36
valid_sources[0x07]	17039	1			T1	2		T3	1		T13	34
valid_sources[0x08]	16212	1			T1	2		T3	1		T13	39
valid_sources[0x09]	15973	1			T3	2		T13	35		T15	23
valid_sources[0x0a]	21256	1			T3	2		T13	42		T15	17
valid_sources[0x0b]	18198	1			T3	6		T13	27		T15	19
valid_sources[0x0c]	16291	1			T3	3		T13	42		T15	19
valid_sources[0x0d]	36044	1			T3	3		T13	25		T15	12
valid_sources[0x0e]	15445	1			T3	1		T13	38		T15	14
valid_sources[0x0f]	18956	1			T3	6		T13	45		T15	16
valid_sources[0x10]	16316	1			T3	2		T13	32		T15	20
valid_sources[0x11]	17141	1			T3	1		T4	2		T13	37
valid_sources[0x12]	19295	1			T13	38		T15	29		T16	24
valid_sources[0x13]	16652	1			T13	40		T15	24		T16	38
valid_sources[0x14]	24101	1			T13	25		T15	15		T16	15
valid_sources[0x15]	17977	1			T3	4		T13	36		T15	20
valid_sources[0x16]	17929	1			T3	2		T13	34		T15	21
valid_sources[0x17]	22219	1			T3	2		T13	38		T15	36
valid_sources[0x18]	25817	1			T1	4		T3	1		T13	28
valid_sources[0x19]	17998	1			T3	1		T13	31		T15	24
valid_sources[0x1a]	79641	1			T1	4		T3	4		T13	34
valid_sources[0x1b]	17148	1			T3	1		T13	34		T15	14
valid_sources[0x1c]	17005	1			T1	1		T3	2		T13	30
valid_sources[0x1d]	15830	1			T3	1		T13	26		T15	14
valid_sources[0x1e]	15947	1			T3	1		T13	39		T15	25
valid_sources[0x1f]	20414	1			T1	4		T3	2		T13	43
valid_sources[0x20]	16112	1			T1	7		T3	1		T13	31
valid_sources[0x21]	16869	1			T3	2		T13	40		T15	25
valid_sources[0x22]	21719	1			T1	2		T13	37		T15	18
valid_sources[0x23]	38502	1			T1	5		T3	1		T13	30
valid_sources[0x24]	16939	1			T3	4		T13	41		T15	14
valid_sources[0x25]	17694	1			T1	1		T3	2		T13	39
valid_sources[0x26]	17252	1			T13	27		T15	19		T16	20
valid_sources[0x27]	16856	1			T1	2		T2	1		T3	3
valid_sources[0x28]	16969	1			T1	1		T3	2		T4	2
valid_sources[0x29]	16733	1			T3	1		T13	44		T15	24
valid_sources[0x2a]	17288	1			T3	5		T13	41		T15	27
valid_sources[0x2b]	16255	1			T13	29		T15	23		T16	38
valid_sources[0x2c]	17729	1			T3	1		T13	38		T15	22
valid_sources[0x2d]	18531	1			T1	9		T3	3		T13	32
valid_sources[0x2e]	17448	1			T4	2		T13	35		T15	23
valid_sources[0x2f]	18866	1			T3	4		T13	23		T15	15
valid_sources[0x30]	21108	1			T3	1		T13	32		T15	23
valid_sources[0x31]	16634	1			T1	3		T3	2		T13	36
valid_sources[0x32]	15742	1			T3	4		T13	26		T15	23
valid_sources[0x33]	20213	1			T3	2		T13	30		T15	21
valid_sources[0x34]	17720	1			T3	2		T13	38		T15	22
valid_sources[0x35]	15470	1			T3	2		T13	31		T15	20
valid_sources[0x36]	22358	1			T1	4		T3	2		T13	55
valid_sources[0x37]	26985	1			T3	3		T13	31		T15	19
valid_sources[0x38]	15603	1			T3	2		T13	39		T15	8
valid_sources[0x39]	17058	1			T1	5		T3	3		T13	31
valid_sources[0x3a]	16541	1			T1	1		T13	30		T15	34
valid_sources[0x3b]	15730	1			T3	1		T13	43		T15	22
valid_sources[0x3c]	16391	1			T3	2		T13	42		T15	21
valid_sources[0x3d]	16263	1			T3	2		T13	30		T15	26
valid_sources[0x3e]	15449	1			T3	3		T13	35		T15	15
valid_sources[0x3f]	23585	1			T3	1		T13	30		T15	19
valid_sources[0x40]	199125	1			T1	2		T3	5		T13	40
valid_sources[0x41]	27705	1			T3	3		T13	27		T15	23
valid_sources[0x42]	15879	1			T3	3		T13	42		T15	25
valid_sources[0x43]	16016	1			T3	2		T13	39		T15	27
valid_sources[0x44]	16942	1			T3	3		T13	23		T15	19
valid_sources[0x45]	18286	1			T1	5		T3	3		T13	31
valid_sources[0x46]	19432	1			T1	4		T3	3		T13	31
valid_sources[0x47]	16927	1			T3	3		T13	35		T15	14
valid_sources[0x48]	21171	1			T3	4		T13	49		T15	17
valid_sources[0x49]	18770	1			T13	29		T15	34		T16	29
valid_sources[0x4a]	17163	1			T1	1		T3	2		T13	41
valid_sources[0x4b]	15778	1			T3	3		T13	36		T15	20
valid_sources[0x4c]	18143	1			T1	4		T3	2		T13	41
valid_sources[0x4d]	19826	1			T3	1		T13	33		T15	32
valid_sources[0x4e]	188270	1			T1	3		T3	5		T13	33
valid_sources[0x4f]	20691	1			T3	3		T4	70		T13	38
valid_sources[0x50]	16500	1			T3	2		T13	41		T15	17
valid_sources[0x51]	19983	1			T3	3		T13	39		T15	15
valid_sources[0x52]	30289	1			T3	2		T13	36		T15	13
valid_sources[0x53]	17912	1			T3	3		T13	25		T15	15
valid_sources[0x54]	16639	1			T1	12		T3	1		T13	34
valid_sources[0x55]	17478	1			T3	2		T13	34		T15	21
valid_sources[0x56]	20112	1			T3	5		T13	40		T15	17
valid_sources[0x57]	18433	1			T1	4		T3	1		T13	28
valid_sources[0x58]	15678	1			T1	3		T3	6		T13	45
valid_sources[0x59]	22996	1			T1	4		T3	2		T13	43
valid_sources[0x5a]	17223	1			T1	9		T3	2		T13	42
valid_sources[0x5b]	17067	1			T3	8		T13	36		T15	19
valid_sources[0x5c]	16244	1			T3	1		T13	56		T15	18
valid_sources[0x5d]	15678	1			T3	1		T13	41		T15	24
valid_sources[0x5e]	17429	1			T3	4		T13	29		T15	20
valid_sources[0x5f]	21436	1			T3	4		T13	31		T15	24
valid_sources[0x60]	16113	1			T3	2		T13	42		T15	26
valid_sources[0x61]	16906	1			T3	1		T4	3		T13	44
valid_sources[0x62]	23268	1			T3	3		T13	46		T15	12
valid_sources[0x63]	16818	1			T3	2		T13	33		T15	23
valid_sources[0x64]	15321	1			T3	1		T13	43		T15	23
valid_sources[0x65]	17797	1			T1	4		T3	1		T13	39
valid_sources[0x66]	15975	1			T3	1		T13	34		T15	24
valid_sources[0x67]	16063	1			T1	7		T3	4		T13	35
valid_sources[0x68]	18375	1			T3	1		T4	2		T13	49
valid_sources[0x69]	28720	1			T3	2		T13	33		T15	27
valid_sources[0x6a]	17262	1			T13	31		T15	26		T16	17
valid_sources[0x6b]	16611	1			T3	2		T13	43		T15	23
valid_sources[0x6c]	17527	1			T3	1		T13	30		T15	13
valid_sources[0x6d]	20993	1			T3	5		T13	43		T15	24
valid_sources[0x6e]	16828	1			T3	1		T4	2		T13	33
valid_sources[0x6f]	15998	1			T1	7		T3	2		T13	33
valid_sources[0x70]	17118	1			T1	2		T3	4		T13	35
valid_sources[0x71]	17189	1			T3	1		T13	54		T15	20
valid_sources[0x72]	24119	1			T3	2		T13	30		T15	24
valid_sources[0x73]	16964	1			T13	39		T15	16		T16	18
valid_sources[0x74]	17546	1			T3	5		T13	38		T15	23
valid_sources[0x75]	17045	1			T3	1		T13	38		T15	27
valid_sources[0x76]	16347	1			T3	4		T13	51		T15	21
valid_sources[0x77]	16160	1			T3	4		T13	35		T15	19
valid_sources[0x78]	15398	1			T1	1		T3	1		T13	43
valid_sources[0x79]	16435	1			T3	2		T13	27		T15	24
valid_sources[0x7a]	19049	1			T3	2		T13	36		T15	28
valid_sources[0x7b]	16866	1			T3	2		T13	29		T15	24
valid_sources[0x7c]	16185	1			T3	7		T13	37		T15	21
valid_sources[0x7d]	15995	1			T1	4		T13	46		T15	16
valid_sources[0x7e]	22367	1			T3	2		T13	36		T15	19
valid_sources[0x7f]	24917	1			T1	2		T3	2		T13	30
valid_sources[0x80]	24000	1			T3	2		T4	2		T13	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

308531

1

T1

50

T2

94

T3

176

values[0x0]

all_enables

biggest_size

132787

1

T1

24

T2

11

T3

75

values[0x1]

all_enables

biggest_size

119609

1

T1

19

T2

7

T3

88