Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32038991	16128	0	0
attest_sw_binding_0_rd_A	32038991	1031	0	0
attest_sw_binding_1_rd_A	32038991	952	0	0
attest_sw_binding_2_rd_A	32038991	903	0	0
attest_sw_binding_3_rd_A	32038991	973	0	0
attest_sw_binding_4_rd_A	32038991	975	0	0
attest_sw_binding_5_rd_A	32038991	936	0	0
attest_sw_binding_6_rd_A	32038991	980	0	0
attest_sw_binding_7_rd_A	32038991	953	0	0
intr_enable_rd_A	32038991	1537	0	0
key_version_rd_A	32038991	955	0	0
max_creator_key_ver_regwen_rd_A	32038991	1034	0	0
max_owner_int_key_ver_regwen_rd_A	32038991	1000	0	0
max_owner_key_ver_regwen_rd_A	32038991	990	0	0
reseed_interval_regwen_rd_A	32038991	1052	0	0
salt_0_rd_A	32038991	916	0	0
salt_1_rd_A	32038991	906	0	0
salt_2_rd_A	32038991	897	0	0
salt_3_rd_A	32038991	998	0	0
salt_4_rd_A	32038991	974	0	0
salt_5_rd_A	32038991	1010	0	0
salt_6_rd_A	32038991	867	0	0
salt_7_rd_A	32038991	985	0	0
sealing_sw_binding_0_rd_A	32038991	913	0	0
sealing_sw_binding_1_rd_A	32038991	921	0	0
sealing_sw_binding_2_rd_A	32038991	992	0	0
sealing_sw_binding_3_rd_A	32038991	867	0	0
sealing_sw_binding_4_rd_A	32038991	1022	0	0
sealing_sw_binding_5_rd_A	32038991	854	0	0
sealing_sw_binding_6_rd_A	32038991	968	0	0
sealing_sw_binding_7_rd_A	32038991	903	0	0
sideload_clear_rd_A	32038991	868	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	16128	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T35	5771	0	0	0
T48	16457	526	0	0
T61	4996	0	0	0
T100	9777	497	0	0
T101	7275	20	0	0
T102	0	139	0	0
T103	0	502	0	0
T104	0	24	0	0
T106	6032	4	0	0
T110	12002	54	0	0
T120	0	173	0	0
T122	0	60	0	0
T123	7033	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1031	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	15	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	23	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	42	0	0
T117	0	16	0	0
T118	0	17	0	0
T165	0	9	0	0
T166	0	8	0	0
T167	0	76	0	0
T168	0	35	0	0
T169	0	6	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	952	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	30	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	28	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	33	0	0
T117	0	31	0	0
T118	0	6	0	0
T165	0	7	0	0
T166	0	6	0	0
T167	0	96	0	0
T168	0	20	0	0
T170	0	9	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	903	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	10	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	19	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	44	0	0
T117	0	49	0	0
T118	0	14	0	0
T165	0	2	0	0
T166	0	4	0	0
T167	0	78	0	0
T168	0	7	0	0
T171	0	45	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	973	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	21	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	14	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	49	0	0
T117	0	46	0	0
T118	0	9	0	0
T165	0	9	0	0
T167	0	71	0	0
T168	0	11	0	0
T169	0	2	0	0
T171	0	48	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	975	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	7	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	17	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	72	0	0
T117	0	33	0	0
T118	0	17	0	0
T165	0	2	0	0
T166	0	18	0	0
T167	0	54	0	0
T168	0	11	0	0
T170	0	8	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	936	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	14	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	9	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	50	0	0
T117	0	27	0	0
T118	0	12	0	0
T165	0	7	0	0
T166	0	7	0	0
T167	0	80	0	0
T168	0	8	0	0
T170	0	5	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	980	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	9	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	19	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	53	0	0
T117	0	24	0	0
T118	0	27	0	0
T165	0	4	0	0
T166	0	9	0	0
T167	0	85	0	0
T169	0	2	0	0
T171	0	39	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	953	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	6	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	17	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	17	0	0
T117	0	25	0	0
T118	0	22	0	0
T166	0	10	0	0
T167	0	83	0	0
T168	0	8	0	0
T169	0	9	0	0
T170	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1537	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	19	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	27	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	28	0	0
T117	0	37	0	0
T118	0	24	0	0
T133	0	17	0	0
T165	0	8	0	0
T166	0	7	0	0
T172	0	13	0	0
T173	0	20	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	955	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	13	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	39	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	22	0	0
T117	0	42	0	0
T118	0	31	0	0
T165	0	4	0	0
T166	0	2	0	0
T167	0	59	0	0
T168	0	13	0	0
T169	0	2	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1034	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	28	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	19	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	62	0	0
T117	0	44	0	0
T118	0	20	0	0
T165	0	8	0	0
T166	0	2	0	0
T167	0	62	0	0
T168	0	16	0	0
T169	0	5	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1000	0	0
T2	9320	4	0	0
T3	7172	0	0	0
T4	3843	0	0	0
T13	33011	0	0	0
T14	128483	0	0	0
T15	46735	0	0	0
T16	97104	0	0	0
T17	81088	0	0	0
T18	1521	0	0	0
T78	4074	0	0	0
T101	0	14	0	0
T106	0	19	0	0
T114	0	47	0	0
T117	0	21	0	0
T118	0	14	0	0
T165	0	7	0	0
T166	0	8	0	0
T167	0	62	0	0
T168	0	6	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	990	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	15	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	23	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	61	0	0
T117	0	38	0	0
T118	0	15	0	0
T165	0	4	0	0
T166	0	3	0	0
T167	0	55	0	0
T168	0	7	0	0
T169	0	3	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1052	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	30	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	40	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	42	0	0
T117	0	36	0	0
T118	0	25	0	0
T165	0	10	0	0
T166	0	9	0	0
T167	0	79	0	0
T168	0	7	0	0
T170	0	2	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	916	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	19	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	25	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	54	0	0
T117	0	41	0	0
T118	0	8	0	0
T165	0	6	0	0
T166	0	9	0	0
T167	0	50	0	0
T169	0	7	0	0
T171	0	58	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	906	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	5	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	27	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	56	0	0
T117	0	27	0	0
T118	0	12	0	0
T165	0	9	0	0
T166	0	8	0	0
T167	0	81	0	0
T168	0	7	0	0
T169	0	1	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	897	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	17	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	29	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	29	0	0
T117	0	33	0	0
T118	0	12	0	0
T165	0	8	0	0
T166	0	10	0	0
T167	0	59	0	0
T168	0	1	0	0
T169	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	998	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	17	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	28	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	58	0	0
T117	0	34	0	0
T118	0	18	0	0
T165	0	18	0	0
T166	0	2	0	0
T167	0	77	0	0
T168	0	13	0	0
T170	0	7	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	974	0	0
T21	4870	0	0	0
T24	18551	0	0	0
T53	11367	0	0	0
T85	7027	0	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	33	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T109	2121	0	0	0
T114	0	56	0	0
T117	0	24	0	0
T118	0	7	0	0
T165	0	12	0	0
T167	0	75	0	0
T168	0	18	0	0
T169	0	2	0	0
T171	0	56	0	0
T174	0	22	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1010	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	22	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	29	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	55	0	0
T117	0	26	0	0
T118	0	6	0	0
T165	0	6	0	0
T166	0	9	0	0
T167	0	87	0	0
T168	0	9	0	0
T170	0	3	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	867	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	18	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	30	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	44	0	0
T117	0	25	0	0
T118	0	13	0	0
T165	0	7	0	0
T166	0	2	0	0
T167	0	85	0	0
T168	0	3	0	0
T171	0	47	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	985	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	6	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	10	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	44	0	0
T117	0	30	0	0
T118	0	37	0	0
T165	0	16	0	0
T166	0	12	0	0
T167	0	72	0	0
T168	0	9	0	0
T169	0	7	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	913	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	26	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	33	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	46	0	0
T117	0	43	0	0
T118	0	10	0	0
T165	0	4	0	0
T166	0	12	0	0
T167	0	62	0	0
T168	0	8	0	0
T169	0	4	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	921	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	35	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	21	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	36	0	0
T117	0	22	0	0
T118	0	21	0	0
T165	0	11	0	0
T166	0	2	0	0
T167	0	67	0	0
T168	0	5	0	0
T170	0	13	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	992	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	5	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	29	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	63	0	0
T117	0	42	0	0
T118	0	15	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	96	0	0
T168	0	8	0	0
T170	0	4	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	867	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	24	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	8	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	65	0	0
T117	0	37	0	0
T118	0	17	0	0
T165	0	7	0	0
T166	0	14	0	0
T167	0	53	0	0
T168	0	20	0	0
T171	0	29	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	1022	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	30	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	22	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	50	0	0
T117	0	12	0	0
T118	0	15	0	0
T165	0	3	0	0
T166	0	13	0	0
T167	0	64	0	0
T168	0	17	0	0
T169	0	15	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	854	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	19	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	16	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	55	0	0
T117	0	29	0	0
T118	0	27	0	0
T165	0	4	0	0
T166	0	6	0	0
T167	0	66	0	0
T168	0	10	0	0
T169	0	7	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	968	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	17	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	27	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	35	0	0
T117	0	28	0	0
T118	0	9	0	0
T165	0	6	0	0
T166	0	13	0	0
T167	0	69	0	0
T168	0	20	0	0
T169	0	12	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	903	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	2	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	23	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	61	0	0
T117	0	36	0	0
T118	0	10	0	0
T166	0	6	0	0
T167	0	56	0	0
T168	0	11	0	0
T169	0	3	0	0
T171	0	29	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32038991	868	0	0
T5	72699	0	0	0
T24	18551	0	0	0
T61	4996	0	0	0
T85	7027	0	0	0
T101	7275	7	0	0
T102	16477	0	0	0
T103	11913	0	0	0
T106	6032	11	0	0
T107	5485	0	0	0
T108	2114	0	0	0
T114	0	48	0	0
T117	0	16	0	0
T118	0	9	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	74	0	0
T168	0	4	0	0
T170	0	1	0	0