Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4233349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

567918

1

T1

420

T2

84

T3

182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4426055	1			T1	529		T2	4693		T3	616
values[0x0]	185968	1			T1	145		T2	34		T3	53
values[0x1]	189244	1			T1	175		T2	30		T3	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2875750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1925517

1

T1

516

T2

1656

T3

332

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15772	1			T1	1		T14	2		T15	3
valid_sources[0x01]	15732	1			T1	3		T3	2		T14	3
valid_sources[0x02]	33705	1			T1	6		T14	1		T15	1
valid_sources[0x03]	18462	1			T1	6		T15	3		T8	5
valid_sources[0x04]	18049	1			T3	2		T14	4		T15	2
valid_sources[0x05]	16266	1			T1	1		T3	7		T15	1
valid_sources[0x06]	15312	1			T3	7		T14	3		T15	2
valid_sources[0x07]	17391	1			T1	1		T3	2		T14	2
valid_sources[0x08]	16549	1			T1	2		T3	9		T14	2
valid_sources[0x09]	16340	1			T1	2		T3	1		T14	3
valid_sources[0x0a]	16604	1			T1	3		T3	9		T14	2
valid_sources[0x0b]	16142	1			T1	7		T3	3		T14	3
valid_sources[0x0c]	16069	1			T1	1		T14	2		T15	1
valid_sources[0x0d]	17124	1			T1	3		T3	1		T14	3
valid_sources[0x0e]	21201	1			T1	2		T14	4		T15	3
valid_sources[0x0f]	25967	1			T3	2		T14	5		T15	2
valid_sources[0x10]	18928	1			T1	1		T14	8		T15	3
valid_sources[0x11]	16292	1			T1	1		T3	2		T14	5
valid_sources[0x12]	16407	1			T1	10		T14	2		T15	4
valid_sources[0x13]	15913	1			T14	3		T15	3		T8	10
valid_sources[0x14]	19713	1			T1	2		T3	5		T14	3
valid_sources[0x15]	15726	1			T1	2		T3	7		T14	1
valid_sources[0x16]	19665	1			T1	11		T2	456		T3	2
valid_sources[0x17]	16009	1			T1	1		T14	1		T15	5
valid_sources[0x18]	19340	1			T1	6		T3	5		T14	3
valid_sources[0x19]	15710	1			T3	3		T8	3		T40	11
valid_sources[0x1a]	16986	1			T3	2		T15	1		T8	3
valid_sources[0x1b]	16968	1			T1	3		T14	2		T8	1
valid_sources[0x1c]	16250	1			T1	7		T3	1		T14	2
valid_sources[0x1d]	16225	1			T1	1		T3	5		T14	3
valid_sources[0x1e]	16147	1			T1	6		T3	1		T14	2
valid_sources[0x1f]	17458	1			T1	9		T14	3		T15	2
valid_sources[0x20]	16382	1			T1	2		T14	6		T8	6
valid_sources[0x21]	18566	1			T1	14		T3	6		T14	2
valid_sources[0x22]	16535	1			T1	2		T14	3		T8	5
valid_sources[0x23]	20843	1			T14	2		T15	1		T8	2
valid_sources[0x24]	15722	1			T1	1		T3	2		T14	1
valid_sources[0x25]	15837	1			T1	3		T3	5		T14	2
valid_sources[0x26]	18815	1			T14	1		T15	3		T8	3
valid_sources[0x27]	16368	1			T3	1		T15	1		T8	1
valid_sources[0x28]	17639	1			T3	3		T14	4		T15	16
valid_sources[0x29]	17753	1			T3	2		T15	2		T8	1
valid_sources[0x2a]	16617	1			T1	7		T14	1		T8	14
valid_sources[0x2b]	16812	1			T1	1		T3	2		T14	4
valid_sources[0x2c]	15942	1			T1	1		T3	5		T14	4
valid_sources[0x2d]	20893	1			T1	2		T2	4301		T3	2
valid_sources[0x2e]	16420	1			T1	3		T3	2		T14	2
valid_sources[0x2f]	15697	1			T3	8		T14	3		T8	3
valid_sources[0x30]	16552	1			T1	8		T3	1		T14	1
valid_sources[0x31]	15551	1			T1	3		T3	1		T14	2
valid_sources[0x32]	15977	1			T1	2		T14	5		T15	1
valid_sources[0x33]	19748	1			T1	3		T3	8		T14	2
valid_sources[0x34]	16553	1			T1	4		T3	2		T14	3
valid_sources[0x35]	15604	1			T3	1		T14	6		T8	5
valid_sources[0x36]	18328	1			T15	1		T8	4		T17	1
valid_sources[0x37]	43073	1			T3	7		T14	2		T15	1
valid_sources[0x38]	27045	1			T1	6		T3	1		T14	2
valid_sources[0x39]	16069	1			T1	3		T3	1		T14	3
valid_sources[0x3a]	17847	1			T14	2		T15	2		T8	3
valid_sources[0x3b]	19834	1			T8	3		T40	6		T24	10
valid_sources[0x3c]	32135	1			T1	2		T14	3		T8	3
valid_sources[0x3d]	22236	1			T1	6		T3	13		T14	1
valid_sources[0x3e]	16101	1			T1	8		T3	6		T14	2
valid_sources[0x3f]	17224	1			T1	2		T3	1		T14	5
valid_sources[0x40]	16014	1			T3	1		T14	3		T15	1
valid_sources[0x41]	16853	1			T1	2		T3	3		T14	1
valid_sources[0x42]	15968	1			T1	6		T3	2		T14	3
valid_sources[0x43]	16910	1			T1	1		T14	1		T15	2
valid_sources[0x44]	15931	1			T1	3		T14	3		T15	6
valid_sources[0x45]	17556	1			T3	3		T14	3		T15	4
valid_sources[0x46]	18496	1			T3	1		T14	4		T15	3
valid_sources[0x47]	35367	1			T1	5		T3	7		T14	2
valid_sources[0x48]	24628	1			T3	2		T14	2		T15	3
valid_sources[0x49]	23853	1			T1	9		T3	9		T14	3
valid_sources[0x4a]	15415	1			T1	4		T3	4		T14	1
valid_sources[0x4b]	18194	1			T1	3		T14	6		T15	3
valid_sources[0x4c]	16680	1			T1	3		T3	2		T14	4
valid_sources[0x4d]	17495	1			T1	5		T3	8		T14	2
valid_sources[0x4e]	16069	1			T3	2		T14	3		T8	8
valid_sources[0x4f]	15591	1			T1	2		T3	12		T14	2
valid_sources[0x50]	19939	1			T14	4		T15	1		T8	2
valid_sources[0x51]	17817	1			T14	1		T15	5		T8	1
valid_sources[0x52]	15904	1			T3	1		T14	2		T15	4
valid_sources[0x53]	16436	1			T3	3		T14	1		T15	4
valid_sources[0x54]	17611	1			T1	4		T3	13		T14	3
valid_sources[0x55]	27176	1			T1	5		T3	4		T14	3
valid_sources[0x56]	15339	1			T3	5		T14	4		T15	1
valid_sources[0x57]	16881	1			T3	3		T14	2		T15	3
valid_sources[0x58]	16233	1			T1	4		T3	6		T14	3
valid_sources[0x59]	17329	1			T14	7		T15	1		T8	7
valid_sources[0x5a]	16874	1			T1	6		T3	2		T14	4
valid_sources[0x5b]	15672	1			T1	8		T14	1		T15	1
valid_sources[0x5c]	16210	1			T1	6		T3	3		T14	1
valid_sources[0x5d]	18518	1			T1	3		T3	3		T14	1
valid_sources[0x5e]	16636	1			T1	15		T3	1		T14	5
valid_sources[0x5f]	16522	1			T3	4		T14	3		T8	4
valid_sources[0x60]	15561	1			T1	3		T14	4		T8	1
valid_sources[0x61]	17473	1			T1	4		T3	3		T14	4
valid_sources[0x62]	16653	1			T1	1		T3	8		T14	1
valid_sources[0x63]	16014	1			T1	10		T3	9		T14	1
valid_sources[0x64]	16763	1			T1	4		T3	5		T14	2
valid_sources[0x65]	34944	1			T3	5		T4	18573		T14	2
valid_sources[0x66]	26974	1			T1	8		T14	2		T15	1
valid_sources[0x67]	17849	1			T3	5		T14	1		T15	6
valid_sources[0x68]	15703	1			T1	1		T14	4		T15	6
valid_sources[0x69]	15891	1			T14	1		T15	2		T8	3
valid_sources[0x6a]	16064	1			T1	5		T3	1		T14	3
valid_sources[0x6b]	17299	1			T1	5		T3	2		T14	2
valid_sources[0x6c]	15436	1			T1	15		T3	2		T14	3
valid_sources[0x6d]	15905	1			T1	3		T14	4		T8	3
valid_sources[0x6e]	16004	1			T1	4		T3	5		T14	2
valid_sources[0x6f]	16981	1			T1	1		T3	4		T14	2
valid_sources[0x70]	21689	1			T1	3		T14	3		T15	3
valid_sources[0x71]	33583	1			T1	6		T14	2		T15	6
valid_sources[0x72]	17805	1			T14	3		T15	3		T8	5
valid_sources[0x73]	15959	1			T1	4		T15	1		T8	3
valid_sources[0x74]	20500	1			T1	2		T3	1		T14	2
valid_sources[0x75]	15967	1			T3	1		T14	1		T8	5
valid_sources[0x76]	37186	1			T3	1		T14	3		T15	4
valid_sources[0x77]	16321	1			T1	1		T8	6		T17	1
valid_sources[0x78]	27139	1			T14	3		T8	2		T17	2
valid_sources[0x79]	70236	1			T1	1		T3	2		T8	6
valid_sources[0x7a]	15444	1			T1	5		T3	2		T14	5
valid_sources[0x7b]	76176	1			T3	2		T14	3		T15	1
valid_sources[0x7c]	16133	1			T14	6		T15	2		T8	3
valid_sources[0x7d]	16258	1			T3	4		T14	5		T8	5
valid_sources[0x7e]	17689	1			T3	9		T15	1		T8	5
valid_sources[0x7f]	15483	1			T1	3		T3	6		T14	1
valid_sources[0x80]	17055	1			T1	10		T14	4		T8	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

312014

1

T1

210

T2

62

T3

145

values[0x0]

all_enables

biggest_size

134525

1

T1

104

T2

15

T3

28

values[0x1]

all_enables

biggest_size

121379

1

T1

106

T2

7

T3

9