Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
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Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

34 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_0.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_1.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_2.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_3.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_4.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_5.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_6.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_7.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.control_shadowed.cdi_sel 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.control_shadowed.dest_sel 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.control_shadowed.operation 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.key_version.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.max_creator_key_ver_shadowed.val 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.max_owner_int_key_ver_shadowed.val 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.max_owner_key_ver_shadowed.val 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.reseed_interval_shadowed.val 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_0.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_1.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_2.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_3.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_4.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_5.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_6.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.salt_7.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_0.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_1.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_2.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_3.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_4.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_5.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_6.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_7.val_0 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.sideload_clear.val 100.00 1 100 1 64 64
lockable_field_cov_of_keymgr_reg_block.start.en 100.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_0.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_0.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_0.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_1.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_1.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_1.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_2.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_2.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_2.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_3.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_3.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_3.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_4.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_4.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_4.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_5.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_5.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_5.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_6.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_6.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_6.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_7.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_7.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.attest_sw_binding_7.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.control_shadowed.cdi_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.cdi_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.cdi_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.control_shadowed.dest_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.dest_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.dest_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.control_shadowed.operation
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.operation

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.control_shadowed.operation
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.key_version.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.key_version.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.key_version.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.max_creator_key_ver_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.max_creator_key_ver_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.max_creator_key_ver_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.max_owner_int_key_ver_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.max_owner_int_key_ver_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.max_owner_int_key_ver_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.max_owner_key_ver_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.max_owner_key_ver_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.max_owner_key_ver_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.reseed_interval_shadowed.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.reseed_interval_shadowed.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.reseed_interval_shadowed.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_0.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_0.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_0.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_1.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_1.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_1.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_2.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_2.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_2.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_3.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_3.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_3.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_4.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_4.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_4.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_5.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_5.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_5.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_6.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_6.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_6.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.salt_7.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_7.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.salt_7.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_0.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_0.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_0.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_1.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_1.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_1.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_2.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_2.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_2.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_3.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_3.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_3.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_4.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_4.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_4.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_5.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_5.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_5.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_6.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_6.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_6.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_7.val_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_7.val_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sealing_sw_binding_7.val_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.sideload_clear.val
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.sideload_clear.val

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.sideload_clear.val
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_keymgr_reg_block.start.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_keymgr_reg_block.start.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_keymgr_reg_block.start.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 496 1 T107 9 T124 2 T108 14
auto[1] 712 1 T107 16 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 494 1 T107 11 T124 3 T108 15
auto[1] 722 1 T107 14 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 474 1 T107 8 T124 4 T108 15
auto[1] 683 1 T107 17 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 510 1 T107 9 T124 2 T135 64
auto[1] 629 1 T107 16 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 431 1 T107 9 T124 3 T108 15
auto[1] 894 1 T105 1 T107 16 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 477 1 T107 12 T124 5 T108 17
auto[1] 729 1 T107 13 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 475 1 T107 10 T124 4 T135 64
auto[1] 732 1 T107 15 T171 1 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 480 1 T107 12 T124 3 T108 16
auto[1] 772 1 T107 13 T171 1 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 785 1 T75 4 T77 20 T79 24
auto[1] 495 1 T79 1 T107 5 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 799 1 T75 4 T77 19 T79 25
auto[1] 713 1 T107 5 T134 1 T124 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 812 1 T75 4 T77 20 T79 25
auto[1] 864 1 T107 5 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 274 1 T75 1 T77 8 T79 11
auto[1] 1251 1 T107 25 T171 1 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 194 1 T107 2 T124 6 T137 1
auto[1] 647 1 T107 2 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295 1 T107 5 T124 5 T135 64
auto[1] 533 1 T107 1 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306 1 T107 6 T139 1 T124 6
auto[1] 531 1 T134 1 T124 14 T136 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 282 1 T107 2 T124 5 T136 1
auto[1] 670 1 T107 3 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 269 1 T77 5 T79 6 T221 7
auto[1] 1301 1 T107 25 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 293 1 T75 2 T77 8 T79 9
auto[1] 1166 1 T105 1 T107 25 T171 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 283 1 T75 3 T77 5 T79 11
auto[1] 1303 1 T107 25 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 248 1 T75 2 T77 6 T79 2
auto[1] 1168 1 T107 25 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T75 1 T77 6 T79 6
auto[1] 1225 1 T107 25 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 281 1 T75 3 T77 8 T79 7
auto[1] 1273 1 T75 1 T105 2 T107 25


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 266 1 T75 3 T77 9 T79 15
auto[1] 1289 1 T107 25 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 258 1 T75 3 T77 12 T79 4
auto[1] 1248 1 T105 1 T107 25 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 407 1 T107 9 T124 3 T137 1
auto[1] 835 1 T107 16 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 487 1 T107 11 T124 3 T108 17
auto[1] 809 1 T107 14 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 486 1 T107 11 T124 2 T137 1
auto[1] 759 1 T107 14 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 486 1 T107 10 T124 3 T108 17
auto[1] 787 1 T107 15 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 473 1 T107 10 T124 5 T137 1
auto[1] 729 1 T105 1 T107 15 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 499 1 T107 11 T124 4 T108 14
auto[1] 752 1 T107 14 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 409 1 T107 12 T124 4 T137 1
auto[1] 879 1 T107 13 T171 1 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 476 1 T107 10 T124 2 T108 15
auto[1] 759 1 T107 15 T171 1 T139 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T75 1 T77 7 T79 9
auto[1] 1091 1 T107 24 T139 1 T134 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 251 1 T77 9 T79 8 T221 7
auto[1] 18 1 T77 1 T79 1 T252 1

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