Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	96.15	98.39	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	29707915	17268	0	0
attest_sw_binding_0_rd_A	29707915	1030	0	0
attest_sw_binding_1_rd_A	29707915	1112	0	0
attest_sw_binding_2_rd_A	29707915	1225	0	0
attest_sw_binding_3_rd_A	29707915	1194	0	0
attest_sw_binding_4_rd_A	29707915	1101	0	0
attest_sw_binding_5_rd_A	29707915	1275	0	0
attest_sw_binding_6_rd_A	29707915	1224	0	0
attest_sw_binding_7_rd_A	29707915	1260	0	0
intr_enable_rd_A	29707915	1691	0	0
key_version_rd_A	29707915	1105	0	0
max_creator_key_ver_regwen_rd_A	29707915	1214	0	0
max_owner_int_key_ver_regwen_rd_A	29707915	1174	0	0
max_owner_key_ver_regwen_rd_A	29707915	1178	0	0
reseed_interval_regwen_rd_A	29707915	1111	0	0
salt_0_rd_A	29707915	1269	0	0
salt_1_rd_A	29707915	1167	0	0
salt_2_rd_A	29707915	1200	0	0
salt_3_rd_A	29707915	1229	0	0
salt_4_rd_A	29707915	1147	0	0
salt_5_rd_A	29707915	1180	0	0
salt_6_rd_A	29707915	1175	0	0
salt_7_rd_A	29707915	1237	0	0
sealing_sw_binding_0_rd_A	29707915	1143	0	0
sealing_sw_binding_1_rd_A	29707915	1161	0	0
sealing_sw_binding_2_rd_A	29707915	1109	0	0
sealing_sw_binding_3_rd_A	29707915	1255	0	0
sealing_sw_binding_4_rd_A	29707915	1186	0	0
sealing_sw_binding_5_rd_A	29707915	1156	0	0
sealing_sw_binding_6_rd_A	29707915	1142	0	0
sealing_sw_binding_7_rd_A	29707915	1220	0	0
sideload_clear_rd_A	29707915	1185	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	17268	0	0
T29	6533	0	0	0
T35	11315	0	0	0
T37	20390	0	0	0
T50	30165	0	0	0
T81	8401	6	0	0
T89	21981	0	0	0
T92	7779	0	0	0
T103	5537	197	0	0
T104	0	141	0	0
T105	0	93	0	0
T106	0	187	0	0
T110	0	183	0	0
T116	0	4	0	0
T117	0	485	0	0
T121	7388	0	0	0
T122	6727	0	0	0
T171	0	3	0	0
T172	0	2	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1030	0	0
T35	11315	0	0	0
T81	8401	34	0	0
T104	14356	13	0	0
T106	6235	10	0	0
T113	0	33	0	0
T116	2004	6	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	6	0	0
T172	0	7	0	0
T173	0	10	0	0
T174	0	11	0	0
T175	0	217	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1112	0	0
T35	11315	0	0	0
T81	8401	28	0	0
T104	14356	17	0	0
T106	6235	12	0	0
T113	0	36	0	0
T116	2004	5	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	6	0	0
T141	2927	0	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	3	0	0
T175	0	226	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1225	0	0
T35	11315	0	0	0
T81	8401	17	0	0
T104	14356	18	0	0
T106	6235	6	0	0
T113	0	31	0	0
T116	2004	1	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	4	0	0
T172	0	6	0	0
T173	0	7	0	0
T174	0	9	0	0
T175	0	243	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1194	0	0
T35	11315	0	0	0
T81	8401	20	0	0
T104	14356	20	0	0
T106	6235	2	0	0
T113	0	48	0	0
T116	2004	2	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	9	0	0
T173	0	18	0	0
T174	0	33	0	0
T175	0	256	0	0
T176	0	15	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1101	0	0
T35	11315	0	0	0
T81	8401	23	0	0
T104	14356	14	0	0
T113	0	34	0	0
T116	2004	7	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	8	0	0
T172	2137	2	0	0
T173	0	13	0	0
T174	0	15	0	0
T175	0	192	0	0
T176	0	37	0	0
T177	2336	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1275	0	0
T35	11315	0	0	0
T81	8401	23	0	0
T104	14356	11	0	0
T113	0	32	0	0
T116	2004	6	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	2	0	0
T139	1807	5	0	0
T172	2137	16	0	0
T173	0	6	0	0
T174	0	11	0	0
T175	0	262	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1224	0	0
T35	11315	0	0	0
T81	8401	24	0	0
T104	14356	16	0	0
T106	6235	5	0	0
T113	0	39	0	0
T116	2004	16	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	6	0	0
T172	0	2	0	0
T173	0	11	0	0
T174	0	6	0	0
T175	0	245	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1260	0	0
T35	11315	0	0	0
T81	8401	27	0	0
T104	14356	1	0	0
T113	0	48	0	0
T116	2004	6	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	5	0	0
T172	2137	8	0	0
T173	0	3	0	0
T174	0	12	0	0
T175	0	220	0	0
T176	0	16	0	0
T177	2336	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1691	0	0
T35	11315	0	0	0
T81	8401	32	0	0
T104	14356	14	0	0
T106	0	3	0	0
T116	2004	8	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	10	0	0
T139	1807	2	0	0
T140	1320	2	0	0
T172	0	4	0	0
T178	1142	25	0	0
T179	0	6	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1105	0	0
T35	11315	0	0	0
T81	8401	32	0	0
T104	14356	7	0	0
T113	0	54	0	0
T116	2004	6	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	3	0	0
T172	2137	2	0	0
T173	0	4	0	0
T174	0	11	0	0
T175	0	271	0	0
T176	0	9	0	0
T177	2336	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1214	0	0
T35	11315	0	0	0
T81	8401	35	0	0
T104	14356	7	0	0
T113	0	36	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	15	0	0
T139	1807	6	0	0
T172	2137	0	0	0
T173	0	10	0	0
T174	0	12	0	0
T175	0	219	0	0
T176	0	8	0	0
T177	2336	0	0	0
T180	0	56	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1174	0	0
T35	11315	0	0	0
T81	8401	20	0	0
T104	14356	19	0	0
T113	0	38	0	0
T116	2004	2	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	1	0	0
T139	1807	6	0	0
T172	2137	4	0	0
T173	0	15	0	0
T174	0	17	0	0
T175	0	227	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1178	0	0
T35	11315	0	0	0
T81	8401	25	0	0
T104	14356	9	0	0
T106	6235	6	0	0
T113	0	43	0	0
T116	2004	5	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	2	0	0
T172	0	10	0	0
T173	0	15	0	0
T174	0	13	0	0
T175	0	228	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1111	0	0
T35	11315	0	0	0
T81	8401	30	0	0
T104	14356	19	0	0
T106	6235	11	0	0
T113	0	34	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T135	12868	0	0	0
T136	0	1	0	0
T141	2927	0	0	0
T172	0	2	0	0
T173	0	9	0	0
T174	0	10	0	0
T175	0	236	0	0
T176	0	7	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1269	0	0
T35	11315	0	0	0
T81	8401	24	0	0
T104	14356	11	0	0
T113	0	44	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	3	0	0
T139	1807	2	0	0
T172	2137	9	0	0
T173	0	12	0	0
T174	0	18	0	0
T175	0	227	0	0
T176	0	3	0	0
T177	2336	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1167	0	0
T35	11315	0	0	0
T81	8401	32	0	0
T104	14356	5	0	0
T113	0	21	0	0
T116	2004	3	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	7	0	0
T139	1807	3	0	0
T172	2137	5	0	0
T173	0	7	0	0
T174	0	17	0	0
T175	0	261	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1200	0	0
T35	11315	0	0	0
T81	8401	9	0	0
T104	14356	31	0	0
T106	6235	11	0	0
T113	0	32	0	0
T116	2004	8	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	1	0	0
T139	1807	2	0	0
T172	0	8	0	0
T173	0	12	0	0
T174	0	8	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1229	0	0
T35	11315	0	0	0
T81	8401	30	0	0
T104	14356	14	0	0
T106	6235	15	0	0
T113	0	42	0	0
T116	2004	13	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	2	0	0
T173	0	9	0	0
T174	0	17	0	0
T175	0	237	0	0
T176	0	14	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1147	0	0
T35	11315	0	0	0
T81	8401	26	0	0
T104	14356	18	0	0
T113	0	31	0	0
T116	2004	2	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	1	0	0
T139	1807	7	0	0
T172	2137	0	0	0
T173	0	12	0	0
T174	0	3	0	0
T175	0	260	0	0
T180	0	29	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1180	0	0
T35	11315	0	0	0
T81	8401	16	0	0
T104	14356	10	0	0
T106	6235	12	0	0
T113	0	30	0	0
T116	2004	3	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	3	0	0
T139	1807	8	0	0
T172	0	7	0	0
T173	0	10	0	0
T174	0	15	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1175	0	0
T35	11315	0	0	0
T81	8401	31	0	0
T104	14356	10	0	0
T106	6235	5	0	0
T113	0	37	0	0
T116	2004	7	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	6	0	0
T139	1807	2	0	0
T172	0	7	0	0
T173	0	6	0	0
T174	0	25	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1237	0	0
T35	11315	0	0	0
T81	8401	13	0	0
T104	14356	16	0	0
T113	0	38	0	0
T116	2004	6	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	2	0	0
T139	1807	6	0	0
T172	2137	5	0	0
T173	0	5	0	0
T174	0	28	0	0
T175	0	265	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1143	0	0
T35	11315	0	0	0
T81	8401	27	0	0
T104	14356	24	0	0
T106	6235	8	0	0
T113	0	28	0	0
T116	2004	9	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	8	0	0
T139	1807	8	0	0
T173	0	9	0	0
T174	0	17	0	0
T175	0	218	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1161	0	0
T35	11315	0	0	0
T81	8401	21	0	0
T104	14356	27	0	0
T106	6235	3	0	0
T113	0	36	0	0
T116	2004	4	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	15	0	0
T139	1807	2	0	0
T172	0	7	0	0
T173	0	7	0	0
T174	0	14	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1109	0	0
T35	11315	0	0	0
T81	8401	14	0	0
T104	14356	17	0	0
T106	6235	8	0	0
T113	0	40	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	8	0	0
T139	1807	4	0	0
T141	2927	0	0	0
T172	0	5	0	0
T173	0	13	0	0
T174	0	12	0	0
T175	0	253	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1255	0	0
T35	11315	0	0	0
T81	8401	23	0	0
T104	14356	25	0	0
T113	0	32	0	0
T116	2004	2	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	10	0	0
T139	1807	1	0	0
T172	2137	5	0	0
T173	0	7	0	0
T174	0	20	0	0
T175	0	249	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1186	0	0
T35	11315	0	0	0
T81	8401	22	0	0
T104	14356	14	0	0
T113	0	47	0	0
T116	2004	4	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	2	0	0
T139	1807	1	0	0
T172	2137	7	0	0
T173	0	13	0	0
T174	0	10	0	0
T175	0	262	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1156	0	0
T35	11315	0	0	0
T81	8401	30	0	0
T104	14356	10	0	0
T113	0	35	0	0
T116	2004	1	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	3	0	0
T172	2137	4	0	0
T173	0	3	0	0
T174	0	6	0	0
T175	0	198	0	0
T176	0	6	0	0
T177	2336	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1142	0	0
T35	11315	0	0	0
T81	8401	26	0	0
T104	14356	21	0	0
T113	0	42	0	0
T116	2004	9	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	2899	1	0	0
T139	1807	5	0	0
T172	2137	4	0	0
T173	0	6	0	0
T174	0	10	0	0
T175	0	228	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1220	0	0
T35	11315	0	0	0
T81	8401	23	0	0
T104	14356	18	0	0
T106	6235	7	0	0
T113	0	30	0	0
T123	19970	0	0	0
T124	10202	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T136	0	6	0	0
T139	1807	7	0	0
T141	2927	0	0	0
T172	0	5	0	0
T173	0	8	0	0
T174	0	17	0	0
T175	0	220	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	29707915	1185	0	0
T35	11315	0	0	0
T81	8401	34	0	0
T104	14356	9	0	0
T113	0	32	0	0
T116	2004	8	0	0
T123	19970	0	0	0
T132	25925	0	0	0
T133	5321	0	0	0
T139	1807	1	0	0
T172	2137	9	0	0
T173	0	10	0	0
T174	0	14	0	0
T175	0	227	0	0
T177	2336	0	0	0
T180	0	40	0	0