Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11361

1

T1

14

T2

7

T3

6

auto[Attestation]

7719

1

T1

8

T2

4

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2828	1			T1	5		T2	2		T3	3
auto[Aes]	3516	1			T1	3		T2	2		T4	3
auto[Kmac]	3335	1			T1	2		T2	3		T14	28
auto[Otbn]	3348	1			T1	1		T2	1		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7582	1			T1	8		T2	4		T3	8
auto[OpGenId]	6053	1			T1	11		T2	3		T3	3
auto[OpGenSwOut]	5883	1			T1	11		T2	2		T3	5
auto[OpGenHwOut]	7144	1			T2	6		T4	4		T5	10
auto[OpDisable]	131	1			T4	1		T14	2		T18	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9834

1

T1

8

T2

12

T3

8

auto[OpDoneFail]

16959

1

T1

22

T2

3

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6602	1			T1	15		T2	1		T3	1
auto[StInit]	4118	1			T1	2		T2	4		T3	2
auto[StCreatorRootKey]	2953	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2575	1			T1	2		T2	4		T3	2
auto[StOwnerKey]	2180	1			T1	2		T2	4		T3	2
auto[StDisabled]	7284	1			T1	7		T3	7		T4	1
auto[StInvalid]	1081	1			T16	31		T28	28		T68	25

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	322	1			T1	3		T14	5		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	112	1			T2	1		T37	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T14	2		T37	2		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T14	2		T131	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	43	1			T3	1		T139	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	200	1			T3	2		T14	2		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T16	1		T28	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	354	1			T1	2		T14	4		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T14	1		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	79	1			T18	1		T138	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	65	1			T29	1		T59	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T14	1		T29	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T29	3		T51	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T26	2		T185	2		T84	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	315	1			T1	1		T14	3		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T29	1		T24	3		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T2	1		T14	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T14	1		T81	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	47	1			T186	1		T56	1		T187	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	153	1			T14	2		T79	1		T29	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	21	1			T98	1		T188	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	334	1			T1	1		T14	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	98	1			T14	1		T39	1		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T14	1		T32	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T183	1		T139	1		T65	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	54	1			T14	2		T104	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	193	1			T3	1		T14	3		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	24	1			T16	1		T68	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	68	1			T14	2		T29	2		T56	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	132	1			T14	1		T36	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T14	1		T29	3		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T14	3		T32	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T1	1		T14	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	196	1			T1	1		T14	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T16	1		T28	2		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	76	1			T14	2		T29	3		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T14	2		T29	3		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T79	1		T81	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	59	1			T29	1		T32	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T48	1		T191	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	210	1			T1	1		T14	2		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	43	1			T16	1		T28	2		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	87	1			T14	3		T29	2		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	97	1			T1	1		T14	3		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T14	1		T102	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T29	1		T192	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	44	1			T32	1		T184	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	166	1			T14	3		T29	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	36	1			T16	1		T28	2		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	87	1			T14	6		T29	2		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	107	1			T36	1		T80	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	83	1			T14	1		T79	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T3	1		T29	3		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T29	1		T48	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	191	1			T14	1		T81	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T16	2		T26	2		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	284	1			T79	1		T104	2		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	115	1			T104	1		T24	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T79	1		T104	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T14	1		T32	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	44	1			T137	1		T189	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	184	1			T14	4		T80	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	35	1			T16	3		T185	2		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	495	1			T14	1		T82	8		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	127	1			T82	1		T24	2		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T4	1		T14	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T18	1		T29	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	81	1			T2	1		T82	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T14	1		T82	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T68	1		T26	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	478	1			T15	12		T79	2		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T15	1		T36	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T14	1		T29	2		T132	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T14	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T2	1		T15	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	298	1			T14	2		T15	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T68	1		T188	1		T193	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	437	1			T5	2		T79	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T24	1		T48	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T5	1		T18	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T2	1		T5	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	84	1			T5	1		T14	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	264	1			T5	1		T14	3		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	25	1			T16	1		T28	2		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	63	1			T14	1		T29	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	128	1			T2	1		T18	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T14	1		T32	1		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	52	1			T14	1		T137	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T4	1		T29	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	160	1			T14	2		T79	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	43	1			T16	2		T28	1		T68	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T14	3		T29	1		T56	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	138	1			T2	1		T4	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	105	1			T36	3		T104	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T14	2		T82	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	77	1			T4	1		T48	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	264	1			T14	3		T82	2		T29	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	34	1			T28	2		T68	2		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	65	1			T14	3		T29	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	121	1			T14	1		T104	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T14	1		T15	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T2	1		T32	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	75	1			T131	1		T32	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	267	1			T14	2		T15	3		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T28	2		T25	1		T198	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	51	1			T29	1		T56	6		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T5	1		T16	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T18	1		T37	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T14	1		T37	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T138	1		T183	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	276	1			T5	3		T14	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T16	1		T68	1		T26	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	176	1			T3	1		T14	4		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	671	1			T1	3		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	185	1			T14	1		T18	1		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	725	1			T1	2		T14	5		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T2	1		T14	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	609	1			T1	1		T14	6		T79	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T14	3		T104	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	667	1			T1	1		T3	1		T14	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	179	1			T1	1		T14	5		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	437	1			T1	1		T14	4		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	173	1			T79	1		T81	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T1	1		T14	6		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	187	1			T14	1		T29	1		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	395	1			T1	1		T14	9		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T3	1		T14	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	446	1			T14	7		T16	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	172	1			T14	1		T79	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	628	1			T14	4		T16	3		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	263	1			T2	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	946	1			T14	2		T82	11		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	251	1			T2	1		T14	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	947	1			T14	2		T15	14		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	259	1			T2	1		T5	3		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	853	1			T5	3		T14	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	158	1			T4	1		T14	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	407	1			T2	1		T14	4		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	260	1			T4	1		T14	2		T36	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	505	1			T2	1		T4	1		T14	6
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	246	1			T2	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	496	1			T14	6		T15	3		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	268	1			T14	1		T18	1		T37	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	485	1			T5	4		T14	1		T16	2