Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 0 5 100.00
Crosses 4 0 4 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr_pin 1 0 1 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 4 0 4 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 53769 1 T1 61 T2 15 T3 33


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x0] 43122 1 T1 61 T3 33 T4 25
values[0x1] 10647 1 T2 15 T5 16 T14 119
transitions[0x0=>0x1] 9010 1 T5 16 T14 119 T15 16
transitions[0x1=>0x0] 9147 1 T5 16 T14 119 T15 16


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pin   cp_intr_pin_value   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] values[0x0] 43122 1 T1 61 T3 33 T4 25
all_pins[0] values[0x1] 10647 1 T2 15 T5 16 T14 119
all_pins[0] transitions[0x0=>0x1] 9010 1 T5 16 T14 119 T15 16
all_pins[0] transitions[0x1=>0x0] 9147 1 T5 16 T14 119 T15 16