Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30735

1

T1

34

T2

17

T3

21

auto[1]

277

1

T122

3

T138

9

T139

16

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30744	1			T1	34		T2	17		T3	21
auto[134217728:268435455]	9	1			T122	1		T138	1		T139	1
auto[268435456:402653183]	7	1			T225	1		T107	1		T399	1
auto[402653184:536870911]	11	1			T139	2		T107	1		T247	1
auto[536870912:671088639]	12	1			T139	1		T225	1		T354	1
auto[671088640:805306367]	5	1			T138	1		T107	1		T247	1
auto[805306368:939524095]	8	1			T247	1		T332	1		T354	1
auto[939524096:1073741823]	6	1			T332	1		T297	1		T229	1
auto[1073741824:1207959551]	7	1			T400	1		T332	1		T350	1
auto[1207959552:1342177279]	11	1			T139	1		T223	1		T107	1
auto[1342177280:1476395007]	8	1			T107	1		T330	1		T401	1
auto[1476395008:1610612735]	9	1			T350	1		T402	1		T403	1
auto[1610612736:1744830463]	4	1			T404	1		T265	1		T405	1
auto[1744830464:1879048191]	7	1			T139	2		T225	1		T247	1
auto[1879048192:2013265919]	8	1			T321	2		T380	1		T373	2
auto[2013265920:2147483647]	10	1			T138	1		T223	1		T321	1
auto[2147483648:2281701375]	5	1			T138	1		T223	1		T403	1
auto[2281701376:2415919103]	7	1			T107	2		T400	1		T297	1
auto[2415919104:2550136831]	10	1			T139	1		T223	1		T247	1
auto[2550136832:2684354559]	6	1			T139	2		T223	1		T350	1
auto[2684354560:2818572287]	10	1			T139	1		T223	1		T332	1
auto[2818572288:2952790015]	9	1			T138	1		T107	1		T340	1
auto[2952790016:3087007743]	14	1			T139	1		T225	1		T107	1
auto[3087007744:3221225471]	7	1			T138	1		T225	1		T340	1
auto[3221225472:3355443199]	11	1			T122	1		T138	1		T225	1
auto[3355443200:3489660927]	10	1			T139	1		T247	1		T400	1
auto[3489660928:3623878655]	9	1			T122	1		T223	1		T406	1
auto[3623878656:3758096383]	7	1			T223	1		T107	1		T400	1
auto[3758096384:3892314111]	16	1			T138	1		T223	1		T247	2
auto[3892314112:4026531839]	6	1			T139	1		T223	1		T225	1
auto[4026531840:4160749567]	12	1			T139	2		T222	1		T340	1
auto[4160749568:4294967295]	7	1			T138	1		T107	1		T332	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30735	1			T1	34		T2	17		T3	21
auto[0:134217727]	auto[1]	9	1			T223	1		T400	1		T380	2
auto[134217728:268435455]	auto[1]	9	1			T122	1		T138	1		T139	1
auto[268435456:402653183]	auto[1]	7	1			T225	1		T107	1		T399	1
auto[402653184:536870911]	auto[1]	11	1			T139	2		T107	1		T247	1
auto[536870912:671088639]	auto[1]	12	1			T139	1		T225	1		T354	1
auto[671088640:805306367]	auto[1]	5	1			T138	1		T107	1		T247	1
auto[805306368:939524095]	auto[1]	8	1			T247	1		T332	1		T354	1
auto[939524096:1073741823]	auto[1]	6	1			T332	1		T297	1		T229	1
auto[1073741824:1207959551]	auto[1]	7	1			T400	1		T332	1		T350	1
auto[1207959552:1342177279]	auto[1]	11	1			T139	1		T223	1		T107	1
auto[1342177280:1476395007]	auto[1]	8	1			T107	1		T330	1		T401	1
auto[1476395008:1610612735]	auto[1]	9	1			T350	1		T402	1		T403	1
auto[1610612736:1744830463]	auto[1]	4	1			T404	1		T265	1		T405	1
auto[1744830464:1879048191]	auto[1]	7	1			T139	2		T225	1		T247	1
auto[1879048192:2013265919]	auto[1]	8	1			T321	2		T380	1		T373	2
auto[2013265920:2147483647]	auto[1]	10	1			T138	1		T223	1		T321	1
auto[2147483648:2281701375]	auto[1]	5	1			T138	1		T223	1		T403	1
auto[2281701376:2415919103]	auto[1]	7	1			T107	2		T400	1		T297	1
auto[2415919104:2550136831]	auto[1]	10	1			T139	1		T223	1		T247	1
auto[2550136832:2684354559]	auto[1]	6	1			T139	2		T223	1		T350	1
auto[2684354560:2818572287]	auto[1]	10	1			T139	1		T223	1		T332	1
auto[2818572288:2952790015]	auto[1]	9	1			T138	1		T107	1		T340	1
auto[2952790016:3087007743]	auto[1]	14	1			T139	1		T225	1		T107	1
auto[3087007744:3221225471]	auto[1]	7	1			T138	1		T225	1		T340	1
auto[3221225472:3355443199]	auto[1]	11	1			T122	1		T138	1		T225	1
auto[3355443200:3489660927]	auto[1]	10	1			T139	1		T247	1		T400	1
auto[3489660928:3623878655]	auto[1]	9	1			T122	1		T223	1		T406	1
auto[3623878656:3758096383]	auto[1]	7	1			T223	1		T107	1		T400	1
auto[3758096384:3892314111]	auto[1]	16	1			T138	1		T223	1		T247	2
auto[3892314112:4026531839]	auto[1]	6	1			T139	1		T223	1		T225	1
auto[4026531840:4160749567]	auto[1]	12	1			T139	2		T222	1		T340	1
auto[4160749568:4294967295]	auto[1]	7	1			T138	1		T107	1		T332	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1540

1

T4

2

T14

9

T16

3

auto[1]

1647

1

T4

1

T14

12

T18

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T14	1		T16	1		T48	1
auto[134217728:268435455]	98	1			T28	1		T184	1		T281	1
auto[268435456:402653183]	106	1			T68	1		T29	2		T51	1
auto[402653184:536870911]	85	1			T16	1		T137	1		T48	1
auto[536870912:671088639]	100	1			T14	1		T79	1		T29	1
auto[671088640:805306367]	106	1			T48	1		T64	2		T25	1
auto[805306368:939524095]	86	1			T14	1		T36	1		T29	2
auto[939524096:1073741823]	81	1			T79	1		T102	1		T48	2
auto[1073741824:1207959551]	94	1			T79	2		T58	1		T19	1
auto[1207959552:1342177279]	100	1			T14	2		T104	1		T68	1
auto[1342177280:1476395007]	96	1			T14	2		T79	1		T104	1
auto[1476395008:1610612735]	106	1			T28	1		T104	1		T29	1
auto[1610612736:1744830463]	78	1			T4	1		T14	1		T184	1
auto[1744830464:1879048191]	90	1			T14	1		T29	1		T48	2
auto[1879048192:2013265919]	105	1			T14	2		T79	1		T64	2
auto[2013265920:2147483647]	93	1			T104	1		T32	1		T102	1
auto[2147483648:2281701375]	94	1			T4	2		T14	1		T48	2
auto[2281701376:2415919103]	108	1			T16	1		T32	1		T20	1
auto[2415919104:2550136831]	99	1			T14	2		T29	3		T48	2
auto[2550136832:2684354559]	109	1			T51	1		T102	1		T184	2
auto[2684354560:2818572287]	103	1			T68	1		T29	1		T24	1
auto[2818572288:2952790015]	106	1			T79	1		T51	1		T64	1
auto[2952790016:3087007743]	100	1			T14	1		T29	2		T183	1
auto[3087007744:3221225471]	101	1			T29	2		T48	1		T189	1
auto[3221225472:3355443199]	100	1			T14	1		T104	1		T68	1
auto[3355443200:3489660927]	108	1			T14	1		T64	1		T25	1
auto[3489660928:3623878655]	101	1			T14	1		T104	1		T29	1
auto[3623878656:3758096383]	126	1			T14	1		T79	1		T28	1
auto[3758096384:3892314111]	103	1			T68	1		T102	1		T137	1
auto[3892314112:4026531839]	105	1			T36	1		T28	1		T48	2
auto[4026531840:4160749567]	102	1			T18	1		T101	1		T48	1
auto[4160749568:4294967295]	106	1			T14	2		T18	1		T68	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35	1			T14	1		T16	1		T43	1
auto[0:134217727]	auto[1]	57	1			T48	1		T26	1		T138	1
auto[134217728:268435455]	auto[0]	52	1			T28	1		T184	1		T281	1
auto[134217728:268435455]	auto[1]	46	1			T76	1		T69	1		T223	1
auto[268435456:402653183]	auto[0]	48	1			T68	1		T29	2		T7	1
auto[268435456:402653183]	auto[1]	58	1			T51	1		T138	1		T182	1
auto[402653184:536870911]	auto[0]	39	1			T16	1		T48	1		T7	1
auto[402653184:536870911]	auto[1]	46	1			T137	1		T206	1		T244	1
auto[536870912:671088639]	auto[0]	61	1			T29	1		T102	1		T24	1
auto[536870912:671088639]	auto[1]	39	1			T14	1		T79	1		T381	1
auto[671088640:805306367]	auto[0]	50	1			T64	1		T65	1		T69	1
auto[671088640:805306367]	auto[1]	56	1			T48	1		T64	1		T25	1
auto[805306368:939524095]	auto[0]	40	1			T36	1		T48	1		T113	1
auto[805306368:939524095]	auto[1]	46	1			T14	1		T29	2		T24	1
auto[939524096:1073741823]	auto[0]	39	1			T48	1		T122	1		T276	1
auto[939524096:1073741823]	auto[1]	42	1			T79	1		T102	1		T48	1
auto[1073741824:1207959551]	auto[0]	46	1			T19	1		T48	1		T25	1
auto[1073741824:1207959551]	auto[1]	48	1			T79	2		T58	1		T43	1
auto[1207959552:1342177279]	auto[0]	46	1			T14	2		T104	1		T68	1
auto[1207959552:1342177279]	auto[1]	54	1			T29	1		T249	1		T202	1
auto[1342177280:1476395007]	auto[0]	51	1			T79	1		T20	1		T43	1
auto[1342177280:1476395007]	auto[1]	45	1			T14	2		T104	1		T25	1
auto[1476395008:1610612735]	auto[0]	44	1			T28	1		T56	2		T224	1
auto[1476395008:1610612735]	auto[1]	62	1			T104	1		T29	1		T137	1
auto[1610612736:1744830463]	auto[0]	41	1			T14	1		T19	1		T20	1
auto[1610612736:1744830463]	auto[1]	37	1			T4	1		T184	1		T20	1
auto[1744830464:1879048191]	auto[0]	38	1			T14	1		T29	1		T48	1
auto[1744830464:1879048191]	auto[1]	52	1			T48	1		T52	1		T56	1
auto[1879048192:2013265919]	auto[0]	55	1			T79	1		T64	1		T7	1
auto[1879048192:2013265919]	auto[1]	50	1			T14	2		T64	1		T43	1
auto[2013265920:2147483647]	auto[0]	41	1			T48	1		T25	1		T56	1
auto[2013265920:2147483647]	auto[1]	52	1			T104	1		T32	1		T102	1
auto[2147483648:2281701375]	auto[0]	41	1			T4	2		T14	1		T48	1
auto[2147483648:2281701375]	auto[1]	53	1			T48	1		T64	1		T138	1
auto[2281701376:2415919103]	auto[0]	64	1			T16	1		T20	1		T27	1
auto[2281701376:2415919103]	auto[1]	44	1			T32	1		T65	1		T56	1
auto[2415919104:2550136831]	auto[0]	51	1			T29	1		T138	1		T139	1
auto[2415919104:2550136831]	auto[1]	48	1			T14	2		T29	2		T48	2
auto[2550136832:2684354559]	auto[0]	48	1			T102	1		T184	1		T89	1
auto[2550136832:2684354559]	auto[1]	61	1			T51	1		T184	1		T122	1
auto[2684354560:2818572287]	auto[0]	54	1			T68	1		T29	1		T189	1
auto[2684354560:2818572287]	auto[1]	49	1			T24	1		T223	1		T56	1
auto[2818572288:2952790015]	auto[0]	55	1			T79	1		T40	1		T139	1
auto[2818572288:2952790015]	auto[1]	51	1			T51	1		T64	1		T65	1
auto[2952790016:3087007743]	auto[0]	45	1			T65	1		T34	1		T98	1
auto[2952790016:3087007743]	auto[1]	55	1			T14	1		T29	2		T183	1
auto[3087007744:3221225471]	auto[0]	48	1			T29	2		T48	1		T189	1
auto[3087007744:3221225471]	auto[1]	53	1			T8	1		T271	1		T206	1
auto[3221225472:3355443199]	auto[0]	43	1			T68	1		T24	1		T25	1
auto[3221225472:3355443199]	auto[1]	57	1			T14	1		T104	1		T137	1
auto[3355443200:3489660927]	auto[0]	45	1			T103	1		T7	1		T276	1
auto[3355443200:3489660927]	auto[1]	63	1			T14	1		T64	1		T25	1
auto[3489660928:3623878655]	auto[0]	57	1			T104	1		T20	1		T76	1
auto[3489660928:3623878655]	auto[1]	44	1			T14	1		T29	1		T43	1
auto[3623878656:3758096383]	auto[0]	59	1			T14	1		T28	1		T68	1
auto[3623878656:3758096383]	auto[1]	67	1			T79	1		T104	1		T32	1
auto[3758096384:3892314111]	auto[0]	56	1			T68	1		T48	1		T64	1
auto[3758096384:3892314111]	auto[1]	47	1			T102	1		T137	1		T7	1
auto[3892314112:4026531839]	auto[0]	44	1			T28	1		T48	1		T189	1
auto[3892314112:4026531839]	auto[1]	61	1			T36	1		T48	1		T69	1
auto[4026531840:4160749567]	auto[0]	57	1			T18	1		T76	1		T276	1
auto[4026531840:4160749567]	auto[1]	45	1			T101	1		T48	1		T89	1
auto[4160749568:4294967295]	auto[0]	47	1			T14	2		T68	1		T29	1
auto[4160749568:4294967295]	auto[1]	59	1			T18	1		T137	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T4

2

T14

7

T16

3

auto[1]

1645

1

T4

1

T14

14

T18

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T104	1		T103	1		T65	1
auto[134217728:268435455]	87	1			T89	1		T65	1		T56	1
auto[268435456:402653183]	99	1			T48	1		T64	1		T20	1
auto[402653184:536870911]	106	1			T104	2		T29	1		T48	1
auto[536870912:671088639]	98	1			T4	2		T14	1		T48	1
auto[671088640:805306367]	105	1			T14	1		T29	2		T25	1
auto[805306368:939524095]	87	1			T102	1		T137	1		T48	2
auto[939524096:1073741823]	81	1			T102	1		T24	1		T137	1
auto[1073741824:1207959551]	80	1			T18	1		T36	1		T79	1
auto[1207959552:1342177279]	116	1			T68	1		T29	4		T64	1
auto[1342177280:1476395007]	108	1			T14	1		T24	2		T137	1
auto[1476395008:1610612735]	92	1			T14	1		T68	1		T48	1
auto[1610612736:1744830463]	120	1			T4	1		T14	2		T51	1
auto[1744830464:1879048191]	104	1			T14	3		T29	1		T32	1
auto[1879048192:2013265919]	113	1			T14	1		T28	1		T48	4
auto[2013265920:2147483647]	84	1			T20	2		T25	1		T182	1
auto[2147483648:2281701375]	98	1			T14	2		T16	1		T18	1
auto[2281701376:2415919103]	91	1			T14	1		T36	1		T29	1
auto[2415919104:2550136831]	109	1			T28	1		T51	1		T25	1
auto[2550136832:2684354559]	115	1			T79	1		T29	1		T51	1
auto[2684354560:2818572287]	115	1			T14	1		T79	1		T68	1
auto[2818572288:2952790015]	100	1			T79	1		T68	2		T184	1
auto[2952790016:3087007743]	108	1			T14	2		T79	1		T29	1
auto[3087007744:3221225471]	94	1			T104	1		T29	2		T48	3
auto[3221225472:3355443199]	95	1			T14	1		T28	1		T102	1
auto[3355443200:3489660927]	100	1			T14	1		T79	1		T58	1
auto[3489660928:3623878655]	91	1			T14	1		T68	1		T29	2
auto[3623878656:3758096383]	92	1			T184	1		T48	1		T25	1
auto[3758096384:3892314111]	81	1			T104	1		T68	1		T102	1
auto[3892314112:4026531839]	103	1			T14	2		T79	1		T28	1
auto[4026531840:4160749567]	117	1			T16	2		T104	1		T29	1
auto[4160749568:4294967295]	92	1			T29	2		T137	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T104	1		T103	1		T65	1
auto[0:134217727]	auto[1]	43	1			T385	1		T56	1		T98	1
auto[134217728:268435455]	auto[0]	45	1			T89	1		T407	1		T259	1
auto[134217728:268435455]	auto[1]	42	1			T65	1		T56	1		T98	1
auto[268435456:402653183]	auto[0]	50	1			T48	1		T20	1		T25	1
auto[268435456:402653183]	auto[1]	49	1			T64	1		T26	1		T7	1
auto[402653184:536870911]	auto[0]	47	1			T48	1		T189	1		T276	1
auto[402653184:536870911]	auto[1]	59	1			T104	2		T29	1		T65	2
auto[536870912:671088639]	auto[0]	45	1			T4	1		T48	1		T138	1
auto[536870912:671088639]	auto[1]	53	1			T4	1		T14	1		T53	1
auto[671088640:805306367]	auto[0]	58	1			T14	1		T27	1		T249	1
auto[671088640:805306367]	auto[1]	47	1			T29	2		T25	1		T138	2
auto[805306368:939524095]	auto[0]	36	1			T48	1		T89	1		T214	1
auto[805306368:939524095]	auto[1]	51	1			T102	1		T137	1		T48	1
auto[939524096:1073741823]	auto[0]	45	1			T137	1		T7	1		T56	1
auto[939524096:1073741823]	auto[1]	36	1			T102	1		T24	1		T122	2
auto[1073741824:1207959551]	auto[0]	37	1			T18	1		T79	1		T48	1
auto[1073741824:1207959551]	auto[1]	43	1			T36	1		T43	1		T89	1
auto[1207959552:1342177279]	auto[0]	69	1			T68	1		T29	2		T27	1
auto[1207959552:1342177279]	auto[1]	47	1			T29	2		T64	1		T25	1
auto[1342177280:1476395007]	auto[0]	46	1			T103	1		T7	1		T76	1
auto[1342177280:1476395007]	auto[1]	62	1			T14	1		T24	2		T137	1
auto[1476395008:1610612735]	auto[0]	51	1			T68	1		T48	1		T43	1
auto[1476395008:1610612735]	auto[1]	41	1			T14	1		T26	1		T65	1
auto[1610612736:1744830463]	auto[0]	60	1			T4	1		T14	1		T122	1
auto[1610612736:1744830463]	auto[1]	60	1			T14	1		T51	1		T408	1
auto[1744830464:1879048191]	auto[0]	45	1			T14	1		T29	1		T48	1
auto[1744830464:1879048191]	auto[1]	59	1			T14	2		T32	1		T69	1
auto[1879048192:2013265919]	auto[0]	59	1			T28	1		T48	1		T43	2
auto[1879048192:2013265919]	auto[1]	54	1			T14	1		T48	3		T89	1
auto[2013265920:2147483647]	auto[0]	35	1			T20	2		T40	1		T189	1
auto[2013265920:2147483647]	auto[1]	49	1			T25	1		T182	1		T44	1
auto[2147483648:2281701375]	auto[0]	45	1			T16	1		T79	1		T7	1
auto[2147483648:2281701375]	auto[1]	53	1			T14	2		T18	1		T104	1
auto[2281701376:2415919103]	auto[0]	39	1			T36	1		T29	1		T137	1
auto[2281701376:2415919103]	auto[1]	52	1			T14	1		T32	1		T48	2
auto[2415919104:2550136831]	auto[0]	48	1			T28	1		T56	2		T113	1
auto[2415919104:2550136831]	auto[1]	61	1			T51	1		T25	1		T183	1
auto[2550136832:2684354559]	auto[0]	58	1			T24	1		T48	1		T25	1
auto[2550136832:2684354559]	auto[1]	57	1			T79	1		T29	1		T51	1
auto[2684354560:2818572287]	auto[0]	61	1			T14	1		T79	1		T68	1
auto[2684354560:2818572287]	auto[1]	54	1			T65	3		T249	1		T223	1
auto[2818572288:2952790015]	auto[0]	48	1			T68	2		T189	3		T76	1
auto[2818572288:2952790015]	auto[1]	52	1			T79	1		T184	1		T138	1
auto[2952790016:3087007743]	auto[0]	46	1			T25	1		T281	1		T49	1
auto[2952790016:3087007743]	auto[1]	62	1			T14	2		T79	1		T29	1
auto[3087007744:3221225471]	auto[0]	41	1			T104	1		T29	1		T48	2
auto[3087007744:3221225471]	auto[1]	53	1			T29	1		T48	1		T53	1
auto[3221225472:3355443199]	auto[0]	40	1			T28	1		T102	1		T64	1
auto[3221225472:3355443199]	auto[1]	55	1			T14	1		T269	1		T45	1
auto[3355443200:3489660927]	auto[0]	44	1			T14	1		T58	1		T139	1
auto[3355443200:3489660927]	auto[1]	56	1			T79	1		T184	1		T40	1
auto[3489660928:3623878655]	auto[0]	50	1			T14	1		T68	1		T56	2
auto[3489660928:3623878655]	auto[1]	41	1			T29	2		T281	1		T49	1
auto[3623878656:3758096383]	auto[0]	38	1			T184	1		T25	1		T138	1
auto[3623878656:3758096383]	auto[1]	54	1			T48	1		T138	1		T189	1
auto[3758096384:3892314111]	auto[0]	42	1			T68	1		T19	1		T186	1
auto[3758096384:3892314111]	auto[1]	39	1			T104	1		T102	1		T64	1
auto[3892314112:4026531839]	auto[0]	48	1			T14	1		T28	1		T69	1
auto[3892314112:4026531839]	auto[1]	55	1			T14	1		T79	1		T184	1
auto[4026531840:4160749567]	auto[0]	56	1			T16	2		T104	1		T29	1
auto[4026531840:4160749567]	auto[1]	61	1			T184	1		T48	1		T339	1
auto[4160749568:4294967295]	auto[0]	47	1			T29	2		T20	1		T25	1
auto[4160749568:4294967295]	auto[1]	45	1			T137	1		T48	1		T67	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T4

2

T14

6

T16

3

auto[1]

1675

1

T4

1

T14

15

T18

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T79	1		T29	1		T20	1
auto[134217728:268435455]	97	1			T29	1		T48	2		T64	1
auto[268435456:402653183]	113	1			T16	1		T79	2		T68	1
auto[402653184:536870911]	100	1			T14	2		T36	1		T29	2
auto[536870912:671088639]	93	1			T28	1		T68	1		T137	1
auto[671088640:805306367]	91	1			T14	1		T281	1		T138	1
auto[805306368:939524095]	105	1			T104	1		T48	3		T43	1
auto[939524096:1073741823]	92	1			T14	1		T18	1		T79	1
auto[1073741824:1207959551]	96	1			T14	2		T65	2		T78	1
auto[1207959552:1342177279]	108	1			T18	1		T104	1		T68	1
auto[1342177280:1476395007]	115	1			T28	2		T68	1		T48	1
auto[1476395008:1610612735]	111	1			T68	1		T137	1		T48	1
auto[1610612736:1744830463]	96	1			T4	1		T104	1		T184	1
auto[1744830464:1879048191]	94	1			T58	1		T29	1		T51	1
auto[1879048192:2013265919]	88	1			T4	1		T14	2		T29	1
auto[2013265920:2147483647]	96	1			T16	1		T79	1		T51	1
auto[2147483648:2281701375]	102	1			T14	1		T29	1		T102	1
auto[2281701376:2415919103]	103	1			T19	1		T139	1		T7	1
auto[2415919104:2550136831]	101	1			T14	1		T28	1		T32	1
auto[2550136832:2684354559]	102	1			T14	1		T137	1		T48	1
auto[2684354560:2818572287]	102	1			T4	1		T14	1		T16	1
auto[2818572288:2952790015]	116	1			T14	1		T104	1		T29	1
auto[2952790016:3087007743]	116	1			T14	2		T29	1		T184	1
auto[3087007744:3221225471]	68	1			T29	2		T24	1		T48	1
auto[3221225472:3355443199]	98	1			T48	2		T89	1		T138	1
auto[3355443200:3489660927]	84	1			T14	1		T79	1		T68	1
auto[3489660928:3623878655]	108	1			T29	1		T24	1		T48	1
auto[3623878656:3758096383]	112	1			T14	1		T64	1		T26	1
auto[3758096384:3892314111]	99	1			T14	2		T64	1		T339	1
auto[3892314112:4026531839]	108	1			T29	1		T48	1		T64	2
auto[4026531840:4160749567]	87	1			T14	1		T79	1		T104	1
auto[4160749568:4294967295]	92	1			T14	1		T36	1		T79	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T20	1		T56	2		T224	1
auto[0:134217727]	auto[1]	48	1			T79	1		T29	1		T113	1
auto[134217728:268435455]	auto[0]	49	1			T29	1		T48	1		T189	1
auto[134217728:268435455]	auto[1]	48	1			T48	1		T64	1		T65	1
auto[268435456:402653183]	auto[0]	53	1			T16	1		T79	1		T68	1
auto[268435456:402653183]	auto[1]	60	1			T79	1		T51	1		T137	1
auto[402653184:536870911]	auto[0]	39	1			T48	1		T189	1		T56	2
auto[402653184:536870911]	auto[1]	61	1			T14	2		T36	1		T29	2
auto[536870912:671088639]	auto[0]	42	1			T28	1		T68	1		T189	1
auto[536870912:671088639]	auto[1]	51	1			T137	1		T48	1		T65	1
auto[671088640:805306367]	auto[0]	41	1			T281	1		T138	1		T7	1
auto[671088640:805306367]	auto[1]	50	1			T14	1		T40	1		T206	1
auto[805306368:939524095]	auto[0]	45	1			T48	2		T43	1		T25	1
auto[805306368:939524095]	auto[1]	60	1			T104	1		T48	1		T188	1
auto[939524096:1073741823]	auto[0]	49	1			T14	1		T79	1		T24	1
auto[939524096:1073741823]	auto[1]	43	1			T18	1		T102	1		T65	2
auto[1073741824:1207959551]	auto[0]	50	1			T14	1		T65	1		T78	1
auto[1073741824:1207959551]	auto[1]	46	1			T14	1		T65	1		T56	1
auto[1207959552:1342177279]	auto[0]	54	1			T18	1		T104	1		T68	1
auto[1207959552:1342177279]	auto[1]	54	1			T102	1		T24	1		T122	1
auto[1342177280:1476395007]	auto[0]	63	1			T28	2		T68	1		T48	1
auto[1342177280:1476395007]	auto[1]	52	1			T64	1		T20	1		T43	1
auto[1476395008:1610612735]	auto[0]	51	1			T68	1		T48	1		T89	1
auto[1476395008:1610612735]	auto[1]	60	1			T137	1		T122	1		T65	2
auto[1610612736:1744830463]	auto[0]	42	1			T4	1		T104	1		T184	1
auto[1610612736:1744830463]	auto[1]	54	1			T48	1		T65	2		T69	1
auto[1744830464:1879048191]	auto[0]	41	1			T48	1		T64	1		T138	1
auto[1744830464:1879048191]	auto[1]	53	1			T58	1		T29	1		T51	1
auto[1879048192:2013265919]	auto[0]	34	1			T29	1		T184	1		T25	1
auto[1879048192:2013265919]	auto[1]	54	1			T4	1		T14	2		T48	1
auto[2013265920:2147483647]	auto[0]	52	1			T16	1		T79	1		T51	1
auto[2013265920:2147483647]	auto[1]	44	1			T64	1		T43	1		T30	1
auto[2147483648:2281701375]	auto[0]	40	1			T98	2		T409	1		T97	1
auto[2147483648:2281701375]	auto[1]	62	1			T14	1		T29	1		T102	1
auto[2281701376:2415919103]	auto[0]	56	1			T19	1		T139	1		T7	1
auto[2281701376:2415919103]	auto[1]	47	1			T65	1		T223	1		T56	1
auto[2415919104:2550136831]	auto[0]	43	1			T28	1		T49	1		T223	1
auto[2415919104:2550136831]	auto[1]	58	1			T14	1		T32	1		T102	1
auto[2550136832:2684354559]	auto[0]	45	1			T14	1		T138	1		T139	1
auto[2550136832:2684354559]	auto[1]	57	1			T137	1		T48	1		T43	1
auto[2684354560:2818572287]	auto[0]	54	1			T4	1		T14	1		T16	1
auto[2684354560:2818572287]	auto[1]	48	1			T32	1		T184	1		T138	1
auto[2818572288:2952790015]	auto[0]	54	1			T102	1		T138	1		T103	1
auto[2818572288:2952790015]	auto[1]	62	1			T14	1		T104	1		T29	1
auto[2952790016:3087007743]	auto[0]	58	1			T184	1		T20	1		T122	1
auto[2952790016:3087007743]	auto[1]	58	1			T14	2		T29	1		T48	1
auto[3087007744:3221225471]	auto[0]	36	1			T29	1		T223	1		T56	3
auto[3087007744:3221225471]	auto[1]	32	1			T29	1		T24	1		T48	1
auto[3221225472:3355443199]	auto[0]	45	1			T48	1		T89	1		T286	1
auto[3221225472:3355443199]	auto[1]	53	1			T48	1		T138	1		T49	1
auto[3355443200:3489660927]	auto[0]	37	1			T68	1		T281	1		T83	1
auto[3355443200:3489660927]	auto[1]	47	1			T14	1		T79	1		T102	1
auto[3489660928:3623878655]	auto[0]	52	1			T29	1		T48	1		T7	1
auto[3489660928:3623878655]	auto[1]	56	1			T24	1		T89	1		T52	1
auto[3623878656:3758096383]	auto[0]	51	1			T14	1		T49	1		T27	1
auto[3623878656:3758096383]	auto[1]	61	1			T64	1		T26	1		T182	1
auto[3758096384:3892314111]	auto[0]	56	1			T64	1		T76	1		T224	1
auto[3758096384:3892314111]	auto[1]	43	1			T14	2		T339	1		T78	1
auto[3892314112:4026531839]	auto[0]	47	1			T64	1		T25	1		T65	1
auto[3892314112:4026531839]	auto[1]	61	1			T29	1		T48	1		T64	1
auto[4026531840:4160749567]	auto[0]	47	1			T14	1		T19	1		T43	1
auto[4026531840:4160749567]	auto[1]	40	1			T79	1		T104	1		T29	1
auto[4160749568:4294967295]	auto[0]	40	1			T36	1		T104	1		T29	1
auto[4160749568:4294967295]	auto[1]	52	1			T14	1		T79	1		T104	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1517

1

T4

2

T14

8

T16

3

auto[1]

1669

1

T4

1

T14

13

T18

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T104	1		T29	1		T122	1
auto[134217728:268435455]	101	1			T14	1		T48	1		T64	1
auto[268435456:402653183]	94	1			T14	1		T79	1		T104	1
auto[402653184:536870911]	102	1			T4	1		T79	3		T28	1
auto[536870912:671088639]	105	1			T14	1		T18	1		T68	1
auto[671088640:805306367]	104	1			T4	1		T36	1		T68	1
auto[805306368:939524095]	115	1			T184	1		T64	2		T89	1
auto[939524096:1073741823]	99	1			T14	1		T29	2		T25	1
auto[1073741824:1207959551]	92	1			T14	1		T18	1		T79	1
auto[1207959552:1342177279]	94	1			T14	1		T16	1		T104	1
auto[1342177280:1476395007]	95	1			T104	1		T52	1		T138	1
auto[1476395008:1610612735]	96	1			T36	1		T29	1		T48	1
auto[1610612736:1744830463]	97	1			T14	1		T29	2		T137	1
auto[1744830464:1879048191]	90	1			T137	1		T25	1		T139	1
auto[1879048192:2013265919]	108	1			T28	1		T184	1		T48	1
auto[2013265920:2147483647]	102	1			T14	1		T68	1		T102	1
auto[2147483648:2281701375]	103	1			T14	2		T68	1		T32	1
auto[2281701376:2415919103]	93	1			T14	1		T29	1		T32	1
auto[2415919104:2550136831]	115	1			T79	2		T51	1		T65	2
auto[2550136832:2684354559]	91	1			T14	3		T48	1		T25	1
auto[2684354560:2818572287]	95	1			T14	1		T16	1		T104	2
auto[2818572288:2952790015]	107	1			T48	2		T64	2		T20	1
auto[2952790016:3087007743]	100	1			T14	1		T68	1		T29	2
auto[3087007744:3221225471]	89	1			T101	1		T64	1		T25	2
auto[3221225472:3355443199]	105	1			T4	1		T68	1		T29	1
auto[3355443200:3489660927]	100	1			T29	2		T19	1		T48	2
auto[3489660928:3623878655]	107	1			T16	1		T48	4		T67	1
auto[3623878656:3758096383]	92	1			T14	1		T79	1		T28	1
auto[3758096384:3892314111]	97	1			T24	1		T48	1		T20	1
auto[3892314112:4026531839]	94	1			T14	1		T28	1		T104	1
auto[4026531840:4160749567]	114	1			T14	3		T68	1		T102	1
auto[4160749568:4294967295]	93	1			T184	1		T138	1		T76	1