Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2821

1

T4

3

T14

21

T16

3

auto[1]

268

1

T122

7

T138

6

T139

15

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T14	1		T36	1		T79	1
auto[134217728:268435455]	84	1			T104	1		T102	1		T137	1
auto[268435456:402653183]	97	1			T4	1		T29	1		T51	1
auto[402653184:536870911]	100	1			T68	1		T137	1		T184	1
auto[536870912:671088639]	90	1			T4	1		T26	1		T122	2
auto[671088640:805306367]	94	1			T137	1		T65	3		T78	1
auto[805306368:939524095]	97	1			T14	2		T68	1		T138	1
auto[939524096:1073741823]	93	1			T14	1		T79	1		T102	1
auto[1073741824:1207959551]	93	1			T18	1		T104	1		T137	1
auto[1207959552:1342177279]	98	1			T14	1		T29	2		T26	1
auto[1342177280:1476395007]	109	1			T14	1		T16	1		T36	1
auto[1476395008:1610612735]	90	1			T14	1		T18	1		T68	2
auto[1610612736:1744830463]	95	1			T14	1		T16	1		T79	1
auto[1744830464:1879048191]	99	1			T16	1		T28	1		T24	1
auto[1879048192:2013265919]	111	1			T14	2		T184	1		T25	1
auto[2013265920:2147483647]	104	1			T29	2		T43	1		T89	1
auto[2147483648:2281701375]	93	1			T79	1		T28	1		T104	1
auto[2281701376:2415919103]	99	1			T14	1		T48	5		T64	1
auto[2415919104:2550136831]	78	1			T14	1		T29	1		T122	1
auto[2550136832:2684354559]	88	1			T101	1		T29	1		T51	1
auto[2684354560:2818572287]	97	1			T14	1		T29	3		T102	1
auto[2818572288:2952790015]	86	1			T14	2		T28	1		T29	1
auto[2952790016:3087007743]	112	1			T79	1		T19	1		T48	2
auto[3087007744:3221225471]	97	1			T4	1		T48	1		T89	2
auto[3221225472:3355443199]	99	1			T184	1		T43	1		T49	1
auto[3355443200:3489660927]	96	1			T14	1		T79	1		T24	1
auto[3489660928:3623878655]	97	1			T14	2		T29	1		T32	1
auto[3623878656:3758096383]	85	1			T68	1		T26	1		T89	1
auto[3758096384:3892314111]	106	1			T14	1		T79	1		T104	1
auto[3892314112:4026531839]	100	1			T14	1		T68	1		T51	1
auto[4026531840:4160749567]	111	1			T28	1		T104	1		T29	1
auto[4160749568:4294967295]	92	1			T14	1		T79	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	86	1			T14	1		T36	1		T79	1
auto[0:134217727]	auto[1]	13	1			T107	2		T222	1		T400	1
auto[134217728:268435455]	auto[0]	78	1			T104	1		T102	1		T137	1
auto[134217728:268435455]	auto[1]	6	1			T139	2		T223	1		T330	1
auto[268435456:402653183]	auto[0]	91	1			T4	1		T29	1		T51	1
auto[268435456:402653183]	auto[1]	6	1			T350	1		T380	1		T297	1
auto[402653184:536870911]	auto[0]	96	1			T68	1		T137	1		T184	1
auto[402653184:536870911]	auto[1]	4	1			T400	1		T341	1		T415	1
auto[536870912:671088639]	auto[0]	80	1			T4	1		T26	1		T138	1
auto[536870912:671088639]	auto[1]	10	1			T122	2		T139	1		T247	1
auto[671088640:805306367]	auto[0]	88	1			T137	1		T65	3		T78	1
auto[671088640:805306367]	auto[1]	6	1			T107	1		T229	1		T308	1
auto[805306368:939524095]	auto[0]	86	1			T14	2		T68	1		T183	1
auto[805306368:939524095]	auto[1]	11	1			T138	1		T340	2		T332	1
auto[939524096:1073741823]	auto[0]	84	1			T14	1		T79	1		T102	1
auto[939524096:1073741823]	auto[1]	9	1			T122	2		T139	1		T380	1
auto[1073741824:1207959551]	auto[0]	86	1			T18	1		T104	1		T137	1
auto[1073741824:1207959551]	auto[1]	7	1			T122	1		T107	1		T247	1
auto[1207959552:1342177279]	auto[0]	88	1			T14	1		T29	2		T26	1
auto[1207959552:1342177279]	auto[1]	10	1			T138	2		T139	1		T223	1
auto[1342177280:1476395007]	auto[0]	100	1			T14	1		T16	1		T36	1
auto[1342177280:1476395007]	auto[1]	9	1			T247	1		T341	1		T411	2
auto[1476395008:1610612735]	auto[0]	85	1			T14	1		T18	1		T68	2
auto[1476395008:1610612735]	auto[1]	5	1			T247	1		T332	1		T399	1
auto[1610612736:1744830463]	auto[0]	82	1			T14	1		T16	1		T79	1
auto[1610612736:1744830463]	auto[1]	13	1			T139	1		T400	1		T332	1
auto[1744830464:1879048191]	auto[0]	89	1			T16	1		T28	1		T24	1
auto[1744830464:1879048191]	auto[1]	10	1			T139	1		T223	1		T332	2
auto[1879048192:2013265919]	auto[0]	102	1			T14	2		T184	1		T25	1
auto[1879048192:2013265919]	auto[1]	9	1			T138	1		T247	1		T400	2
auto[2013265920:2147483647]	auto[0]	96	1			T29	2		T43	1		T89	1
auto[2013265920:2147483647]	auto[1]	8	1			T139	1		T247	1		T341	1
auto[2147483648:2281701375]	auto[0]	82	1			T79	1		T28	1		T104	1
auto[2147483648:2281701375]	auto[1]	11	1			T340	1		T402	1		T403	1
auto[2281701376:2415919103]	auto[0]	89	1			T14	1		T48	5		T64	1
auto[2281701376:2415919103]	auto[1]	10	1			T139	2		T223	1		T340	1
auto[2415919104:2550136831]	auto[0]	74	1			T14	1		T29	1		T122	1
auto[2415919104:2550136831]	auto[1]	4	1			T400	1		T340	1		T229	1
auto[2550136832:2684354559]	auto[0]	82	1			T101	1		T29	1		T51	1
auto[2550136832:2684354559]	auto[1]	6	1			T402	1		T341	2		T229	1
auto[2684354560:2818572287]	auto[0]	91	1			T14	1		T29	3		T102	1
auto[2684354560:2818572287]	auto[1]	6	1			T139	1		T223	1		T321	1
auto[2818572288:2952790015]	auto[0]	83	1			T14	2		T28	1		T29	1
auto[2818572288:2952790015]	auto[1]	3	1			T332	1		T373	1		T416	1
auto[2952790016:3087007743]	auto[0]	101	1			T79	1		T19	1		T48	2
auto[2952790016:3087007743]	auto[1]	11	1			T139	1		T223	1		T225	1
auto[3087007744:3221225471]	auto[0]	89	1			T4	1		T48	1		T89	2
auto[3087007744:3221225471]	auto[1]	8	1			T139	1		T223	1		T332	1
auto[3221225472:3355443199]	auto[0]	93	1			T184	1		T43	1		T49	1
auto[3221225472:3355443199]	auto[1]	6	1			T225	1		T247	1		T403	1
auto[3355443200:3489660927]	auto[0]	86	1			T14	1		T79	1		T24	1
auto[3355443200:3489660927]	auto[1]	10	1			T139	1		T223	1		T400	1
auto[3489660928:3623878655]	auto[0]	91	1			T14	2		T29	1		T32	1
auto[3489660928:3623878655]	auto[1]	6	1			T321	1		T340	1		T380	1
auto[3623878656:3758096383]	auto[0]	77	1			T68	1		T26	1		T89	1
auto[3623878656:3758096383]	auto[1]	8	1			T107	1		T321	1		T332	1
auto[3758096384:3892314111]	auto[0]	99	1			T14	1		T79	1		T104	1
auto[3758096384:3892314111]	auto[1]	7	1			T122	1		T107	1		T406	1
auto[3892314112:4026531839]	auto[0]	87	1			T14	1		T68	1		T51	1
auto[3892314112:4026531839]	auto[1]	13	1			T321	1		T332	1		T242	1
auto[4026531840:4160749567]	auto[0]	96	1			T28	1		T104	1		T29	1
auto[4026531840:4160749567]	auto[1]	15	1			T138	1		T107	5		T340	1
auto[4160749568:4294967295]	auto[0]	84	1			T14	1		T79	1		T29	1
auto[4160749568:4294967295]	auto[1]	8	1			T122	1		T138	1		T139	1